CN101460654A - 使用含碳的硅薄膜形成超浅接合区的方法 - Google Patents
使用含碳的硅薄膜形成超浅接合区的方法 Download PDFInfo
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- CN101460654A CN101460654A CNA2007800158687A CN200780015868A CN101460654A CN 101460654 A CN101460654 A CN 101460654A CN A2007800158687 A CNA2007800158687 A CN A2007800158687A CN 200780015868 A CN200780015868 A CN 200780015868A CN 101460654 A CN101460654 A CN 101460654A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D—PROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D3/00—Pretreatment of surfaces to which liquids or other fluent materials are to be applied; After-treatment of applied coatings, e.g. intermediate treating of an applied coating preparatory to subsequent applications of liquids or other fluent materials
- B05D3/02—Pretreatment of surfaces to which liquids or other fluent materials are to be applied; After-treatment of applied coatings, e.g. intermediate treating of an applied coating preparatory to subsequent applications of liquids or other fluent materials by baking
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
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- C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
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Abstract
提供一在基板上形成超浅接合区的方法。某些实施例中提供一在基板上形成超浅接合区的方法。基板置于处理腔内。在基板上沉积硅碳层。将硅碳层暴露给掺杂物。基板被加热至超过950℃的温度,以便引发硅碳层中掺杂物的实质退火。某些实施例中,基板被加热至大约1000℃与1100℃之间的温度。某些实施例中,基板被加热至大约1030℃与1050℃之间的温度。某些实施例中提供一具有陡峭p-n接合区的结构。
Description
技术领域
本发明的实施例大致相关于半导体组件与其制造方法,而明确地,关于场效晶体管(Field Effect Transistor,FET)组件中超浅接合区的制造方法。
背景技术
极大规模集成电路(Ultra-large-scale integrated,ULSI)通常包含超过百万个的晶体管形成于一半导体基板上,且该些晶体管可协同执行电子组件中不同的功能。此类晶体管可能包括互补式金氧半导体(complementarymetal-oxide-semiconductor,CMOS)、场效晶体管与金氧半场效晶体管(metaloxide semiconductor field effect transistors,MOSFET)。
CMOS晶体管包括一栅极结构(gate structure),其配置在半导体基板界定的源极(source)区与漏极(drain)区之间。栅极结构通常包括一形成在栅极介电材质(gate dielectric material)上的栅电极(gate electrode)。栅电极调控电荷载子(charge carrier)的流动以便接通或截断晶体管,该流动位于栅极介电层之下且形成于漏极区与源极区之间的沟道区域(channel region)中。沟道、漏极与源极区域在技术中一同被视为「晶体管接合区」。为了帮助此类晶体管操作速度的增加,持续存在着降低晶体管接合区尺寸的趋势。
栅极通常以掺杂多晶硅(polysilicon,Si)形成,而栅极介电材质可能包含一由诸如二氧化硅(SiO2)或掺氮二氧化硅等等高介电常数材质(例如,高于4.0的界电常数)所组成的薄膜(例如,小于20)。
可藉由利用离子布植处理界定半导体基板中的源极与漏极区来制造CMOS晶体管。然而,较小尺寸的晶体管接合区必须先形成浅纵深(例如,100至500之间的纵深)的源极与漏极区。此类超浅接合区需要陡峭的接合区,但因为离子穿隧效应(ion-channeling)与瞬间增益扩散(transient enhanced diffusion,TED)现象,是难以利用离子布植技术形成陡峭接合区。由于掺杂物与过量的硅(晶格间)之间的交互作用,掺杂物在布植后退火(annealing)过程中经历极度增益扩散或瞬间增益扩散。此增益扩散导致更深的源极/漏极接合区与更差的接合区分布(junctionprofile)。
许多方法已经试着在形成超浅接合区时减少瞬间增益扩散。一个制造超浅晶体管接合区的方法称为同步布植碳(carbonco-implantation)法,此法中碳与掺杂物(例如硼)被同步植入。虽然同步布植碳法可成功地减少瞬间增益扩散,但同步布植碳法需承受在薄膜中产生大量点缺陷(point defects)的不利条件。
另一方法利用同步布植氟去减少退火过程中的瞬间增益扩散。然而,此法亦需承受与同步布植碳法相同的不利条件,例如退火过程后仍存在的点缺陷。
因此,需要一种制造场效晶体管超浅接合区的改良方法。
发明内容
本发明大致相关于一种场效晶体管组件的超浅接合区的制造方法。某些实施例中提供在基板上形成超浅接合区的方法。基板被置入处理腔中。硅碳层(siliconcarbon layer)被沉积在基板上。硅碳层暴露于掺杂物之下。基板被加热至超过950℃的温度,以便促使硅碳层中的掺杂物实质退火。某些实施例中,基板被加热至大约1000℃至1100°之间的温度。某些实施例中,基板被加热至大约1030℃至1050°之间的温度。
某些实施例中,提供在基板表面形成超浅接合区的方法。基板被置入处理腔中。硅碳外延层被沉积在基板上。掺杂物被植入硅碳层中。基板被加热至超过950℃的温度。某些实施例中,利用浸没式等离子体离子布植处理(plasmaimmersion ion implantation process)将掺杂物植入硅碳层中。某些实施例中,在加热基板超过950℃之后,硅碳层上部的可置换碳(substitutuional carbon)浓度低于硅碳层下部的可置换碳浓度。
某些实施例中,提供一具有陡峭p-n接合区的结构。此结构包括一半导体基板。此结构更包括一在沉积的硅碳外延层由离子布植所界定的源极区与漏极区。此结构更包括一具有一栅极结构位于其上的沟道区域,该栅极结构包括栅极与介电层。某些实施例中,陡峭的p-n接合区具有大约3nm/decade的掺杂物分布。
上文已相当概括地描述本发明的特征与技术优点,为了可以更加理解接下的本发明的详细描述。本发明的额外特征与优点会描述于之后的本发明申请专利范围内。熟悉技术的人士可以理解,其可轻易地利用所揭露的概念与实施例当作基础,来修改或设计其它完成与本发明相同目的的结构或处理。熟悉技术的人士亦可以理解,此类相等的意涵并不悖离所附专利申请范围提出的本发明的精神与范围外。
附图说明
为了以更加详细的方式了解本发明上述特征,简短地概括于发明内容的本发明更特定的描述,可以参照实施例来执行,其中某些实施例描述于附图中。然而值得注意的是附图仅描述此发明典型的实施例,并不会因而视为其范围的限制因素,好让本发明可以包含其它相等功效的实施例。
图1描述一种根据叙述于此文中的某些实施例的在基板上形成一超浅接合区的示范处理流程;
图2A-2E描述金氧半场效晶体管中源极/漏极延展组件的制造技术;
图3A-3C描述许多藉由应用叙述于此文中的实施例的包含选择性沉积的含硅外延层的组件;
图4描述沉积后(对照组)与突发式退火处理后的硅碳外延薄膜的高分辨率X光绕射仪(HR-XRD)频谱的标示图;
图5描述沉积后(对照组)、布植后与布植后/退火处理后的硅碳外延薄膜的高分辨率X光绕射仪频谱的标示图;以及
图6描述布植后/退火处理后的硅碳薄膜的碳与磷的二次离子质谱仪(Secondary Ion Mass Spectroscopy,SIMS)纵深分布的标示图。
主要组件符号说明:
100示范处理顺序 110、120、130、140 步骤
230、310、330 基板 232、312 源极/漏极区
234、244、316 间隙壁 235、318 栅极氧化层
236、322 栅极 238 凹处
240、314、334 含硅外延层 242 选择性的多晶层
248 增厚层 313 含硅层
319 保护层 320、338 偏置层
332 集极层 333、340 绝缘层
336 接触层 400、500、600 标示图
402、502 对照组
突发式退火处理后的硅碳外延薄膜
504 布植后的硅碳外延薄膜
506 布植后/退火处理后的硅碳外延薄膜
对照样本 604 碳的纵深分布
606 磷的纵深分布
具体实施方式
列举于专利申请范围中的本发明的实施例大致提供一种形成基板表面上的超浅接合区的方法。基板被置入处理腔中。硅碳层被沉积在基板表面上。硅碳层暴露给掺杂物。基板被加热至超过950℃的温度,以便导致掺杂物的实质退火反应发生于硅碳层中。
整个说明书中,「含硅(silicon-containing)」一词的材质、化合物、薄膜或层需理解为包括一至少含有硅且可能包含锗、碳、硼、砷、磷、镓与/或铝的合成物。其它诸如金属、卤素或氢等元素可能并入含硅材质、化合物、薄膜或层中,此些元素通常处于百万分之(part permillion,ppm)的浓度。含硅材质的化合物或合金会以缩写表示,诸如Si代表硅、SiGe代表硅锗、SiC代表硅碳且SiGeC代表硅锗碳。缩写既不代表具有化学计量关系的化学方程式,也不代表含硅材质任何特定的还原/氧化态。
图1描述一种形成基板上超浅接合区的示范处理顺序100。步骤110中,基板被置入处理腔中。步骤120中,沉积硅碳层于基板上。步骤130中,硅碳层暴露于掺杂物中。步骤140中,基板被加热至超过950℃的温度,以便导致掺杂物的实质退火反应发生于硅碳层中。
步骤110中,基板被置入处理腔中。步骤110的基板可以是图案基板(patterned substrate)。图案基板包括电子特征(形成于基板表面之内或之上)的基板。图案基板可能包含单晶表面与至少一不是单晶的第二表面(例如,多晶或非晶表面)。单晶表面包括裸晶基板(bare crystalline substrate)或沉积的单一结晶层(通常以诸如硅、硅锗、硅碳等材质形成)。多晶或非晶表面可能包括介电材质(诸如氧化物或氮化物,特别是氧化硅或氮化硅)与非晶硅表面。
步骤120中,沉积硅碳层于基板上。利用外延处理来沉积步骤120的硅碳层。通常,处理腔在整个外延处理中维持在一恒定的温度中。然而,某些步骤会执行于变动的温度中。处理腔维持在大约250℃至1,000℃范围之间内的温度,较佳的温度为大约500℃至800℃之间,且更佳的温度为大约550℃至750℃之间。实施外延处理的适当温度取决于特定前驱物(用来沉积与/或蚀刻含硅材质)。一实例中,已发现对于含硅材质而言,相对于使用较常见蚀刻剂的处理,氯气(Cl2)可在较低的温度下扮演相当成功的蚀刻剂。因此,一实例中,预先加热该处理腔的较佳温度大约或低于750℃,较佳的温度为大约或低于650℃,且更佳的温度为大约或低于550℃。处理腔通常维持在大约0.1Torr至200Torr之间的压力下,较佳的压力为大约1Torr至50Torr之间。在此沉积步骤之中与之间,压力可能出现波动,但通常是固定的。
在步骤120的沉积处理中,基板暴露给沉积气体好在单晶表面上形成外延层同时在第二层上形成多晶层。基板暴露给沉积气体一段大约0.5秒至30秒的时间,较佳的时间为大约1秒至20秒,且更佳的时间为大约5秒至10秒。沉积处理的特定暴露时间决定于蚀刻处理的暴露时间、特定前驱物与处理使用的温度。一般而言,基板暴露于沉积气体中长达足以形成最大厚度的外延且同时形成最小厚度的多晶层(在沉积步骤120中可以容易地蚀刻掉)。
沉积气体至少包括一硅源、一携带气体与一碳源。某些实施例中,沉积气体可能至少包括一蚀刻剂(诸如氯化氢或氯)。
通常以大约5sccm至500sccm范围之间的速度提供硅源进入处理腔内,较佳的速度为大约10sccm至300sccm之间,且更佳的速度为大约50sccm至200sccm之间(例如,大约100sccm)。有用于沉积气体(沉积含硅化合物)的硅源包括硅烷类(silanes)、卤化硅烷类(halogenated silanes)与有机硅烷类(organosilanes)。硅烷类包括硅烷(SiH4)与具有实验式SixH(2x+2)等较高的硅烷类,诸如二硅烷(Si2H6)、三硅烷(Si3H8)与四硅烷(Si4H10)等等。卤化硅烷类包括具有实验式X’ySixH(2x+2-y)的化合物,其中X’可以是氟、氯、溴或碘,诸如六氯二硅烷(Si2C16)、四氯硅烷(SiC14)、二氯硅烷(C12SiH2)与三氯硅烷(Cl3SiH)。有机硅烷类包括具有实验式RySixH(2x+2-y)的化合物,其中R可以是甲基、乙基、丙基或丁基,诸如甲基硅烷((CH3)SiH3)、二甲基硅烷((CH3)2SiH2)、三甲基硅烷((CH3)3SiH))、乙基硅烷((CH3CH2)SiH3)甲基二硅烷((CH3)Si2H5)、二甲基二硅烷((CH3)2Si2H4)与六甲基二硅烷((CH3)6Si2)。已发现有机硅烷化合物是有益的硅源,如同将碳并入沉积的含硅化合物实施例中的碳源一样。
通常一起提供硅源与携带气体进入处理腔内。携带气体的流速大约1slm(standard liters per minute,公升/分钟)至100slm之间,较佳的流速为大约5slm至75slm之间,且更佳的流速为大约10slm至50slm之间(例如,约25slm)。携带气体可能包括氮(N2)、氢(H2)、氩、氦与上述的混合物。惰性携带气体是较佳的携带气体,且其包括氮、氩、氦与上述的混合物。携带气体基于外延处理中使用的前驱物与/或处理温度而挑选。通常携带气体在各个步骤中是一样的。然而,某些实施例可能在特定的步骤中利用不同的携带气体。
以低温(例如,低于800℃)处理为其特色的实施例中,最好是利用氮作为携带气体。低温处理的可以使用一部分归因于在蚀刻处理中氯气的应用。氮在低温沉积处理中保持惰性。因此在低温处理中,并不会将氮并入沉积的含硅材质中。再者,氮携带气体不会形成如同氢携带气体所形成的氢端面(hydrogen-terminatedsurfaces)。藉由在基板表面上吸收氢携带气体而形成的氢端面,抑制含硅层的成长速度。最后,由于氮远比氢、氩或氦便宜,低温处理会因为氮的经济优点而采取氮作为携带气体。
步骤120中提供给处理腔的碳源与硅源和携带气体一起形成含硅化合物,例如硅碳材质通常以大约0.1sccm至20sccm范围内的速度提供进入处理腔,较佳的速度为大约0.5sccm至10sccm之间,而更佳的速度为大约1sccm至5sccm之间,例如约2sccm。用来沉积含硅化合物的碳源包括乙基、丙基与丁基的有机硅烷类、烷基类、烯类与炔类。上述的碳源包括甲基硅烷(methylsilane,CH3SiH3)、二甲基硅烷(dimethylsilane,(CH3)2SiH2)、三甲基硅烷(trimethylsilane,(CH3)3SiH))、乙基硅烷(ethylsilane,CH3CH2SiH3)、甲烷(methane,CH4)、乙烯(ethylene,C2H4)、乙炔(ethyne,C2H2)、丙烷(propane,C3H8)、丙烯(propene,C3H6)、丁炔(butyne,C4H6)等等。外延层的碳浓度在大约200ppm至5at.%(原子百分比)范围之内,较佳的浓度为大约1at.%至3at.%之间,例如1.5at.%。某些实施例中,单一外延层内的碳浓度可能是渐次变化的,最好以外延层较低的部分比外延层较高的部分具有较高的碳浓度而渐次变化。或者,锗源与碳源可能同时在步骤120时加入处理腔内,与硅源和携带气体一起形成含硅化合物,例如硅锗碳材质。
停止沉积处理。一实例中,处理腔会以洁净气体或携带气体注满,与/或以真空泵浦排空处理腔。清洁与/或排空处理移除过剩的沉积气体、反应副产品与其它污染物。另一实例中,一但已停止沉积处理,不需要清洁与/或排空处理腔立即开始蚀刻处理。
可以执行另一选择的蚀刻处理。蚀刻处理从基板表面移除在步骤120中沉积的含硅材质。蚀刻处理将外延(或单晶)材质与非晶(或多晶)材质两者皆移除。若有任何沉积在基板表面的多晶层,其将会以比外延层更快的速度被移除。蚀刻处理的持续时间与沉积处理的持续时间相抵,以得到选择性形成在基板所欲区域的外延层的最终沉积。因此,步骤120中的沉积处理与蚀刻处理的最终效果除了形成选择性与外延成长的含硅材质,同时减少(若有的话)含硅材质的多晶成长。
在蚀刻处理中,基板暴露给蚀刻气体的时间范围大约是1秒至90秒之间,较佳的时间范围为大约2秒至30秒之间,而更佳的时间范围为大约4秒至10秒之间。蚀刻气体至少包括一蚀刻剂与一携带气体。通常蚀刻剂以大约10sccm至700sccm范围之间的速度提供进入处理腔,较佳的速度为大约50sccm至500sccm之间,而更佳的速度为大约100sccm至400sccm之间,例如大约200sccm。应用于蚀刻气体内的蚀刻剂可能包括氯(Cl2)、氯化氢(HCl)、三氯化硼(BCl3)、氯甲烷(CH3Cl)、四氯化碳(CCl4)、三氟化氯(ClF3)与上述的混合物。最好是利用氯或氯化氢作为蚀刻剂。
蚀刻剂通常与一携带气体共同提供进入处理腔内。携带气体具有大约1slm至100slm范围之间的流速,较佳的流速大约5slm至75slm之间,而更佳的流速大约10slm至50slm之间,例如大约25slm。携带气体可能包括氮(N2)、氢(H2)、氩、氦与上述的混合物。某一实施例中,较倾向惰性的携带气体,其包括氮、氩、氦与上述的混合物。可基于外延处理时特定前驱物与/或温度来挑选携带气体。通常利用相同的携带气体于各个步骤中。然而,某些实施例在蚀刻处理中会应用一不同于沉积处理中所用的携带气体。某些实施例中,较佳的蚀刻剂氯气,特别是当交替气体供应(alternating gas supply,AGS)处理执行在低温(例如,<800℃)下时。例如,一包含氯(作为蚀刻剂)与氮(作为携带气体)的蚀刻气体在大约500℃至750℃范围之内的温度下接触基板表面。另一实例中,包含氯与氮的蚀刻气体在大约250℃至500℃范围之内的温度下接触基板表面。
停止蚀刻处理。一实例中,处理腔会以洁净气体或携带气体注满,与/或以真空泵浦排空处理腔。清洁与/或排空处理移除过剩的蚀刻气体、反应副产品与其它污染物。另一实例中,一但已停止蚀刻处理,不需要清洁与/或排空处理腔立即开始增加外延层的厚度。
外延层与多晶层的厚度可以决定的。假如达到预定的厚度,那么就停止了外延处理。然而,假如尚未达到预定的厚度,那么以一周期重复沉积处理直到达到预定的厚度。通常外延层成长至具有大约10至2,000范围之间的厚度,较佳的厚度为大约100至1,500之间,而更佳的厚度为大约400至1,200之间,例如大约800。若有的话,多晶层通常沉积在原子层至大约500范围之间的厚度内。含硅外延层或含硅多晶层所欲或是预定的厚度特定于独特制程。一实例中,外延层可以达到预定的厚度然而多晶层却太厚了。
步骤130中,硅碳薄膜暴露给一掺杂物。典型的掺杂物可能至少包括一掺杂化合物,好提供诸如硼、砷、磷、镓或铝等元素掺杂物的来源。掺杂物提供沉积的含硅化合物许多传导特性,例如电子组件所需的方向性电子流(在受到调控与所欲路径内)。含硅化合物的薄膜以特定掺杂物掺杂以达到所欲的传导特性。某些实施例中,含硅化合物以P型掺杂,例如藉由利用二硼烷(diborane)来增加硼的浓度到达大约1015原子数/立方厘米至1021原子数/立方厘米范围之间。某些实施例中,P型掺杂物具有至少5×1019原子数/立方厘米的浓度。某些实施例中,P型掺杂物的浓度大约1×1020原子数/立方厘米至2.5×1021原子数/立方厘米之间。某些实施例中,含硅化合物以N型掺杂,例如以磷与/或砷掺杂至大约1015原子数/立方厘米至1021原子数/立方厘米范围之间的浓度。
在步骤130中,掺杂物源通常以大约0.1sccm至20sccm范围之间的速度提供进入处理腔内,较佳的速度为大约0.5sccm至10sccm之间,而更佳的速度为大约1sccm至5sccm之间,例如大约2sccm。有用于掺杂物源的含硼掺杂物包括硼烷类(boranes)与有机硼烷类(organoboranes)。硼烷类包括硼烷(borane)、二硼烷(B2H6)、三硼烷(triborane)、四硼烷(tetraborane)与五硼烷(pentaborane),而烷基硼烷类(alkylboranes)包括具有RxBH(3-x)实验式的化合物,其中R可以为甲基、乙基、丙基或丁基而x可以为1、2或3。烷基硼烷类包括三甲基硼烷(trimethylborane,(CH3)3B)、二甲基硼烷(dimethylborane,(CH3)2BH)、三乙基硼烷(triethylborane,(CH3CH2)3B)与二乙基硼烷(diethylborane,(CH3CH2)2BH)。掺杂物亦可包括胂(AsH3)、膦(PH3)与烷基膦类(alkylphosphines),例如具有RxPH(3-x)实验式的化合物,其中R可以为甲基、乙基、丙基或丁基而x可以为1、2或3。烷基膦类包括三甲基膦(trimethylphosphine,(CH3)3P)、二甲基膦(dimethylphosphine,(CH3)2PH)、三乙基膦(triethylphosphine,(CH3CH2)3P)与二乙基膦(diethylphosphine,(CH3CH2)2PH)。铝和镓掺杂物源可以包括烷基化与/或卤素化的衍生物,例如以实验式RxMX(3-x)描述的化合物,其中M可以为铝或镓,R可以为甲基、乙基、丙基或丁基,X可以为氯或氟而x可以为0、1、2或3。铝或镓掺杂物源的实例包括三甲基铝(trimethylaluminum,Me3Al)、三乙基铝(triethylaluminum,Et3Al)、二甲基氯化铝(dimethylaluminumchloride,Me2AlCl)、氯化铝(aluminum chloride,AlCl3)、三甲基镓(trimethylgallium,Me3Ga)、三乙基镓(triethylgallium,Et3Ga)、二甲基氯化镓(dimethylgalliumchloride,Me2GaCl)与氯化镓(galliumchloride,GaCl3)。
某些实施例中,掺杂物可以经由例如离子布植法的处理引进。某些实施例中,砷以5 X 1014 and 1 X 1015之间的份量在0.7keV(千电子伏特)至1keV之间植入。某些实施例中,磷以5 X 1014至1 X 1015之间的份量在1keV下植入。某些实施例中,硼以5 X 1014至1 X 1015之间的份量在0.5keV下植入。离子布植法可以用来形成诸如源极与漏极的掺杂物区。在本实例中,掺杂物区的厚度可以是非常薄。例如,掺杂物区的厚度可以低于300。掺杂浓度可以低于或等于或高于1 X 1020原子数/立方厘米,而掺杂份量大约是1.5 X 1015cm-2。
某些实施例中,可用浸没式等离子体离子布植法来执行离子布植。浸没式等离子体离子布植法可能包括一处理,其中电极层暴露给等离子体源,而外加偏压会应用在基板上。执行浸没式等离子体离子布植的处理工具可能包括单一与/或一组晶圆反应器,其中可以应用直流电(direct current,DC)与/或射频(radiofrequency,RF)偏压在基板上。浸没式等离子体离子布植反应器包括在0.01mTorr至大约1000Torr范围之间的处理周围压力。基板保持在150℃至1100℃范围之间的温度下。可藉由微波电子回旋共振(electron cyclotron resonance,ECR)等离子体、螺旋式等离子体(helicon plasma)、感应耦合等离子体(inductivelycoupled plasma)与/或其它高密度等离子体源产生高密度等离子体。电将可至少包括氩、氢、氮、氙、氧、砷、二硼烷、氢化锗(GeH4)、磷与/或其它杂质源。例如,螺旋式等离子体会利用大约200Watts至2500Watts范围之间的射频功率。外加偏压会位于大约+200V至500V之间。浸没式等离子体离子布植法的其它态样讨论于2005年5月17日提出且命名为“利用浸没式等离子体离子布植法来进行绝缘体上硅的结构的制造”(一般标示为美国专利申请案第6,893,907号),其以参考方式于此并入本文中,但其不与当前的说明书与申请专利范围相抵触。
步骤140中,在基板上执行一退火(annealing)处理。可以实施退火处理来活化与恢复离子布植所引发的损坏。退火处理可以包括一快速热处理(rapid thermalprocess,RTP)、固态外延的重新结晶、雷射退火与或突发式退火(spikeannealing)。退火温度取决于应用的处理。某些实施例中,突发式退火执行于高于950℃的温度下。例如,突发式退火会具有大约1000℃至1100℃范围之间的温度,例如1030℃至1050℃之间,较佳的温度为大约1050℃,然而固态外延会执行在500℃或更低的温度下。
一较佳的实施例中,突发式退火执行于快速热处理系统中,此系统能够维持退火处理周围的气体压力在明显低于大气压力的程度下。此类快速热处理系统的一实例为位于Santa Clara,California的Applied Materials,Inc.商业上提供的RADIANCE CENTURA系统。突发式退火更近一步讨论于2005年5月24日提出且命名为“用于超浅接合区的突发式退火处理的进步”(一般标示为美国专利申请案第6,897,131号),与2004年10月12日提出且命名为“最理想的突发式退火的周围”(一般标示为美国专利申请案第6,803,297号),上述的案例以参考方式于此并入本文中,但其不与当前的说明书与申请专利范围相抵触。
一实例中,如同绘示于图2A-2E中,源极/漏极的延展形成在金氧半场效晶体管组件中,其中含硅层外延式与选择性地沉积在基板表面。图2A绘示藉由布植离子进入基板230的表面而形成源极/漏极区232。源极/漏极区232的部分以形成在栅极氧化层(gate oxide layer)235上的栅极236与间隙壁(spacer)234而连结。为了形成源极/漏极延展,源极/漏极区232的部分被蚀刻与潮式清洗(wet-cleaned)以产生如图2B中的凹处238。在源极/漏极区232的部分被蚀刻之前,藉由沉积硬质罩幕层(hardmask)可避免栅极236的蚀刻。
第2C图描述此文中叙述的外延处理的一实施例,其中含硅外延层240与选择性多晶层242同时且选择性地沉积(不沉积在间隙壁234上)。藉由调整外延处理中的沉积与蚀刻处理而选择性地将多晶层242形成于栅极236上。或者,当外延层240沉积在源极/漏极区232上时,持续地从栅极236上蚀刻掉多晶层242。
另一实例中,含硅外延层240与多晶层242是含硅锗层,其具有大约1at.%至50at.%范围之间的锗浓度,较佳为大约24at.%或更少。多层含硅锗层包含变化数量的硅与锗,其以逐次变化的元素浓度堆栈来形成含硅外延层240。例如,可以大约15at.%至25at.%范围之间的锗浓度来沉积第一硅锗层,而可以大约25at.%至35at.%范围之间的锗浓度来沉积第二硅锗层。
另一实例中,含硅外延层240与多晶层242是含硅碳(SiC)层,其具有大约200ppm至5at.%范围之间的碳浓度,较佳为大约3at.%或更少,较佳地,从大约1at.%至2at.%之间,例如大约1.5at.%。另一实施例中,含硅外延层240与多晶层242是硅锗碳(SiGeC)层,其具有大约1at.%至50at.%范围之间的锗浓度,较佳为大约24at.%或更少,以及大约200ppm至5at.%范围之间的碳浓度,较佳为大约3at.%或更少,更佳为1at.%至2at.%,例如大约1.5at.%。
含硅、硅锗、硅碳或硅锗碳的多层会以变化的顺序沉积,以在含硅外延层240中形成逐次变化的元素浓度。通常以大约1×1019原子数/立方厘米至2.5×1021原子数/立方厘米范围之间的掺杂物(诸如,硼、砷、磷、镓或铝)浓度掺杂含硅层,较佳的浓度为大约5×1019原子数/立方厘米至2×1020原子数/立方厘米。加入含硅材质各层的掺杂物形成逐次变化的掺杂物。例如,藉由以大约5×1019原子数/立方厘米至1×1020原子数/立方厘米范围之间的掺杂物浓度(例如硼)来沉积第一含硅锗层,以及以大约1×1020原子数/立方厘米至2×1020原子数/立方厘米范围之间的掺杂物浓度(例如硼)来沉积第二含硅锗层,进而形成含硅外延层240。
紧接在含硅层的沉积之后,并入含硅碳层与含硅锗碳层的碳通常位于结晶晶格的间隙部位。间隙碳的含量大约是10at.%或更少,较佳的含量为低于大约5at.%,且更佳的含量为大约1at.%至3at.%之间,例如大约2at.%。可用退火处理含硅外延层240来并入至少一部分(若不是全部的话)的间隙碳进入结晶晶格的取代位置(substitutional sites)上。退火处理可能包括一突发式退火,诸如快速热处理(RTP)、雷射退火或以一大气压力气体(例如氧、氮、氢、氩、氦或上述的混合物等)的热退火(thermal annealing)。退火处理执行大约800℃至1200℃范围之间的温度下,较佳的温度为大约1050℃至1100℃。退火处理可以立即发生于含硅层沉积之后或是在许多其它基板承受的处理步骤之后。
下一步骤中,第2D图显示间隙壁244,其通常是一沉积在间隙壁234上的氮化物(例如氮化硅「Si3N4」)间隙壁。通常以化学气相沉积(chemical vapordeposition,CVD)或原子层沉积(atomic layer depostion,ALD)技术于不同的腔内沉积间隙壁244。因此,基板从用来沉积含硅外延层240的处理腔中移除。在两腔室之间的传送中,基板可能暴露于周围环境,诸如温度、压力或含水与氧的大气。在沉积间隙壁244或执行其它半导体处理(诸如,退火、沉积或布植)之后,立即第二次暴露基板给周围环境,此发生在沉积增厚层(elevated layer)248之前。一实施例中,一不具有或具有最小量(例如,低于大约5at%)的锗的外延层(未显示),其在基板暴露给周围环境之前沉积在外延层240的顶部,由于相对于以高于大约5
at%锗浓度而形成的外延层,较容易从包含最小量的锗浓度的外延层移除天生氧化物。
图2E绘示另一实例,其中由含硅材质组成的增厚层248选择性与外延式的沉积在外延层(例如掺杂硅锗)240上。沉积处理中,多晶层242更近一步地成长、沉积或蚀刻于栅极236上。
一较佳的实施例中,增厚层248以包含极少(或没有)的锗或碳的硅外延沉积而成。然而,一替代的实施例中,增厚层248确实包含锗与/或碳。例如,增厚层248可能具有大约5at%或更少的锗。另一实例中,增厚层248可能具有大约2at%或更少的碳。增厚层248亦可以一掺杂物(诸如硼、砷、磷、铝或镓)掺杂。
合硅化合物应用于沉积含硅层处理的实施例中,其应用于双极型组件(Bipolar device)制造(例如基极「base」、射极「emitter」、集极「collector」、射极接点「emitter contact」)、双载子互补式金氧半导体(BiCMOS)组件制程(例如基极「base」、射极「emitter」、集极「collector」、射极接点「emitter contact」)与互补式金氧半导体(CMOS)组件制程(例如,沟道、源极/漏极、源极/漏极延展、增厚的源极/漏极、基板、应变硅「strained silicon」、绝缘层上覆硅「siliconon insulator」与接点插塞「contact plug」)。处理的其它实施例讲授了含硅层的成长,其可运用来当作栅极、基极接点(base contact)、集极接点(collectorcontact)、射极接点、增厚的源极/漏极与其它应用。
本处理特别有用于沉积选择性外延式含硅层在金氧半场效晶体管与双极型晶体管中(如绘示于图3A-3C中)。图3A-3B显示含硅化合物外延成长于金氧半场效晶体管组件上。含硅化合物沉积在组件的源极/漏极特征上。含硅化合物黏附且成长于下层的结晶晶格上,且当含硅化合物成长至所欲厚度时一直维持此种排列。图3A描述含硅化合物沉积成一凹陷的源极/漏极层,而图3B显示含硅化合物沉积成一凹陷的源极/漏极层与增厚的源极/漏极层。
藉由离子布植法形成源极/漏极区312。通常,基板310以P型掺杂时源极/漏极区312也以P型掺杂。含硅层313选择性成长于源极/漏极区312与/或直接在基板310上。含硅外延层314根据此文中的态样选择性地成长于含硅层313。栅极氧化层318连结片段的含硅层313。通常,栅极氧化层318由二氧化硅、氮氧化硅(silicon oxynitride)或二氧化铪(hafnium oxide)所组成。部分地包围栅极氧化层318的是间隙壁316,其通常是例如氮氧叠层(nitride/oxidestack)(例如,氮化硅/氧化硅/氮化硅)的绝缘材质。栅极层322(例如,多晶硅)可能具有沿着其垂直侧边的保护层319(例如二氧化硅),如图3A中所示。或者,栅极层322可能具有配置于其每一侧边的间隙壁316与偏置层(off-set layer)320(例如,氮化硅)。
另一实例中,图3C绘示沉积的含硅外延层334作为一双极式晶体管的基极层。含硅外延层334选择式地成长在本发明不同的实施例中。含硅外延层334沉积在N型集极层332(之前已沉积在基板330上)上。晶体管更近一步包括绝缘层333(例如,氧化硅或氮化硅)、接触层336(例如,大量掺杂多晶硅)、偏置层338(例如氮化硅)与第二绝缘层340(例如,氧化硅或氮化硅)。
本发明的处理可以施行于原子层外延(ALE)、化学气相沉积(CVD)与原子层沉积(ALD)等技术上已知的设备中。该设备可能包括许多气体管线,好在进入处理腔之前维持沉积气体与蚀刻气体的分离。此后,气体被带至与加热过的基板接触,于其上成长了含硅化合物薄膜。可用来沉积含硅薄膜的硬件包括,位于Santa Clara,California的Applied Materials,Inc.所提供的Epi Centura系统与Poly Gen系统。原子层沉积设备揭示于2005年7月12日提出且命名为“原子层沉积所用的气体输送设备与方法”(一般标示为美国专利申请案第6,916,398号)中,且为了描述该设备,其全文以参考资料并入本文中。其它设备包括技术已知的批次炉(batch)与高温管型炉(high-temperature furnaces)等等。
实例1:一300mm裸露的硅晶圆置于300mm Epi Centura系统中减少压力的腔室(可从Santa Clara,CA的Applied Materials,Inc.获得)中。一800厚且未掺杂Si:C的外延薄膜沉积在300mm裸露的硅晶圆上。利用“Quantum X implanter”(可从Santa Clara,CA的Applied Materials,Inc.获得)以2keV与1.5 x 1015cm-2份量布植磷。利用“Centura RTP”(可从Santa Clara,CA的Applied Materials,Inc.获得)在1050℃温度下执行突发式退火于硅晶圆上。处理过的外延薄膜以高分辨率X光绕射仪(HR-XRD)辨识其特征好确定可置换碳的浓度与厚度。以二次离子质谱仪(Secondary Ion Mass Spectroscopy,SIMS)确定全体碳(可置换碳加上间隙碳)的浓度与磷浓度的纵深分布。可以使用穿透式电子显微镜来作外延薄膜的微结构研究。
图4描述沉积后(对照组)402与突发式退火处理后404的硅碳外延薄膜的高分辨率X光绕射仪(HR-XRD)频谱的标示图400。X轴代表Omega[角秒(arcsec)]而Y轴代表强度[天文单位(A.U.)]。Si:C的比值集中在大约1240角秒(位于基板硅所代表的尖峰的正面),表示可置换碳的浓度为1.24%。同样地,许多厚度边缘(thickness fringes)显示外延膜高度结晶化。一插入硅晶格常数(5.43105A)与碳化硅立方体(cubic silicon carbide)的晶格常数(4.35965A)之间,且类似Vegard的直线,其被用来从X光绕射仪的结果确定可置换碳的存在。
突发式退火对Si:C薄膜的可置换碳的影响亦显示于图4。从两个X光绕射仪频谱的比较来说,可以在藉由1050℃温度下的突发式退火发现可置换碳减少0.06%(相当于尖峰向较低的omega移动60角秒)。然而,并没有发现变宽的尖峰。而厚度边缘套试(thickness fringe fitting)结果也获得相同厚度(误差范围内)。这显示了在退火过后,薄膜仍可维持其品质(仅损失些微的可取代碳)。
图5描述沉积后(对照组)502、布植后504与布植后/退火处理后506的硅碳外延薄膜的高分辨率X光绕射仪频谱的标示图500。X轴代表Omega[角秒(arcsec)]而Y轴代表强度[天文单位(A.U.)]。对布植后/退火处理后的样本506来说,可以发现显著的改变。尖峰从1240”移至1100”,且具有不对称变宽的尖峰。再者,厚度条纹尖峰更增强于Si:C尖峰的左面以及邻近基板尖峰的肩峰(shoulder peak)上。由于布植法典型地引发层的上部的损害,为了配合X光绕射仪的结果,发展出具有不同碳浓度的两层模式。根据两层模式,顶部300具有非常低的可置换碳浓度(大约0.35%),然而第二层具有560的厚度,其具有将近1.24%的可置换碳。
图6描述布植后/退火处理后的硅碳薄膜的碳604与磷606的二次离子质谱仪(Secondary Ion Mass Spectroscopy,SIMS)纵深分布的标示图600。覆盖对照样本602的碳纵深分布作为比较。发现全体碳大约是1.3%。这显示了超过90%的置换力。在1 X 1018cm-3磷浓度下的接合区纵深大约是370,其接近于上述X光绕射仪两层模式的顶层厚度。再者,沿着纵深的碳浓度似乎在布植引起的射程末端(end-of-range)缺失内出现些微的震荡。值得注意的是磷接合区分布,其陡峭度达至3nm/decade,显示Si:C外延膜中磷扩散的显著延迟。
总结,虽然1050℃温度下的突发式退火导致可置换碳的些微损失(0.6%)不过仍保持高度结晶,但是磷布植法引发可置换碳的显著损失与碳纵深分布的改变。亦发现一非常陡峭的接合区形成于Si:C外延薄膜内。
虽然上述之文指向本发明的实施例,但可以在不悖离其基本范围内设计出本发明其它与更进一步的实施例,且其范围取决于之后的权利要求书。
Claims (24)
1.一种于一基板上形成一超浅接合区的方法,该方法至少包含:
沉积一硅碳层在该基板上;
将该基板暴露在一掺杂物下;又接着;
加热该基板至一超过950℃的温度以便引发该掺杂物与该硅碳层的实质退火处理。
2.如权利要求1所述的方法,其中该温度位于1000℃与1100℃之间。
3.如权利要求1所述的方法,其中该温度位于1030℃与1050℃之间。
4.如权利要求1所述的方法,其中该温度大约是1050℃。
5.如权利要求1所述的方法,其中该沉积一硅碳层在基板上的步骤包括外延式沉积该硅碳层。
6.如权利要求1所述的方法,其中该掺杂物选自硼、砷、磷与上述物质的组合物所组成的群组中。
7.如权利要求1所述的方法,其中该将硅碳层暴露在一掺杂物下的步骤包括执行一离子布植处理。
8.如权利要求7所述的方法,其中该离子布植处理包括在大约1keV与2keV之间,布植剂量大约5 X 1014原子数/平方厘米至1 X 1015原子数/平方厘米之间的磷。
9.如权利要求7所述的方法,其中该离子布植处理包括在大约0.5 keV下,布植剂量大约5 X 1014原子数/平方厘米至1 X 1015原子数/平方厘米之间的硼。
10.如权利要求1所述的方法,其中该将该硅碳层暴露在一掺杂物之下的步骤与该沉积一硅碳层于基板的步骤同时发生。
11.如权利要求1所述的方法,其中该加热一基板的步骤包括执行一突发式退火。
12.如权利要求1所述的方法,其中该超浅接合区具有一大约3nm/decade的掺杂物分布。
13.一种于一基板上形成一超浅接合区的方法,其至少包含:
沉积一硅碳外延层在该基板上;
布植一掺杂物进入该硅碳层;以及
加热该基板至一超过950℃的温度。
14.如权利要求13所述的方法,其中该温度位于1000℃与1100℃之间。
15.如权利要求13所述的方法,其中该温度大约是1050℃。
16.如权利要求13所述的方法,其中该掺杂物选自硼、砷、磷与上述的组合物组成的群组中。
17.如权利要求13所述的方法,其中该布植处理包括在大约1 keV与2 keV之间下,布植剂量大约5 X 1014原子数/平方厘米至1 X 1015原子数/平方厘米之间的磷。
18.如权利要求13所述的方法,其中该布植一掺杂物进入该硅碳层包括布植剂量大约5 X 1014原子数/平方厘米至1 X 1015原子数/平方厘米之间的硼。
19.如权利要求13所述的方法,其中该超浅接合区具有一大约3 nm/decade的掺杂物分布。
20.如权利要求13所述的方法,其中该加热该基板至一超过950℃的温度之后,该硅碳层的一上部的可置换碳浓度低于该硅碳层的一下部的可置换碳浓度。
21.如权利要求13所述的方法,其中该布植一掺杂物进入硅碳层的步骤包括执行一浸没式等离子体离子布植处理。
22.如权利要求13所述的方法,其中该沉积一硅碳外延层于基板上的步骤包括执行一选择式外延处理。
23.一种具有一陡峭p-n接合区的结构,该结构至少包含:
一半导体基板;
一源极区与一漏极区(藉由在一外延式沉积的硅碳层内进行离子布植而界定);以及
一沟道区(其具有一栅极结构在该沟道区之上),该栅极结构包括一栅电极与一介电层。
24.如权利要求23所述的结构,其中该陡峭p-n接合区具有一大约3nm/decade的掺杂接合区分布。
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TWI385732B (zh) | 2013-02-11 |
EP2024531A2 (en) | 2009-02-18 |
TW200802614A (en) | 2008-01-01 |
KR101170210B1 (ko) | 2012-08-01 |
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