CN101409267A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN101409267A
CN101409267A CNA2008101701520A CN200810170152A CN101409267A CN 101409267 A CN101409267 A CN 101409267A CN A2008101701520 A CNA2008101701520 A CN A2008101701520A CN 200810170152 A CN200810170152 A CN 200810170152A CN 101409267 A CN101409267 A CN 101409267A
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semiconductor device
diaphragm
substrate
film
pad
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石堂仁则
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NEC Corp
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Abstract

提供一种半导体器件，具有衬底、倒装芯片安装在衬底上的半导体芯片、和提供在衬底与半导体芯片之间间隙中的叠层膜。该叠层膜由覆盖衬底表面的保护膜和形成在焊料抗蚀剂膜与半导体芯片之间的底层填料膜组成。在接触所述底层填料膜的接触表面上使保护膜粗糙化。

Description

半导体器件及其制造方法
该申请基于日本专利申请No.2007-266808，其内容通过引用结合于此。
技术领域
本发明涉及一种具有填充在半导体芯片和衬底之间间隙中的底层填料的半导体器件及其制造方法。
背景技术
已知日本早期公开专利公布No.2006-93493中描述的常规印刷线路板。该公布描述了具有使用抛光(buff)或湿法喷砂在衬底表面上提供有粗糙化的保护层和层叠在保护层上的绝缘基底(预浸料)的绝缘衬底的印刷线路板。由环氧丙烯酸树脂组成的膜用于保护层。
该公开描述了这种结构能改善保护层和绝缘基底之间的粘附性。
日本早期公开专利公布No.H6-97634描述了一种印刷线路板，该印刷线路板具有提供有安装垫和由干膜组成且具有允许在那里暴露安装垫顶表面的开口的焊料抗蚀剂的衬底。
参考示出制造半导体器件方法的图4A、4B和5，下面的段落将说明本发明要解决的主题。
首先，如图4A所示，通过在具有预先形成在衬底上的第一安装垫114的衬底112上涂敷负型液体焊料抗蚀剂，并通过照相显影使该涂敷膜图案化以形成开口115，来形成焊料抗蚀剂膜116。
接下来，利用高锰酸盐和等离子体处理对焊料抗蚀剂膜116进行沾污去除，以实现0.05μm或更大的表面粗糙度Ra(算术平均粗糙度)，由此得到如图4B所示的粗糙化的焊料抗蚀剂膜118。
然后，如图5A所示，在衬底112上的第一安装垫114上形成预先沾锡120，以由此得到印刷线路板。
接下来，如图5B所示，半导体芯片126侧上的安装垫128和衬底112侧上的第一安装垫114被连接，而在其间放置焊料凸块122，由此使半导体芯片126和印刷线路板相互电连接。然后在半导体芯片126和焊料抗蚀剂膜118之间填充底层填料材料以形成底层填料膜124，由此得到半导体器件。
然而，由此得到的半导体器件仍具有改善焊料抗蚀剂膜118润湿性的均匀性的一些空间。为此，在倒装芯片安装后焊料抗蚀剂膜118表面的可清洁性有时不够，而在焊料抗蚀剂膜118的表面上留下诸如焊剂的残留物。在底层填料膜124和焊料抗蚀剂膜118之间的界面上有时产生气泡。这些残留物和气泡有时引起在底层填料膜124中产生空隙，且有时导致凸块间短路。
另外，在填充过程中底层填料材料有时会从半导体芯片126和焊料抗蚀剂膜118之间的间隙流出，该填充过程会抑制底层填充带的均匀形成，会导致渗流，并会降低半导体器件的产量。
考虑上述情形之后理解本发明，其中其主题在于提供抑制凸块间短路的半导体器件，及以良好的产品产量制造该半导体器件的方法。
发明内容
根据本发明，提供了一种半导体器件，其包括衬底；倒装芯片安装在衬底上的半导体芯片；以及提供在衬底与半导体芯片之间的间隙中的叠层膜，该叠层膜由覆盖衬底表面的保护膜和在保护膜与半导体芯片之间形成的底层填料膜组成，其中在接触底层填料膜的保护膜的接触表面上使保护膜被粗糙化。
由于在本发明中保护膜的表面称为粗糙化的表面，所以改善了保护膜表面的润湿性，因此防止在底层填料层中产生空隙。结果，可抑制凸块间短路，并可提高产品的产量。
因为在填充底层填料材料的过程中成功地防止底层填料材料从半导体芯片和保护膜之间的间隙渗流出，所以还可提高半导体器件的产量。
从上面清楚的是，在制造过程中本发明的半导体器件具有能确保极好效果的结构。
根据本发明，还提供了制造半导体器件的方法，其包括在具有第一安装垫形成在其上的衬底上方形成保护膜；在保护膜中形成开口，以允许第一安装垫暴露在开口的底部；使保护膜的表面粗糙化；当在其间放置凸块时以倒装芯片方式在衬底上的第一安装垫上安装半导体芯片；清洁保护膜的表面；以及通过填充和固化底层填料材料，在保护膜和半导体芯片之间的间隙中形成底层填料膜。
在使保护膜表面粗糙化之后，该方法具有清洁保护膜表面的步骤。
依靠这种结构，可改善保护膜表面的润湿性，且还可确保在倒装芯片安装之后保护膜表面具有好的可清洁性。因此，能抑制由于焊剂等残留物和气泡所产生的空隙。因此能抑制凸块间短路，并能提高产品的产量。
此外，由于保护膜的表面被粗糙化和清洁之后填充底层填料材料，所以可以成功防止底层填料材料从半导体芯片和保护膜之间的间隙渗流出，由此可以提高产品的产量。
应该明白，本发明上下文中的“带状几何图形”意味着底层填料膜的端部剖面，其属于从半导体芯片的边缘到焊料抗蚀剂表面布置的底层填料膜部分。
根据本发明，可提供抑制凸块间短路和底层填料材料渗流出，且具有均匀带状几何图形的半导体器件，以及能以高产量制造这种半导体器件的方法。
附图说明
结合附图，根据某些优选实施例的以下描述，将使本发明的上述和其他目的、优点和特征将变得更加明显，其中：
图1A至2B是示意性示出制造一个实施例的半导体器件的方法步骤的截面图；
图3是说明该实施例的半导体器件的端部剖面的截面图；
图4A至5B是逐步示出的截面图，说明了本发明的主题；
图6是逐步示出的截面图，说明了本发明的另一主题；以及
图7是说明该实施例的半导体器件的修进实例的截面图。
具体实施方式
现在参考示例性实施例在这里描述本发明。本领域技术人员将认识到，可以使用本发明的教导实现许多可替选的实施例，并且本发明不限制于用于解释目的而示例的实施例。
在用于说明本发明实施例的所有图中，任何相似的要素将用相同的附图标记示出，以适当避免重复说明。
图2B是示出该实施例的部分半导体器件的截面图，图3是示出半导体器件边缘部分的局部截面图。
如图2B所示，该实施例的半导体器件具有衬底12、倒装芯片安装在衬底12上的半导体芯片26和在衬底12和半导体芯片26之间的间隙中填充的叠层膜。
该叠层膜由覆盖衬底12表面的保护膜(焊料抗蚀剂膜18)和在焊料抗蚀剂膜18与半导体芯片26之间形成的底层填料膜24组成。
衬底12是印刷线路板，且具有形成在其表面上的多个第一安装垫14。在第一安装垫14上，安装半导体芯片26，同时将焊料凸块22放置于其间。衬底12具有大约0.4μm的厚度。
如图3所示，在安装半导体芯片26的衬底区域中在衬底12上形成第一安装垫14。在围绕半导体芯片26的区域中，形成第二安装垫29。在形成于焊料抗蚀剂膜18中的开口30的底部暴露第二安装垫29的上表面。
在半导体芯片26的边缘到在开口30底部暴露的第二安装垫29表面的周边之间的距离b可调整到大约0.5mm到2.5mm。
焊料抗蚀剂膜18可由环氧树脂等组成。将焊料抗蚀剂膜18的厚度“a”调整到5μm或更大且30μm或更小，且优选为5μm或更大且15μm或更小。
在接触底层填料膜24的焊料抗蚀剂18的接触表面18a上使焊料抗蚀剂膜18粗糙化。接触表面18a的表面粗糙度Ra(算术平均粗糙度)优选为0.2μm或更大且0.5μm或更小。表面粗糙度Ra可使用原子力显微镜测量。底层填料膜24可由环氧树脂等组成。
焊料凸块22可由无铅焊料组成。在焊料抗蚀剂上方的焊料凸块22的高度大约为50μm到100μm。在互连延伸区中的凸块的节距大约为150μm到240μm。
接下来，将说明制造该实施例的半导体器件的方法。
制造该实施例的半导体器件的方法具有下面的步骤(a)到(f)。
步骤(a)：在具有第一安装垫形成在其上的衬底上形成保护膜。
步骤(b)：在保护膜中形成开口，在开口中允许第一安装垫暴露在它的底部。
步骤(c)：使保护膜的表面粗糙化。
步骤(d)：在衬底上的第一安装垫上以倒装芯片的方式安装半导体芯片，同时将凸块放置在其间。
步骤(e)：清洁保护膜的表面。
步骤(f)：通过在保护膜和半导体芯片之间的间隙中填充并固化底层填料材料来形成底层填料膜。
将顺序说明上述步骤。
步骤(a)：在具有第一安装垫14形成于其上的衬底12上形成保护膜。
首先，将负干膜型焊料抗蚀剂层压到具有第一安装垫14预先形成在其上的衬底12。
选择干膜型焊料抗蚀剂的厚度，使得在衬底12侧上的安装垫14上使这种固化的厚度“a”可以为5μm或更大30μm或更小。
焊料抗蚀剂膜的厚度优选为5μm或更大到15μm或更小。由于焊料抗蚀剂膜的厚度像上述的一样薄，所以可优化焊料凸块的几何图形且抵御外力的保持强度可以取决于最大的底层填料膜。即，改善了连接可靠性。在此可采用的用于干膜型焊料抗蚀剂的典型材料可以是Taiyo Ink MFG有限公司的PFR-800AUS410。
步骤(b)：在保护膜中形成开口15，在开口中允许第一安装垫14暴露在它的底部。
更具体地，如图1A所示，通过照相显影技术使焊料抗蚀剂膜图案化，由此形成具有开口15的保护膜(焊料抗蚀剂膜16)，在这里允许安装垫14的表面暴露在开口15的底部。
步骤(c)：使保护膜(焊料抗蚀剂膜16)的表面粗糙化。
如图1B所示，使焊料抗蚀剂膜16的表面粗糙化，由此得到粗糙化的焊料抗蚀剂膜18。可给定粗糙法以便获得表面粗糙度Ra(算术平均粗糙度)为0.2μm或更大且0.5μm或更小的焊料抗蚀剂膜18。
过度粗糙化可使焊料抗蚀剂膜18变脆且可使特性退化，使得表面粗糙度Ra(算术平均粗糙度)可优选地调整为0.5μm或更小。
可通过湿法喷砂执行粗糙化。
用于湿法喷砂的条件可包括使用具有1mm宽的狭缝的宽喷枪，使用A#800氧化铝研磨剂，喷枪和焊料抗蚀剂膜16的距离大约为10到30mm，大气供给压力大约为0.18到0.30MPa，和处理速度大约为1.0到1.8m/min。
步骤(d)：在衬底12上的第一安装垫14上以倒装芯片的方式安装半导体芯片26，同时将凸块22放置在其间。
首先，如图2A所示，在衬底12侧上的第一安装垫14上形成预先沾锡20。因此得到提供有具有预定表面粗糙度的焊料抗蚀剂膜18的印刷线路板。
接下来，半导体芯片26的安装垫28和衬底12侧上的第一安装垫14被连接，同时将凸块22放置在其间，由此电连接半导体芯片26和印刷线路板。
步骤(e)：清洁保护膜(焊料抗蚀剂膜18)的表面。
根据常用的方法，使用清洁液，例如常用的乙醇基溶剂或水基清洁剂进行清洁。通过获得如上所述的粗糙度的粗糙化，来改善焊料抗蚀剂膜18的可清洁性。
步骤(f)：通过在保护膜(焊料抗蚀剂膜18)和半导体芯片26之间的间隙中填充并固化底层材料形成底层填料膜。
如图2B所示，在半导体芯片和焊料抗蚀剂膜18之间的间隙中底层填料材料被填充、固化以形成底层填料膜24并由此可得到该半导体器件。在此可采用的底层填料材料可以是那些环氧树脂基。
步骤(f)之后，可通过一般工序制造半导体器件。
下面将说明该实施例的效果。
在该实施例中，焊料抗蚀剂膜18的接触面18a被给定为粗糙化的表面。接触面18a的表面粗糙度Ra(算术平均粗糙度)可优选地调整到0.2μm或更大且0.5μm或更小。
为此，改善焊料抗蚀剂膜18表面的润湿性，并在倒装芯片结合之后允许彻底去除残留物，如遗留在焊料抗蚀剂膜18表面上的焊剂。在填充底层材料的过程中，改善焊料抗蚀剂膜18表面的润湿性，还有利于抑制在焊料抗蚀剂膜18的表面产生气泡。
依靠这种结构，可成功地防止由于残留物和气泡而引起的空隙在底层填料膜24中产生，由此可抑制凸块间短路，并可改善产品的产量。
另外，在填充底层填料材料的过程中可以成功地防止底层填料材料从半导体芯片26和焊料抗蚀剂膜18之间的间隙中渗流出，使得可改善半导体器件的产量。
而且，如图3所示配置该实施例的半导体器件，其中在围绕半导体芯片26的至少部分区域中提供第二安装垫29。即使在形成底层填料膜之后，第二安装垫29的表面也保持暴露。
随着近来的生长需要降低尺寸、更高的处理速度和更低的功率消耗的电子器具，具有在单个封装中集成多个LSI系统的SiP(封装内系统)取得了显著的进展。与此相关，在倒装芯片安装的半导体芯片附近对具有安装垫表面的半导体器件提出了新的要求。在半导体芯片26的附近提供的第二安装垫29允许在其上安装另一半导体芯片或半导体封装，以便形成SiP。
如果将其表面上粗糙化的与算术平均粗糙度Ra为0.05μm左右一样精细的焊料抗蚀剂膜118应用于如图4A、4B和5所示由此配置的半导体器件，则底层填料材料可超出预定范围溢出以延伸在提供在半导体芯片126周围的安装垫129的上方。底层填料膜124的端部剖面(带状几何图形132)在横向方向上变宽足够覆盖安装垫114，使得安装垫114不再可用。
在找出这样的新主题之后，本发明人最后得到本发明。
更具体地，如图3所示，在该实施例中焊料抗蚀剂膜18的表面被给定为粗糙表面，其中其表面粗糙度Ra(算术平均粗糙度)优选地调整为0.2μm或更大且0.5μm或更小。
依靠这种结构，现在底层填料膜24具有以预定几何图形安置的底层填料膜的端部剖面(带状几何图形32)，防止延伸在半导体芯片26周围提供的第二安装垫29的上方，并可以保持它们是可利用的。更具体地，可通过倒装芯片安装到这些第二安装垫29上来连接另一半导体芯片或另一半导体封装。
该实施例的保护膜由于膜型焊料抗蚀剂组成。
通过使用干膜型焊料抗蚀剂，可平面化半导体芯片26下面的焊料抗蚀剂膜18，由此半导体芯片26和焊料抗蚀剂膜18之间的间隙高度可制作为一致的。
由于在倒装芯片安装之后得到的半导体芯片26和焊料抗蚀剂膜18之间的间隙高度的一致性，所以清洁溶液能够均匀地延伸到那里。通过落在上述范围内的焊料抗蚀剂膜18的表面粗糙的增强效应，在倒装芯片安装之后的清洁过程中可进一步改善可清洁性。
优势还在于可以防止底层填料材料渗流出。
仅作为示范性情形，上文已参考附图描述了本发明的实施例，同时允许采用不同于上面描述的各种结构。
例如，提供在半导体芯片26周围的第二安装垫29可围绕半导体芯片26两圈或更多圈。
可替选地，可在衬底12上平行安装两个或更多半导体芯片26，且还可替选地，可在衬底12上从半导体芯片26上方安装半导体封装。
图7示出具有在衬底12上从半导体芯片26上方安装的半导体封装40的半导体器件的实例。半导体封装40具有多个焊球42，且安装在第二安装垫29上，同时将焊球42放置在其间。在衬底12的背面上，提供多个焊球34。图7示出的半导体器件具有POP(堆叠封装)结构。
将本发明的半导体器件用于POP结构可成功地防止底层填料材料渗流出，且可有助于形成一致的带状几何图形，使得根本不用底层填料材料覆盖第二安装垫29。因此半导体封装40可确保与第二安装垫29连接的期望性能，并由此可改善半导体器件的产量。
[实例]
[实例1]
根据下面描述的条件制造图2B和图3中示出的半导体器件。
(a)材料
焊料抗蚀剂膜18：环氧树脂膜，来自Taiyo Ink MFG有限公司的PFR-800 AUS410。
底层填料膜24：环氧基树脂；以及
凸块22：无铅焊料。
(b)粗糙化(湿法喷砂)焊料抗蚀剂膜18的表面
使用提供具有1mm宽的狭缝(产品名称：Macoho有限公司的物理精细蚀刻机)的宽喷枪的湿法喷砂设备，并使用A#800氧化铝研磨剂，来执行湿法喷砂，同时设置喷枪和焊料抗蚀剂膜16之间的距离大约为10mm到30mm，大气供给压力大约为0.18MPa到0.25MPa，处理速度大约为1.0m/min到1.8m/min。
(c)测量表面粗糙度的方法
使用原子力显微镜测量表面粗糙度Ra(算术平均粗糙度)。
发现焊料抗蚀剂膜18的表面粗糙度Ra为0.2μm。
[实例2]
除了在将大气供给压力调整为约0.25Mpa到0.30Mpa的同时对焊料抗蚀剂膜18的表面进行湿法喷砂以外，制造半导体器件与实例1中描述的类似。
发现焊料抗蚀剂膜18的表面粗糙度Ra为0.5μm。
证实了实例1、2中得到的半导体器件抑制了底层填料膜24中的空隙和凸块间短路的产生。还证实了以如图3所示的预定几何图形设置了底层填料膜24的带状几何图形32，使在半导体芯片26周围提供的第二安装垫暴露。
[比较实例1]
除了在大气供给压力大约为0.05MPa到0.13MPa的情况下，使用A#2000氧化铝研磨剂对焊料抗蚀剂膜进行湿法喷砂以外，制造半导体器件与如实例1中描述的类似。
发现焊料抗蚀剂膜的表面粗糙度Ra(算术平均粗糙度)为0.1μm。
在比较实例1的半导体器件中，确定了在底层填料膜中的空隙，并确定了凸块间短路。还发现，如图6所示，在半导体芯片周围提供的安装垫129被底层填料膜覆盖。
[比较实例2]
除了使用A#600氧化铝研磨剂对焊料抗蚀剂膜进行湿法喷砂以外，制造半导体器件与如实例1中描述的类似。
发现焊料抗蚀剂膜的表面粗糙度Ra(算术平均粗糙度)为0.6μm。
证实了，在比较实例2的半导体器件中，焊料抗蚀剂膜变脆了，并因此使诸如焊料的耐热性和耐化学药品的特性退化了。
显然，本发明不限制于上述实施例，在不偏离本发明范围和精神的情况下可以作修变和改变。

Claims (13)

1.一种半导体器件，包括：
衬底；
半导体芯片，倒装芯片安装在所述衬底上；
叠层膜，提供在所述衬底和所述半导体芯片之间的间隙中，所述叠层膜由覆盖所述衬底的表面的保护膜与形成在所述保护膜和所述半导体芯片之间的底层填料膜组成，
其中在接触所述底层填料膜的保护膜的接触表面上，使所述保护膜粗糙化。
2.如权利要求1所述的半导体器件，
其中在接触所述底层填料膜的保护膜的接触表面上，所述保护膜具有0.2μm或更大且0.5μm或更小的算术平均粗糙度。
3.如权利要求1所述的半导体器件，还包括：
第一安装垫，形成在所述衬底上，并且被连接至所述半导体芯片同时在其间放置有凸块；以及
第二安装垫，与所述第一安装垫不同，形成在衬底的围绕所述半导体芯片的至少局部区域中的所述衬底上。
4.如权利要求3所述的半导体器件，
其中所述第二安装垫具有暴露的表面。
5.如权利要求3所述的半导体器件，还包括：
半导体封装，安装在所述第二安装垫上同时在其间放置有焊球，所述半导体封装布置在所述半导体芯片上方。
6.如权利要求3所述的半导体器件，
其中从所述第一安装垫的表面测量的所述保护膜的表面的高度为5μm或更大且30μm或更小。
7.如权利要求1所述的半导体器件，
其中所述保护膜由干膜型焊料抗蚀剂组成。
8.一种制造半导体器件的方法，包括：
在具有在其上形成的第一安装垫的衬底上方形成保护膜；
在所述保护膜中形成开口以便允许所述第一安装垫暴露在开口的底部；
使所述保护膜的表面粗糙化；
当在其间放置凸块时在所述衬底上的所述第一安装垫上以倒装芯片方式安装半导体芯片；
清洁所述保护膜的表面；以及
通过填充和固化底层填料材料，在所述保护膜和所述半导体芯片之间的间隙中形成底层填料膜。
9.如权利要求8所述的制造半导体器件的方法，
其中所述使所述保护膜的表面粗糙化包括使所述保护膜的表面粗糙化以便将其算术平均粗糙度调整到为0.2μm或更大且0.5μm或更小。
10.如权利要求8所述的制造半导体器件的方法，
其中，形成所述底层填料膜以便允许不同于所述第一安装垫的第二安装垫的表面暴露在围绕所述半导体芯片的至少部分区域中。
11.如权利要求8所述的制造半导体器件的方法，
其中从所述第一安装垫的表面测量的所述保护膜的表面的高度为5μm或更大且30μm或更小。
12.如权利要求8所述的制造半导体器件的方法，
其中所述形成所述保护膜包括在所述衬底上方放置干膜型焊料抗蚀剂。
13.如权利要求8所述的制造半导体器件的方法，
其中所述使所述保护膜的表面粗糙化包括利用湿法喷砂使所述保护膜的表面粗糙化。
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