CN101390209B - 通过在栅极和沟道中引起应变来增强cmos晶体管性能的方法 - Google Patents
通过在栅极和沟道中引起应变来增强cmos晶体管性能的方法 Download PDFInfo
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- CN101390209B CN101390209B CN2005800385018A CN200580038501A CN101390209B CN 101390209 B CN101390209 B CN 101390209B CN 2005800385018 A CN2005800385018 A CN 2005800385018A CN 200580038501 A CN200580038501 A CN 200580038501A CN 101390209 B CN101390209 B CN 101390209B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/794—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising conductive materials, e.g. silicided source, drain or gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/796—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0172—Manufacturing their gate conductors
- H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0172—Manufacturing their gate conductors
- H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0184—Manufacturing their gate sidewall spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/904,461 US20060099765A1 (en) | 2004-11-11 | 2004-11-11 | Method to enhance cmos transistor performance by inducing strain in the gate and channel |
| US10/904,461 | 2004-11-11 | ||
| PCT/US2005/041051 WO2006053258A2 (en) | 2004-11-11 | 2005-11-10 | Method to enhance cmos transistor performance by inducing strain in the gate and channel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101390209A CN101390209A (zh) | 2009-03-18 |
| CN101390209B true CN101390209B (zh) | 2010-09-29 |
Family
ID=36316861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2005800385018A Expired - Fee Related CN101390209B (zh) | 2004-11-11 | 2005-11-10 | 通过在栅极和沟道中引起应变来增强cmos晶体管性能的方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US20060099765A1 (enExample) |
| EP (1) | EP1815506A4 (enExample) |
| JP (1) | JP4979587B2 (enExample) |
| KR (1) | KR101063360B1 (enExample) |
| CN (1) | CN101390209B (enExample) |
| TW (1) | TW200629426A (enExample) |
| WO (1) | WO2006053258A2 (enExample) |
Families Citing this family (36)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7396724B2 (en) * | 2005-03-31 | 2008-07-08 | International Business Machines Corporation | Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals |
| US20060228843A1 (en) * | 2005-04-12 | 2006-10-12 | Alex Liu | Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel |
| US7232730B2 (en) * | 2005-04-29 | 2007-06-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a locally strained transistor |
| US7790561B2 (en) * | 2005-07-01 | 2010-09-07 | Texas Instruments Incorporated | Gate sidewall spacer and method of manufacture therefor |
| US7488670B2 (en) | 2005-07-13 | 2009-02-10 | Infineon Technologies Ag | Direct channel stress |
| US20070108529A1 (en) | 2005-11-14 | 2007-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained gate electrodes in semiconductor devices |
| US7678630B2 (en) * | 2006-02-15 | 2010-03-16 | Infineon Technologies Ag | Strained semiconductor device and method of making same |
| US20070281405A1 (en) * | 2006-06-02 | 2007-12-06 | International Business Machines Corporation | Methods of stressing transistor channel with replaced gate and related structures |
| DE102006035646B3 (de) * | 2006-07-31 | 2008-03-27 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung verformter Transistoren durch Verspannungskonservierung auf der Grundlage einer verspannten Implantationsmaske |
| DE102006051494B4 (de) * | 2006-10-31 | 2009-02-05 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Ausbilden einer Halbleiterstruktur, die einen Feldeffekt-Transistor mit verspanntem Kanalgebiet umfasst |
| US7471548B2 (en) * | 2006-12-15 | 2008-12-30 | International Business Machines Corporation | Structure of static random access memory with stress engineering for stability |
| US20080237733A1 (en) * | 2007-03-27 | 2008-10-02 | International Business Machines Corporation | Structure and method to enhance channel stress by using optimized sti stress and nitride capping layer stress |
| JP5222583B2 (ja) * | 2007-04-06 | 2013-06-26 | パナソニック株式会社 | 半導体装置 |
| KR100839359B1 (ko) * | 2007-05-10 | 2008-06-19 | 삼성전자주식회사 | 피모스 트랜지스터 제조 방법 및 상보형 모스 트랜지스터제조 방법 |
| JP5076771B2 (ja) * | 2007-09-21 | 2012-11-21 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| US7718496B2 (en) * | 2007-10-30 | 2010-05-18 | International Business Machines Corporation | Techniques for enabling multiple Vt devices using high-K metal gate stacks |
| JP5194743B2 (ja) * | 2007-11-27 | 2013-05-08 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| US20090142891A1 (en) * | 2007-11-30 | 2009-06-04 | International Business Machines Corporation | Maskless stress memorization technique for cmos devices |
| DE102007057687B4 (de) * | 2007-11-30 | 2010-07-08 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Erzeugen einer Zugverformung in Transistoren |
| US20090179308A1 (en) * | 2008-01-14 | 2009-07-16 | Chris Stapelmann | Method of Manufacturing a Semiconductor Device |
| DE102008007003B4 (de) * | 2008-01-31 | 2015-03-19 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zum selektiven Erzeugen von Verformung in einem Transistor durch eine Verspannungsgedächtnistechnik ohne Hinzufügung weiterer Lithographieschritte |
| JP5117883B2 (ja) * | 2008-02-25 | 2013-01-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US7767534B2 (en) * | 2008-09-29 | 2010-08-03 | Advanced Micro Devices, Inc. | Methods for fabricating MOS devices having highly stressed channels |
| US8193049B2 (en) * | 2008-12-17 | 2012-06-05 | Intel Corporation | Methods of channel stress engineering and structures formed thereby |
| CN102386134B (zh) * | 2010-09-03 | 2013-12-11 | 中芯国际集成电路制造(上海)有限公司 | 制作半导体器件结构的方法 |
| CN102403226B (zh) * | 2010-09-15 | 2014-06-04 | 中国科学院微电子研究所 | 晶体管及其制造方法 |
| US8952429B2 (en) * | 2010-09-15 | 2015-02-10 | Institute of Microelectronics, Chinese Academy of Sciences | Transistor and method for forming the same |
| CN102637642B (zh) * | 2011-02-12 | 2013-11-06 | 中芯国际集成电路制造(上海)有限公司 | Cmos器件的制作方法 |
| CN102790085B (zh) | 2011-05-20 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | 半导体装置及其制造方法 |
| CN102290352B (zh) * | 2011-09-09 | 2013-02-06 | 电子科技大学 | 一种mos晶体管局部应力的引入技术 |
| CN105304567A (zh) * | 2014-07-31 | 2016-02-03 | 上海华力微电子有限公司 | 用于形成嵌入式锗硅的方法 |
| CN106158630B (zh) * | 2015-03-24 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的形成方法 |
| US10263107B2 (en) * | 2017-05-01 | 2019-04-16 | The Regents Of The University Of California | Strain gated transistors and method |
| CN111508961A (zh) * | 2020-04-27 | 2020-08-07 | 复旦大学 | 一种高隧穿效率半浮栅存储器及其制备方法 |
| US11735590B2 (en) | 2020-11-13 | 2023-08-22 | International Business Machines Corporation | Fin stack including tensile-strained and compressively strained fin portions |
| CN115547936B (zh) * | 2022-12-02 | 2023-06-16 | 合肥晶合集成电路股份有限公司 | 半导体结构的制作方法 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6512273B1 (en) * | 2000-01-28 | 2003-01-28 | Advanced Micro Devices, Inc. | Method and structure for improving hot carrier immunity for devices with very shallow junctions |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6213061A (ja) * | 1985-07-11 | 1987-01-21 | Fujitsu Ltd | 半導体集積回路装置 |
| US6281532B1 (en) * | 1999-06-28 | 2001-08-28 | Intel Corporation | Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering |
| JP2002093921A (ja) * | 2000-09-11 | 2002-03-29 | Hitachi Ltd | 半導体装置の製造方法 |
| JP2002198368A (ja) * | 2000-12-26 | 2002-07-12 | Nec Corp | 半導体装置の製造方法 |
| US6563152B2 (en) * | 2000-12-29 | 2003-05-13 | Intel Corporation | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel |
| JP4831885B2 (ja) * | 2001-04-27 | 2011-12-07 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
| JP3737045B2 (ja) * | 2001-11-13 | 2006-01-18 | 株式会社リコー | 半導体装置 |
| US6586294B1 (en) * | 2002-01-02 | 2003-07-01 | Intel Corporation | Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks |
| JP4173672B2 (ja) * | 2002-03-19 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
| JP2004096041A (ja) * | 2002-09-04 | 2004-03-25 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| US6828211B2 (en) * | 2002-10-01 | 2004-12-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control |
| JP2004172389A (ja) * | 2002-11-20 | 2004-06-17 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| US6921913B2 (en) * | 2003-03-04 | 2005-07-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained-channel transistor structure with lattice-mismatched zone |
| US7052946B2 (en) * | 2004-03-10 | 2006-05-30 | Taiwan Semiconductor Manufacturing Co. Ltd. | Method for selectively stressing MOSFETs to improve charge carrier mobility |
| US7172936B2 (en) * | 2004-09-24 | 2007-02-06 | Texas Instruments Incorporated | Method to selectively strain NMOS devices using a cap poly layer |
-
2004
- 2004-11-11 US US10/904,461 patent/US20060099765A1/en not_active Abandoned
-
2005
- 2005-11-08 TW TW094139082A patent/TW200629426A/zh unknown
- 2005-11-10 CN CN2005800385018A patent/CN101390209B/zh not_active Expired - Fee Related
- 2005-11-10 EP EP05820872A patent/EP1815506A4/en not_active Withdrawn
- 2005-11-10 KR KR1020077010335A patent/KR101063360B1/ko not_active Expired - Fee Related
- 2005-11-10 WO PCT/US2005/041051 patent/WO2006053258A2/en not_active Ceased
- 2005-11-10 JP JP2007541381A patent/JP4979587B2/ja not_active Expired - Fee Related
-
2007
- 2007-08-15 US US11/838,967 patent/US20070275522A1/en not_active Abandoned
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6512273B1 (en) * | 2000-01-28 | 2003-01-28 | Advanced Micro Devices, Inc. | Method and structure for improving hot carrier immunity for devices with very shallow junctions |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101063360B1 (ko) | 2011-09-07 |
| JP4979587B2 (ja) | 2012-07-18 |
| US20060099765A1 (en) | 2006-05-11 |
| EP1815506A4 (en) | 2009-06-10 |
| EP1815506A2 (en) | 2007-08-08 |
| US20070275522A1 (en) | 2007-11-29 |
| WO2006053258A3 (en) | 2008-01-03 |
| KR20070084030A (ko) | 2007-08-24 |
| CN101390209A (zh) | 2009-03-18 |
| WO2006053258A2 (en) | 2006-05-18 |
| TW200629426A (en) | 2006-08-16 |
| JP2008520110A (ja) | 2008-06-12 |
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Granted publication date: 20100929 Termination date: 20181110 |