CN101383302B - 具有悬垂连接堆叠的集成电路封装系统 - Google Patents
具有悬垂连接堆叠的集成电路封装系统 Download PDFInfo
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Abstract
本发明涉及一种具有悬垂连接堆叠的集成电路封装系统,公开了一种集成电路封装方法(900)包括:提供第一导线(302),使其与第二导线(304)相邻;在该第一导线(302)上方形成第一连接堆叠(312),并使该第一连接堆叠(312)悬垂于第二导线(304)上方;将集成电路元件(106)与该第一连接堆叠(312)相连;以及封装所述集成电路元件(106)和第一连接堆叠(312)。
Description
技术领域
本发明主要涉及集成电路封装系统,尤其涉及具有电性互连的集成电路封装系统。
背景技术
各部门、各行业和不同的国家地区都在不断要求电子工业提供更轻、更快、更小、多功能、更可靠并更符合成本效益的产品。为满足数量众多而又多种多样的客户的要求,需高度集成更多的电路以提供所需功能。几乎所有的应用都在不断地要求集成电路具有更小的尺寸,更好的性能以及更好的特性。
这些看似无尽的要求跟我们日常生活的产品一样常见。大量的手机、便携式电脑、录音机等便携式电子产品中以及汽车、飞机、工业控制系统等大型电子系统中都要求更小更密集的集成电路。
随着对更小并具有更多特性的电子产品的需求的不断增长,厂商正在努力寻求能够使集成电路包括更多特征同时缩小尺寸的方法。电子产品的日益小型化通常涉及元件的小型化、更高的集成电路(IC)封装密度、更高的性能以及更低的成本。随着新一代电子产品的发布,技术的进步使得用于制造这些电子产品的集成电路数量趋向于减少,同时产品的功能性在增加。
半导体封装结构在持续小型化,以增加封装于其中的元件密度,并缩小具有IC产品的最终产品的尺寸。其响应信息以及通讯设备的经常存在的小尺寸、低厚度、低成本以及不断提高的性能的要求。
不断的功能集成和小型化也带来了各种挑战。例如,尽管具有更高功能性的半导体产品可具有更小的尺寸,但仍然可能需要设置大量的输入/输出(I/O)界面,尺寸缩小增加了集成电路封装及集成电路载体的I/O密度或者缩小了I/O间距。
而不断增加的I/O密度带来了无数的制造问题。其中一些问题涉及集成电路制造领域,例如精细间距连接和连接的可靠性。另一些问题涉及将这些具有更高I/O密度的集成电路安装至载体以进行封装。还有一些问题涉及容置具有精细间距I/O的集成电路封装的印刷电路板或系统主板领域。
缩小I/O间距后的问题例如为在基板上进行引线键合仅限于指状焊片(bondfinger)或线路表面的平面宽度,以确保可靠的接合。部分位于指状焊片或线路宽度以外的接合可导致结合不良或与相邻的指状接脚短路。
因此,仍然需要提供低制造成本、高产量、并具有高信赖度的集成电路封装系统。针对不断增长的节约成本和提高效益的需求,解决上述问题更显得至关重要。
长久以来人们一直在努力寻求解决方案,但先前的发展并未给出任何公开或暗示,因此,上述问题的解决方案长久以来一直困惑着本领域的技术人员。
发明内容
本发明提供一种集成电路封装方法,包括:提供第一导线,使其与第二导线相邻;在该第一导线上方形成第一连接堆叠(stack),并使该第一连接堆叠悬垂(overhanging)于所述第二导线上方;将集成电路元件与该第一连接堆叠相连;以及封装该集成电路元件和第一连接堆叠。
本发明的特定实施例中,可在上述方式之外加入其他方式或者以其他方式取代上述方式。本领域的技术人员在参照附图阅读下面详细的描述后将明白这些方式。
附图说明
图1为本发明实施例中的集成电路封装系统的俯视图;
图2为图1所示的集成电路封装系统沿2-2线的剖视图;
图3为位于载体上方的连接堆叠的较详细俯视图;
图4为图3所示的位于载体上方的连接堆叠沿4-4线的较详细剖视图;
图5为部分载体在形成第一和第二底部结构阶段的俯视图;
图6为图5所示结构沿6-6线的剖视图;
图7为图5所示的结构处于形成第一连接堆叠和第二连接堆叠阶段的示意图;
图8为图7所示结构沿8-8线的剖视图;以及
图9为本发明实施例中用于制造集成电路封装系统的集成电路封装方法流程图。
具体实施方式
下面对实施例作充分描述以使本领域的技术人员能够制造并使用本发明。应当理解的是,基于本发明的揭露,其他实施方式将显而易见,并可在不背离本发明范围的情况下作出系统上的、工艺上的或机械上的变化。
下面的描述中给出了多种特定的细节,以便充分理解本发明。但是,显而易见的是,本发明可在不具有上述特定细节的情况下实施。为使本发明更为清楚,本发明略去对一些已知的电路、系统构造和工艺步骤的详细描述。同样,系统实施例的附图为半图示,并非按照比例绘制,尤其,为使表达清楚,附图中一些尺寸是经放大后显示的尺寸。一般地说,本发明可在任何方位下操作。
此外,为使描述清楚易懂,本发明揭露并描述的多个实施例中,彼此类似的特征采用类似的附图标记。为描述方便,将实施例编号为第一实施例、第二实施例等等,其并不具有其他意义或者限制本发明。
为说明目的,这里将术语“水平”定义为与集成电路的平面或表面平行的平面,而不管其方向。术语“垂直”是指与刚才定义过的“水平”垂直的方向。“上面”、“下面”、“底部”、“顶部”、“侧(如在“侧壁”中)”、“更高”、“更低”、“上面的”、“之上”、“之下”等术语都是相对于水平面而言。这里的“上面”指与元件直接接触。术语“处理”包括形成所述结构所需的材料沉积、图形化、曝光、显影、蚀刻、清洗、模压和/或材料去除等。术语“系统”对应其所用地方的上下文中所指的本发明的方法和装置。
现在参考图1,其中为根据本发明实施例的集成电路封装系统100的俯视图。该俯视图描绘了没有顶部遮盖的集成电路封装系统100。该俯视图中描述了,载体102具有若干导线104,载体102例如为层压基板(laminatesubstrate),导线104例如为绕线。
在载体102上方设置集成电路元件106,例如集成电路芯片。优选的,连接堆叠108,例如堆叠凸点支持基座,设在载体102的预定部分之上并位于导线104的上方。优选的,采用内部互连110,例如反向隔离式针脚接合(ReverseStand-offStitchBond:RSSB)线、带状接合线(RibbonBondWire)等连接集成电路设备106和预定选择的连接堆叠108。
为描述目的,集成电路封装系统100具有层压基板构成的载体102,但可以理解该集成电路封装系统100也可使用其他类型的载体102。例如,载体102可由具有接脚(未图示)的集成电路封装系统100的导线架(未图示)形成。同样为描述目的,采用集成电路封装系统100的实施例来显示本发明,尽管可以理解具有连接堆叠108的本发明可形成于不同的系统层次,例如形成于集成电路封装系统100不包括的印刷电路板或系统主板。
现在参考图2,图2显示了图1所示的集成电路封装系统100沿2-2线的剖视图。如剖视图所示,具有非主动面202和主动面204的集成电路元件106以非主动面202面向载体102的方式设置在载体102上方。优选的,主动面204上形成有电路。
优选的,连接堆叠108位于导线104上方,连接堆叠108提供内部互连110和导线104之间的电性连接路径。如前面所述,内部互连110连接集成电路元件106的主动面204和连接堆叠108。封装胶体206,例如环氧树脂成型材料(EMC),优选的位于集成电路元件106、内部互连110以及载体102上方的连接堆叠108上方。
现在参考图3,其中图3显示了位于载体102上方的连接堆叠108的较详细俯视图。如俯视图所示,部分载体102具有若干导线104,导线104包括第一导线302和第二导线304。第一导线302优选的具有第一线宽306。第二导线304优选的具有第二线宽308。为描述目的,图中所示的第一线宽306和第二线宽308大体相同,但可以理解的是于其他实施例中此两宽度可彼此不同。
间距310优选的说明第一导线302与第二导线304之间的间隔,其中,间距310可通过测量第一导线302与第二导线304的对等位置获得。例如,间距310可通过测量第一导线302一侧至第二导线304相同一侧获得。再例如,间距310也可通过测量第一导线302中心至第二导线304中心获得。为描述目的,间距310用来表示导线104间的间隔,但是可以理解部分导线104间的间隔可为不同值或不同间距(未图示)。
优选的,连接堆叠108被描述为包括位于第一导线302上方的第一连接堆叠312和位于第二导线304上方的第二连接堆叠314。优选的,第一连接堆叠312和第二连接堆叠314呈悬垂交错构造,从而以免第一连接堆叠312和第二连接堆叠314彼此接触。
优选的,第一连接堆叠312和第二连接堆叠314的中心分别位于或大致位于第一导线302和第二导线304上方。第一连接堆叠312优选的具有第一顶宽316;第二连接堆叠314优选的具有第二顶宽318。为描述目的,第一顶宽316和第二顶宽318大体相同,但可以理解的是,于其他实施例中第一顶宽316和第二顶宽318可彼此不同。
优选的,第一顶宽316大于第一线宽306,以使第一连接堆叠312延伸至第一导线302之外并悬垂于至少部分第二导线304的上方。优选的,第二顶宽318大于第二线宽308,以使第二连接堆叠314延伸至第二导线304之外并悬垂于至少部分第一导线302的上方。如果第一导线302和第二导线304不采用如图所示的悬垂交错结构,第一连接堆叠312将与第二连接堆叠314就会彼此接触,其中心将无法分别位于第一导线302和第二导线304上方。
内部互连110包括第一互连320和第二互连322。优选的,第一互连320连接第一连接堆叠312。第一连接堆叠312提供预定的表面积供设置第一互连320的第一针脚接合324和第一连接堆叠312连接。优选的,第二互连322连接第二连接堆叠314。第二连接堆叠314提供预定的表面积供设置第二互连322的第二针脚接合326和第二连接堆叠314连接。
第一连接堆叠312和第二连接堆叠314的悬垂交错构造也减弱甚至消除了第一互连320与第二互连322的不慎短路。此外,第一连接堆叠312和第二连接堆叠314的悬垂交错构造使集成电路封装系统100具有更高密度的内部互连110。而且,在悬垂交错构造中的连接堆叠108,进一步优选的使各连接堆叠108的中心位于导线104上方,因而能够实现更可靠的连接和信号质量。另外,在内部互连110的连接过程中,连接堆叠108可保护导线104免于受损。
现在参考图4,其中显示了图3所示的位于载体102上方的连接堆叠108沿4-4线的较详细剖视图。该剖视图显示第一连接堆叠312和部分第二连接堆叠314。在上述剖视图中,第二连接堆叠314未显示的另一部分与第一连接堆叠312重合。
上述剖视图显示出位于载体102上方的第一导线302和第二导线304。为描述目的,第一导线302和第二导线304位于载体102上方,但可以理解的是第一导线302和第二导线304也可以不位于载体102上方。例如,第一导线302和第二导线304可位于载体102内,并外露出如阻焊膜(soldermask)的掩膜(未图示)。第一导线302和第二导线304呈梯形截面,截面的短边朝向远离载体102的方向。
第一连接堆叠312包括具有第一底部宽度404的第一底部结构402和具有第一顶部宽度316的第一顶部结构406。优选的,第一顶部宽度316和第一底部宽度404分别通过测量第一顶部结构406和第一底部结构402的最宽部分获得。第一底部结构402和第一顶部结构406可以形成为多种结构类型,例如导电凸块,导电球,导电柱(conductivecolumn),导电杆(conductivepost)或者其结合等。为描述目的,图中的第一连接堆叠312具有两层:第一底部结构402和第一顶部结构406,但可以理解的是该第一连接堆叠312可具有不同数目的层。
优选的,第一连接堆叠312的中心位于第一导线302上方。优选的,第一底部结构402的中心位于第一导线302上方以及第一顶部结构406下方。优选的,第一针脚接合324位于第一顶部结构406上方。第一底部宽度404优选的大于第一线宽306,第一顶部宽度316大于第一底部宽度404,从而描述了第一连接堆叠312呈倒置的多层圆锥形结构。
同样,第二连接堆叠314包括具有第二底部宽度410的第二底部结构408和具有第二顶部宽度318的第二顶部结构412。优选的,第二顶部宽度318和第二底部宽度410分别通过测量第二顶部结构412和第二底部结构408的最宽部分获得。第二底部结构408和第二顶部结构412可以被形成为多种结构类型,例如导电凸块,导电球,导电柱,导电杆或者其结合等。为描述目的,图中的第二连接堆叠314被显示为具有第二底部结构408和第二顶部结构412构成的两层,但可以理解的是该第二连接堆叠314可具有不同数目的层。
优选的,第二连接堆叠314的中心位于第二导线304上方。优选的,第二底部结构408的中心位于第二导线304上方以及第二顶部结构412下方。优选的,第二针脚接合326位于第二顶部结构412上方。第二底部宽度410优选大于第二线宽308,第二顶部宽度318大于第二底部宽度410,从而显示第二连接堆叠314呈倒置的多层圆锥形结构。
呈悬垂交错构造的第一连接堆叠312和第二连接堆叠314为缩小第一导线302和第二导线304之间的间距310提供了额外的自由度。第一底部结构402和第二底部结构408分别与第一导线302和第二导线304形成居中的以及可靠的连接。同时,第一顶部结构406和第二顶部结构412分别为图3所示的第一互连320和图3所示的第二互连322提供了充足的表面积。
现在参考图5,其中显示了部分载体102在形成第一底部结构402和第二底部结构408阶段的俯视图。如俯视图所示,第一导线302和第二导线304基本上彼此平行。优选的,第一底部结构402和第二底部结构408分别形成于第一导线302和第二导线304上方。
优选的,具有第一底部宽度404的第一底部结构402延伸于具有第一线宽306的第一导线302上方,并进入第一导线302和第二导线304之间的空间502。优选的,第一底部结构402并不延伸于第二导线304上方。
优选的,具有第二底部宽度410的第二底部结构408延伸于具有第二线宽308的第二导线304上方,并进入第一导线302和第二导线304之间的空间502。优选的,第二底部结构408并不延伸于第一导线302上方。
现在参考图6,其中显示了图5所示结构沿图5的6-6线的剖视图。如剖视图所示,第一导线302和第二导线304之间具有间距310和空间502。优选的,具有第一底部宽度404的第一底部结构402位于第一导线302上方并部分覆盖该第一导线302。此外,优选的,第一底部结构402延伸进入第一导线302与第二导线304之间的空间502。第一底部结构402并不延伸于第二导线304上方。
优选的,第一底部凸起602延伸自第一底部结构402的顶部。优选的,第一底部凸起602具有平坦顶部表面。第一底部凸起602可辅助形成图4的第一连接堆叠312,例如形成金属间化合物(IMC)。
同样,优选的,该剖视图显示具有第二底部宽度410的第二底部结构408位于第二导线304上方并部分覆盖该第二导线304。此外,优选的,第二底部结构408延伸进入第一导线302与第二导线304之间的空间502。第二底部结构408并不延伸于第一导线302上方。
优选的,第二底部凸起604延伸自第二底部结构408的顶部。优选的,第二底部凸起604具有平坦顶部表面。第二底部凸起604可辅助形成图4的第二连接堆叠314,例如形成金属间化合物(IMC)。
现在参考图7,其中显示了图5所示结构在形成第一连接堆叠312与第二连接堆叠314阶段的示意图。图7的结构显示了第一导线302和第二导线304之间具有间距310和空间502。优选的,第一顶部结构406和第二顶部结构412分别形成于图6所示的第一底部结构402和图6所示的第二底部结构408上方,从而形成第一连接堆叠312和第二连接堆叠314。
优选的,具有第一顶部宽度316的第一顶部结构406延伸于第一导线302和空间502的上方并悬垂于至少部分第二导线304的上方。同样,优选的具有第二顶部宽度318的第二顶部结构412延伸于第二导线304和空间502的上方并悬垂于至少部分第一导线302的上方。第一连接堆叠312和第二连接堆叠314的悬垂交错构造减弱甚至避免了第一顶部结构406和第二顶部结构412的彼此接触。
现在参考图8,其中显示了图7所示结构沿图7的8-8线的剖视图。剖视图显示了第一导线302与第二导线304之间的间距310和空间502。优选的,具有第一顶部宽度316的第一顶部结构406位于第一底部结构402和第一导线302上方并延伸进入第一导线302和第二导线304之间的空间502。优选的,第一顶部结构406悬垂于至少部分第二导线304的上方。
优选的,第一顶部凸起802延伸自第一顶部结构406的顶部。优选的,第一顶部凸起802具有平坦顶部表面面。第一顶部凸起802可辅助形成图4的第一连接堆叠312,例如形成金属间化合物(IMC)。第一顶部凸起802还可提供平坦表面,以与图3所示的第一互连320的第一针脚接合324连接。
同样,优选的,该剖视图显示具有第二顶部宽度318的第二顶部结构412的一部分位于第二底部结构408和第二导线304上方并延伸进入第一导线302和第二导线304之间的空间502。优选的,第二顶部结构412悬垂于至少部分第一导线302的上方。
优选的,第二顶部凸起804延伸自第二顶部结构412的顶部。优选的,第二顶部凸起804具有平坦顶部表面。第二顶部凸起804可辅助形成图4的第二连接堆叠314,例如形成金属间化合物(IMC)。第二顶部凸起804还可提供平坦表面,以与图3所示的第二互连322的第二针脚接合326连接。
现在参考图9,其中为根据本发明实施例用于制造集成电路封装系统100的集成电路封装方法900的流程图。该方法900包括:步骤902,提供与第二导线相邻的第一导线;步骤904,在第一导线上方形成第一连接堆叠,并使第一连接堆叠悬垂于第二导线上方;步骤906,将集成电路元件与第一连接堆叠相连;以及步骤908,封装该集成电路元件和第一连接堆叠。
本发明另一重要方面是为降低成本、简化系统、提高性能的历史趋势提供了有益的支持和帮助。
本发明的上述和其他有价值的方面继续进一步推进了技术向更高级别的发展。
因此,在这里揭示了本发明的集成电路封装系统为集成电路封装系统提升产量,增加可靠性,降低成本提供了重要的并且在此之前未曾知晓并未曾使用的解决方案、性能和功能方式。其作为结果的过程和构造直接、简单、符合成本效益、灵活多变、准确、灵敏而有效,并可适应已知的元件而进行迅速、经济、有效的制造、应用和使用。
尽管结合特定的最佳模式对本发明作了描述,可以理解的是根据上述描述,本领域的技术人员可作替换、修改和变更。从而,该替换、修改和变更应当落在所要求的权利要求范围内。这里所给出的及附图显示的全部内容都是描述性的并且是非限制性的。
Claims (10)
1.一种集成电路封装方法(900),包括:
提供第一导线(302),使其与第二导线(304)相邻;
在该第一导线(302)上方形成第一连接堆叠(312),并使该第一连接堆叠(312)悬垂于至少部分该第二导线(304)的上方;
在该第二导线(304)上方形成第二连接堆叠(314),并使该第二连接堆叠(314)悬垂于至少部分该第一导线(302)的上方,与该第一连接堆叠(312)形成交错构造;
将集成电路元件(106)与该第一连接堆叠(312)相连;
将该集成电路元件(106)与该第二连接堆叠(314)相连;
将第一互连(320)与该第一连接堆叠(312)和该集成电路元件(106)相连;
将第二互连(322)与该第二连接堆叠(314)和该集成电路元件(106)相连;以及
封装该集成电路元件(106)、该第一连接堆叠(312)、该第二连接堆叠(314)、该第一互连(320)和该第二互连(322)。
2.如权利要求1所述的方法(900),其中:
该第一连接堆叠(312)包括第一底部结构(402)与第一顶部结构(406),该第一顶部结构(406)的宽度大于该第一底部结构(402)的宽度,且该第一互连(320)连接至该第一顶部结构(406);以及
该第二连接堆叠(314)包括第二底部结构(408)与第二顶部结构(412),该第二顶部结构(412)的宽度大于该第二底部结构(408)的宽度,且该第二互连(322)连接至该第二顶部结构(412)。
3.如权利要求2所述的方法(900),其中,在第一导线(302)上方形成第一连接堆叠(312)并使其悬垂于第二导线(304)上方的方法包括:
在第一导线(302)上方形成该第一底部结构(402),使该第一底部结构(402)悬垂于第一导线(302)与第二导线(304)之间的空间(502)上方;以及
在该第一底部结构(402)上方形成该第一顶部结构(406),并使该第一顶部结构(406)悬垂于空间(502)和至少部分第二导线(304)的上方。
4.如权利要求1所述的方法(900),其中,在第一导线(302)上方形成第一连接堆叠(312)包括至少部分的覆盖第一导线(302)的侧面。
5.如权利要求1所述的方法(900),其中,形成第一连接堆叠(312)的中心位于第一导线(302)上方。
6.一种集成电路封装系统(100),包括:
第一导线(302);
第二导线(304),与第一导线(302)相邻;
第一连接堆叠(312),位于第一导线(302)上方并悬垂于至少部分该第二导线(304)的上方;
第二连接堆叠(314),位于该第二导线(304)上方并悬垂于至少部分该第一导线(302)的上方,与该第一连接堆叠(312)形成交错构造;以及
集成电路元件(106),连接该第一连接堆叠(312)和该第二连接堆叠(314);
第一互连(320),连接该第一连接堆叠(312)和该集成电路元件(106);
第二互连(322),连接该第二连接堆叠(314)和该集成电路元件(106);以及
封装胶体(206),覆盖该集成电路元件(106)、该第一连接堆叠(312)、该第二连接堆叠(314)、该第一互连(320)和该第二互连(322)。
7.如权利要求6所述的系统(100),其中:
该第一连接堆叠(312)包括第一底部结构(402)与第一顶部结构(406),该第一顶部结构(406)的宽度大于该第一底部结构(402)的宽度,且该第一互连(320)连接至该第一顶部结构(406);以及
该第二连接堆叠(314)包括第二底部结构(408)与第二顶部结构(412),该第二顶部结构(412)的宽度大于该第二底部结构(408)的宽度,且该第二互连(322)连接至该第二顶部结构(412)。
8.如权利要求7所述的系统(100),其中,位于第一导线(302)上方并悬垂于第二导线(304)上方的第一连接堆叠(312)包括:
该第一底部结构(402),位于第一导线(302)上方,并悬垂于第一导线(302)和第二导线(304)之间的空间(502)上方;以及
该第一顶部结构(406),位于该第一底部结构(402)上方,并悬垂于空间(502)和至少部分第二导线(304)的上方。
9.如权利要求6所述的系统(100),其中,位于第一导线(302)上方的第一连接堆叠(312)包括至少部分的覆盖第一导线(302)的侧面。
10.如权利要求6所述的系统(100),其中,第一连接堆叠(312)的中心位于第一导线(302)上方。
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TW200903679A (en) | 2009-01-16 |
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