CN101361180A - 高频元件模块及其制造方法 - Google Patents

高频元件模块及其制造方法 Download PDF

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CN101361180A
CN101361180A CNA2007800015433A CN200780001543A CN101361180A CN 101361180 A CN101361180 A CN 101361180A CN A2007800015433 A CNA2007800015433 A CN A2007800015433A CN 200780001543 A CN200780001543 A CN 200780001543A CN 101361180 A CN101361180 A CN 101361180A
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frequency component
device module
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CN101361180B (zh
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吉田大广
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Toshiba Corp
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Abstract

本发明提供一种高频元件模块及其制造方法，本发明的一种方式的高频元件模块具有：绝缘基板，其表面设有电极，背面设有接地基板；高频元件，设置在该绝缘基板上，该元件的端子与所述电极连接；灌封部件，覆盖该高频元件；和金属层，设置在该灌封部件上并且与所述接地基板连接。

Description

高频元件模块及其制造方法
发明领域
本发明涉及一种嵌入微波元件等高频元件的高频元件模块，尤其涉及其结构。
背景技术
伴随近年来的信息化社会的发展，对增大传输容量的需求日益增强，并且要求传输容量更大的系统和高度的调制方式，随之还要求具有高增益而且低价格的器件。
针对这种需求，例如日本公开公报特开2001-345419号公报公开了一种模块，对在陶瓷单板上设置金属板并固定粘接了元件的简易型封装体涂覆聚酰亚胺(poliymide)来保护表面，在其上覆盖用于保护导线和元件的灌封(potting)部件。
但是，灌封部件具有绝缘性，在高性能的元件和高增益的元件中放射电磁场，对外部造成不良影响，而且反之由于周围电磁场和自身产生的微波输出的蔓延，使得性能明显恶化，所以有时用途受到限定。
并且，日本专利公开公报特开2003-298004号公报公开了一种高频元件模块，为了防止在高频频带动作的能动元件芯片之间的电磁波干扰，利用分散了镍粒子等金属粒子的绝缘树脂层使其密封。
但是，在这种高频元件模块中，金属粒子有可能被腐蚀，存在不能长期进行充足的电磁屏蔽的问题。
发明内容
本发明是鉴于上述现有高频元件模块的问题而提出的，其目的在于，提供一种在长时间内电磁波对外部的影响以及受来自外部的影响较小，因此电气性能良好而且结构简单并且价格低廉的高频元件模块及其制造方法。
根据本发明的一种方式(aspect)，提供一种高频元件模块，其特征在于，具有：绝缘基板；高频元件，设置在该绝缘基板上；灌封部件，覆盖该高频元件；和金属层，设置在该灌封部件上，并且至少一端接地。
根据本发明的其他方式，提供一种高频元件模块，其特征在于，具有：绝缘基板，其表面设有电极，背面设有接地基板；高频元件，设置在该绝缘基板上，该元件的端子与所述电极连接；灌封部件，覆盖该高频元件；和金属层，设置在该灌封部件上，并且与所述接地基板连接。
根据本发明，可以实现一种高频元件模块，在长时间内电磁波对外部的影响以及受来自外部的影响较小，因此电气性能良好而且结构简单并且价格低廉。
附图说明
图1是表示本发明的第1实施方式的结构的剖视图。
图2是本发明的第1实施方式的俯视图。
图3是说明本发明的第1实施方式的制造方法的图。
图4是表示本发明的第2实施方式的结构的剖视图。
图5是说明在本发明的第2实施方式的布线图形的图。
具体实施方式
以下，使用附图说明本发明的实施方式。
<第1实施方式>
图1是表示本发明的第1实施方式的高频元件模块的结构的剖视图，图2是该高频元件模块的俯视图。图1表示图2中的A1-A2剖面。
高频元件模块包括：绝缘基板12，其利用陶瓷构成，具有预定的孔部11，在表面设有布线；布线于该绝缘基板12的表面的电极13a、13b；包括孔部11的背面在内设置的接地基板13；设置在该接地基板13上的孔部11内的垫台部14；固定在该垫台部14上的高频元件15；利用例如金构成的导线17a、17b，其将该高频元件15的元件端子16a、16b和上述绝缘基板12上的电极13a、13b连接；灌封部件18，覆盖在这些导线17a、17b和上述高频元件15上并密封它们；和设置在该灌封部件18上的金属膜19。高频元件15例如是场效应晶体管(FET)，在其周围涂覆有表面保护部件例如聚酰亚胺20，用于保护该元件的表面并改善紧密粘接性。
下面，说明该实施方式的高频元件模块的制造方法。到设置灌封部件18为止可以采用与现有技术相同的方法。然后，如图3所示，设置仅留出灌封部件18上部的必要部分的掩膜图形31，利用该掩膜图形蒸镀金属材料例如铝，由此设置金属膜19。金属膜19的厚度优选为1～5微米左右。
并且，使金属膜19形成为图2所示的大小和形状。即，在与图1所示剖面正交的方向的绝缘基板12上，按照图2所示设有接地端子22a、22b，灌封部件18上的金属膜19形成为与这些接地端子22a、22b连接的形状。接地端子22a、22b与上述接地基板13连接。
另一方面，绝缘基板12的孔部11包括电极13a、13b在内被灌封部件18覆盖。其上的金属膜19被设置成为不接触上述电极13a、13b。通过使金属膜19形成为这种大小和形状，金属膜19与接地端子22a、22b相连接，并且被电磁屏蔽。
如果使用铝作为金属膜19，则可以获得屏蔽效果高、价格低廉的高频元件模块。
根据该实施方式，可以几乎完全电磁屏蔽高频元件15，可以减小外部的影响。而且，绝缘性提高，所以能够实现高增益的高频元件，可以获得价格低廉的高频元件模块。
<第2实施方式>
但是，在被用作上述高频元件的单片微波集成电路(MMIC：MonolithicMicrowave Integrated circuits)元件等中，为了满足小型化要求，频繁地变更模块的端子位置。在这种情况下，虽然认为也可以变更接合线，但是在MMIC元件等高增益的器件中，如果形成导线在上述高频元件上面跨越的形式，则有时会产生获得器件所产生的电磁场的感应并谐振等不良情况。下面叙述的第2实施方式是适合于这种情况的高频元件模块。
图4是表示该第2实施方式的高频元件模块的结构的剖视图。符号41～52b对应于图1中的符号11～22b。
例如，在利用陶瓷构成的绝缘基板42的孔部41设置有垫台部41，在其上安装有例如作为MMIC元件的高频元件45，在背面设置有接地基板43。在绝缘基板42的表面设有电极43a、43c和电极43b、43d，利用金构成的导线47a、47b等连接这些电极。在高频元件45的周围涂覆有作为该元件的表面保护部件的例如聚酰亚胺50。高频元件45和导线被利用灌封部件48密封。在该灌封部件48上，与上述第1实施方式相同，例如通过蒸镀设置有铝的厚度为1～5微米的金属膜49。
在该实施方式中，在该金属膜49上涂覆有作为绝缘层的有机类聚酰亚胺53，再在其上设有如图5所示的例如用于连接上述电极43b和电极43c的布线图形54。图4是点线B1、B2之间的剖视图。
如图4所示，在其上涂覆有例如有机类聚酰亚胺55，作为保护该布线图形54的保护层。
根据本发明的实施方式，即使连接作为元件的端子的电极，也不会产生谐振等，具有能够获得稳定而且低廉的高频元件模块的优点。
在上述实施方式中，作为高频元件，说明了使用FET和MMIC元件的情况，但本发明不限于此，也可以适用于具有在普通微波等高频中使用的元件的模块。
并且，在上述实施方式中，说明了在设于绝缘基板的孔部设置高频元件并利用灌封部件密封的结构的高频元件模块。但是，本发明不限于这种模块，也可以适用于在绝缘基板上设置高频元件并利用灌封部件覆盖的结构的高频元件模块。
在上述实施方式中，说明了均在高频元件周围涂覆聚酰亚胺作为表面保护部件的情况。如果将聚酰亚胺涂覆于高频元件上，则可以保护高频元件，并且具有可以提高高频元件与灌封部件的紧密粘接性的效果。而且，只要高频元件与灌封部件的紧密粘接性良好，则在本发明中也可以涂覆其他材料作为表面保护部件，而不限于聚酰亚胺。另外，如果不需要保护高频元件，则在本发明中未必需要表面保护部件。
在上述实施方式的说明中，说明了在灌封部件上设置有金属膜的情况，但本发明不仅可以设置金属膜，也可以设置普通的金属层。
并且，在上述实施方式中，说明了在绝缘基板的背面设置有接地基板，与该接地基板连接的接地端子被设置在绝缘基板的表面上的情况。但是，本发明不限于这种结构的模块，只要形成于上述灌封部件上的金属层至少一端被接地即可。一般来说，本发明的高频元件模块只要具有以下部分即可，即，绝缘基板，设置在该绝缘基板上的高频元件，覆盖该高频元件的灌封部件，和设置在该灌封部件上并且至少一端被接地的金属层。
并且，在上述实施方式中，说明了在绝缘基板上设置有一个高频元件的情况，但是也可以设置有多个高频元件。
本发明不限于上述实施方式，可以在本发明的技术思想范围内实施各种变形。

Claims (16)

1.一种高频元件模块，其特征在于，具有：
绝缘基板；
高频元件，设置在该绝缘基板上；
灌封部件，覆盖该高频元件；和
金属层，设置在该灌封部件上，并且至少一端接地。
2.一种高频元件模块，其特征在于，具有：
绝缘基板，表面设有电极，背面设有接地基板；
高频元件，设置在该绝缘基板上，其端子与所述电极连接；
灌封部件，覆盖该高频元件；和
金属层，设置在该灌封部件上，并且与所述接地基板连接。
3.根据权利要求2所述的高频元件模块，其特征在于，
所述金属层是铝薄膜。
4.一种高频元件模块，其特征在于，具有：
绝缘基板，具有孔部，且表面设有电极；
接地基板，在该绝缘基板的背面至少覆盖所述孔部；
高频元件，设置在所述孔部内，其端子与所述电极连接；
灌封部件，覆盖该高频元件；和
金属层，设置在该灌封部件上，并且与所述接地基板连接。
5.根据权利要求4所述的高频元件模块，其特征在于，
所述金属层是铝薄膜。
6.一种高频元件模块，其特征在于，具有：
绝缘基板，表面设有电极、背面设有接地基板；
高频元件，设置在该绝缘基板上，其端子与所述电极连接；
表面保护部件，为了保护该高频元件的表面而被涂覆；
灌封部件，密封涂覆了该表面保护部件的所述高频元件；
金属层，设置在该灌封部件上，并且与所述接地基板连接；
绝缘层，设置成覆盖该金属层；
布线图形，设置在该绝缘层上，并且与所述电极连接；和
保护层，设置在该布线图形上。
7.根据权利要求6所述的高频元件模块，其特征在于，
所述表面保护部件是聚酰亚胺。
8.根据权利要求7所述的高频元件模块，其特征在于，
所述金属层是铝薄膜。
9.根据权利要求8所述的高频元件模块，其特征在于，
所述高频元件是单片微波集成电路元件。
10.一种高频元件模块，其特征在于，具有：
绝缘基板，具有孔部，且表面设有电极；
接地基板，在该绝缘基板的背面至少覆盖所述孔部；
高频元件，设置在所述孔部内，其端子与所述电极连接；
表面保护部件，为了保护该高频元件的表面而被涂覆；
灌封部件，密封涂覆了该表面保护部件的所述高频元件；
金属层，设置在该灌封部件上，并且与所述接地基板连接；
绝缘层，设置成覆盖该金属层；
布线图形，设置在该绝缘层上，并且与所述电极连接；和
保护层，设置在该布线图形上。
11.根据权利要求10所述的高频元件模块，其特征在于，
所述表面保护部件是聚酰亚胺。
12.根据权利要求11所述的高频元件模块，其特征在于，
所述金属层是铝薄膜。
13.根据权利要求12所述的高频元件模块，其特征在于，
所述高频元件是单片微波集成电路元件。
14.一种高频元件模块的制造方法，其特征在于，具有以下步骤，
在表面设有电极、背面设有接地基板的绝缘基板上，设置其端子与所述电极连接的高频元件，
利用灌封部件覆盖该高频元件，
在该灌封部件上设置金属层，
将该金属层与所述接地基板连接。
15.一种高频元件模块的制造方法，其特征在于，具有以下步骤，
在表面设有电极、背面设有接地基板的绝缘基板上，设置其端子与所述电极连接的高频元件，
在该高频元件上涂覆用于保护其表面的表面保护部件，
利用灌封部件密封涂覆了该表面保护部件的所述高频元件，
在该灌封部件上设置与所述接地基板连接的金属层，
设置覆盖该金属层的绝缘层，
在该绝缘层上设置与所述电极连接的布线图形，
在该布线图形上设置保护层。
16.根据权利要求15所述的高频元件模块的制造方法，其特征在于，所述表面保护部件是聚酰亚胺。
CN2007800015433A 2006-05-16 2007-05-11 高频元件模块 Expired - Fee Related CN101361180B (zh)

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Families Citing this family (13)

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Publication number Priority date Publication date Assignee Title
US8053872B1 (en) 2007-06-25 2011-11-08 Rf Micro Devices, Inc. Integrated shield for a no-lead semiconductor device package
US8062930B1 (en) 2005-08-08 2011-11-22 Rf Micro Devices, Inc. Sub-module conformal electromagnetic interference shield
US20090002969A1 (en) 2007-06-27 2009-01-01 Rf Micro Devices, Inc. Field barrier structures within a conformal shield
US8959762B2 (en) 2005-08-08 2015-02-24 Rf Micro Devices, Inc. Method of manufacturing an electronic module
US7956429B1 (en) 2007-08-02 2011-06-07 Rf Micro Devices, Inc. Insulator layer based MEMS devices
US9137934B2 (en) 2010-08-18 2015-09-15 Rf Micro Devices, Inc. Compartmentalized shielding of selected components
US8835226B2 (en) 2011-02-25 2014-09-16 Rf Micro Devices, Inc. Connection using conductive vias
US9627230B2 (en) 2011-02-28 2017-04-18 Qorvo Us, Inc. Methods of forming a microshield on standard QFN package
US9807890B2 (en) 2013-05-31 2017-10-31 Qorvo Us, Inc. Electronic modules having grounded electromagnetic shields
US11127689B2 (en) 2018-06-01 2021-09-21 Qorvo Us, Inc. Segmented shielding using wirebonds
US11219144B2 (en) 2018-06-28 2022-01-04 Qorvo Us, Inc. Electromagnetic shields for sub-modules
US11114363B2 (en) 2018-12-20 2021-09-07 Qorvo Us, Inc. Electronic package arrangements and related methods
US11515282B2 (en) 2019-05-21 2022-11-29 Qorvo Us, Inc. Electromagnetic shields with bonding wires for sub-modules

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2524202B1 (fr) * 1982-03-23 1985-11-08 Thomson Csf Module preadapte pour diode hyperfrequence, et procede de realisation de la connexion de polarisation de la diode
JP2987950B2 (ja) * 1991-01-25 1999-12-06 日立化成工業株式会社 ポリイミド系樹脂ペーストおよびこれを用いたｉｃ
JP2001035956A (ja) * 1999-07-19 2001-02-09 Sanyo Electric Co Ltd 半導体装置
JP3500335B2 (ja) * 1999-09-17 2004-02-23 株式会社東芝 高周波回路装置
JP2001345419A (ja) 2000-05-31 2001-12-14 Hitachi Ltd 一体型高周波無線回路モジュール
JP2003179181A (ja) * 2001-12-11 2003-06-27 Ngk Spark Plug Co Ltd 樹脂製配線基板
JP2003298004A (ja) 2002-04-04 2003-10-17 Fujitsu Ltd 素子間干渉電波シールド型高周波モジュール及び電子装置
JP2005109306A (ja) * 2003-10-01 2005-04-21 Matsushita Electric Ind Co Ltd 電子部品パッケージおよびその製造方法
JP2005340656A (ja) * 2004-05-28 2005-12-08 Matsushita Electric Ind Co Ltd 高周波集積回路装置及びその製造方法

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