TWI336510B - - Google Patents

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Publication number
TWI336510B
TWI336510B TW096113658A TW96113658A TWI336510B TW I336510 B TWI336510 B TW I336510B TW 096113658 A TW096113658 A TW 096113658A TW 96113658 A TW96113658 A TW 96113658A TW I336510 B TWI336510 B TW I336510B
Authority
TW
Taiwan
Prior art keywords
disposed
frequency component
electrode
metal layer
sealing material
Prior art date
Application number
TW096113658A
Other languages
English (en)
Other versions
TW200802743A (en
Inventor
Tomohiro Yoshida
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW200802743A publication Critical patent/TW200802743A/zh
Application granted granted Critical
Publication of TWI336510B publication Critical patent/TWI336510B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4805—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1306—Field-effect transistor [FET]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Casings For Electric Apparatus (AREA)
  • Waveguides (AREA)
  • Waveguide Connection Structure (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Description

1336510 (1) 九、發明說明 【發明所屬之技術領域】 本發明係關於埋入著微波元件等高頻元件之高頻元件 模組，尤其是，與其構造相關。 【先前技術】 隨著最近之資訊化社會的發展，對於增加傳送容量之 要求也愈來愈強烈，而且，也要求較大傳送容量之系統及 高度之調變方式。而且，也要求具有高利得且低價格之裝 置。 針對如上所示之要求，如日本公開公報特間200 1 -3 45 4 1 9號公報所示，對於陶瓷之單板具備金屬板且固設著 元件之簡易型封裝實施聚醯亞胺（polyimide)之塗佈來保 護表面，並在其上塗佈以保護絲線及元件爲目的之注封 (potting)材的模組係大家所熟知。 注封材雖然具有絕緣性，然而，高性能之元件及高利 得之元件卻會放射電磁場，而對外部產生不良影響，或者 ，相反地，因爲周圍之電磁場及自己所發出之微波之輸出 之潛通而導致性能明顯劣化，而使其用途受到限制。 此外，日本特許公開公報特開2003-298004係記載著 ，爲了防止以高頻段驅動之能動元件晶片間之電磁波干涉 ，以分散著Ni粒子等之金屬粒子之絕緣樹脂層進行密封 之高頻元件模組。 然而，因爲此種高頻元件模組之金屬粒子可能會腐蝕 -4- (2) (2)1336510 ’而有無法長期充分實.現電磁遮蔽之問題。 【發明內容】 本發明有鑑於上述之傳統之高頻元件模組之問題點， 提供一種，電磁波對外部之影響、及受到外部之影響，可 以長期保持於較小，具有良好電氣性能且構造簡單又價廉 之高頻元件模組及其製造方法。 依據本發明之一觀點（aspect)，係提供其特徵爲具有 :絕緣基板；配設於該絕緣基板之高頻元件；用以覆蓋該 高頻元件之注封材；以及配設於該注封材之上，且至少〜 端進行接地之金屬層；之高頻元件模組。 依據本發明之其他觀點，係提供其特徵爲具有：於表 面配設著電極且於背面配設著接地基板之絕緣基板；配設 於該絕緣基板，其端子連結於前述電極之高頻元件；用以 覆蓋該高頻元件之注封材：以及配設於該注封材之上，_ 結於前述接地基板之金屬層；之高頻元件模組。 依據本發明，可以得到電磁波對外部之影響及受到外 部之影響可以長期保持於較小，因而具有良電氣性能，_ 造簡單且價廉之高頻元件模組。 【實施方式】 以下，參照圖面，針對本發明之實施形態，進行說明 -5- 1336510 ⑶ <第1實施形態> , 第1圖係本發明第1實施形態之高頻元件模組之構造之 剖面圖，第2圖係該高頻元件模組之上面圖。第1圖係第2 圖之A1-A2之剖面。 由：具有特定之孔部11，由陶瓷所構成，於表面配設 著配線之絕緣基板12;配線於該絕緣基板12之表面之電極 13a、13b:以含有孔部11之背面之方式配設之接地基板13 ;配設於該接地基板13上之孔部11內之台部14;固定於該 台部14之上之高頻元件15 ;用以連結該高頻元件15之元件 端子16a、16b及上述絕緣基板12上之電極13a、13b，例 如由金所構成之絲線1 7 a、1 7 b ;用以覆蓋於該等絲線1 7 a 、17b及上述高頻元件15之上來進行密封之注封材18;以 及配設於該注封材18之上之金屬膜19;所構成。高頻元件 15係例如場效電晶體（FET)，其周圍塗佈著用以保護該元 件之表面且密合性良好之例如聚醯亞胺20之表面保護材。 其次，針對本實施形態之高頻元件模組之製造方法進 行說明。至配設注封材1 8爲止，利用與傳統相同之方法即 可。其次，如第3圖所示，配設只有注封材18之上部之必 要部份鏤空之遮罩圖案31，利用該遮罩圖案實施例如鋁之 金屬材料之蒸鍍來配設金屬膜19。金屬膜19之厚度應爲1 〜5微米程度。 此外，金屬膜1 9係如第2圖所示之大小及形狀。亦即 ，係於垂直於第1圖所示之剖面之方向之絕緣基板12上， 配設如第2圖所示之接地端子22a、22b’注封材18上之金 -6- (5) 1336510 部41，於其上，固定著例如MMIC元件之高頻元件45，背 . 面則配設著接地基板43。於絕緣基板42之表面，配設著電 極43a、43c及電極43b、43d，由金所構成之絲線47a、 4 7b等連結於該等電極。於高頻元件45之周圍，塗佈著例 • 如聚醯亞胺50之該元件之表面保護材。高頻元件45及絲線 係被注封材48所密封。於該注封材48之上，與上述第1實 施形態相同，配設著金屬膜49，例如，以蒸鍍配設1〜5微 φ 米之厚度之鋁。 本實施形態時，於該金屬膜49之上，塗佈著有機系之 聚醯亞胺53做爲絕緣層，此外，於其上，如第5圖所示， 配設例如用以連結上述電極43b及電極43c之配線圖案54 。第4圖係虛線B 1、B 2間之剖面圖。 如第4圖所示，於其上，塗佈例如有機系之聚醯亞胺 55當做用以保護該配線圖案54之保護層。 依據本發明之本實施形態，即使連結元件端子之電極 φ 間，也不會發生振盪等，而具有可得到安定且價廉之高頻 元件模組之優點。 上述實施形態時，係針對採用FET及MM 1C元件做 ' 爲高頻元件時進行說明，然而，本發明並未受限於此，也 ' 可使用於一般之具有應用於微波等高頻之元件之模組。 此外，上述實施形態時，係針對於配設於絕緣基板之 孔部配設著高頻元件並以注封材進行密封之構造之高頻元 件模組進行說明。然而，本發明並未受限於上述模組，亦 可應用於在絕緣基板之上配設高頻元件並以注封材覆蓋之 -8 - (6) (6)1336510 構造之_頻兀件模組。. 上述實施形態皆針對於高頻元件之周圍塗佈聚醯亞胺 當做表面保護材時進行說明。將聚醯亞胺塗佈於高頻元件 塗佈’不但可保護高頻元件’而且，具有提高高頻元件及 注封材之密合性之效果。然而，本發明亦可依據高頻元件 及注封材之密合性，塗佈聚醯亞胺以外之其他材料當做表 面保護材。此外，無需保護高頻元件時，本發明也不一定 需要表面保護材。 上述實施形態係針對於注封材之上配設金屬膜時進行 說明，然而，本發明並未受限於金屬膜，一般而言，以配 設金屬層爲佳。 此外，上述實施形態係針對於絕緣基板之背面配設接 地基板’且將連結於該接地基板之接地端子配設於絕緣基 板之表面時進行說明。然而，本發明並未受限於該構造之 模組，形成於上述注封材之上之金屬層只要至少一端接地 即可。一般而言，本發明之高頻元件模組只要具有：絕緣 基板、配設於該絕緣基板之高頻元件、用以覆蓋該高頻元 件之注封材、以及配設於該注封材之上，且至少一端進行 接地之金屬層；即可。 此外，上述實施形態係針對於絕緣基板之上配設1個 高頻元件時進行說明，然而，亦可配設複數個高頻元件。 本發明並未受限於上述實施形態，在本發明之技術思 想之範圍內可進行各種變形。 (7) (7)1336510 【圖式簡單說明】 第1圖係本發明之第1實施形態之構造之剖面圖。 第2圖係本發明之第1實施形態之上面圖。 第3圖係本發明之第1實施形態之製造方法之說明圖。 第4圖係本發明之第2實施形態之構造之剖面圖。 第5圖係本發明之第2實施形態之配線圖案之說明圖。 【主要元件符號說明】 11 :孔部 1 2 :絕緣基板 1 3 :接地基板 1 3 a .電極 1 3 b :電極 1 4 :台部 1 5 :高頻元件 16a :元件端子 16b :元件端子 1 7 a .絲線 1 7 b :絲線 1 8 :注封材 19 :金屬膜 2〇 :聚醯亞胺 22a :接地端子 22b :接地端子 -10- 1336510 遮罩圖案 孔部 絕緣基板 接地基板 :電極 :電極 台部 高頻元件 :元件端子 :元件端子 :絲線 :絲線 注封材 金屬膜 聚醯亞胺 :接地端子 :接地端子 聚醯亞胺 配線圖案 5 5 :聚醯亞胺

Claims (1)

1336510 十 0 • (1) 、申請專利範圍 L一種高頻元件模組，其特徵爲具有： 絕緣基板； 高頻元件，配設於該絕緣基板； 注封材，用以覆蓋該高頻元件；以及 金屬層，配設於該注封材之上，且至少一端進行接地 2·—種商頻元件模組，其特徵爲具有： 絕緣基板，於表面配設著電極且於背面配設著接地基 _ 板 ， 高頻元件，配設於該絕緣基板，其端子連結於前述電 極 0 ， 注封材，用以覆蓋該高頻元件；以及 金屬層，配設於該注封材之上，連結於前述接地基板 • 中 3 ·如申請專利範圍第2項所記載之高頻元件模組，其 前述金屬層係鋁之薄膜。 4. 一種高頻元件模組，其特徵爲具有： 絕緣基板，具有孔部，於表面配設著電極： 接地基板，在該絕緣基板之背面至少覆蓋著前述孔部 極； 高頻元件，配設於前述孔部內，其端子連結於前述電 -12- (2) (2)1336510 注封材，用以覆蓋.該高頻元件；以及 金屬層，配設於該注封材之上，連結於前述接地基板 〇 5.如申請專利範圍第4項所記載之高頻元件模組，其 中 前述金屬層係鋁之薄膜。 6 . —種高頻元件模組，其特徵爲具有： 絕緣基板，於表面配設著電極且於背面配設著接地基 板； 高頻元件，配設於該絕緣基板，其端子連結於前述電 極； 表面保護材，以保護該高頻元件之表面爲目的而塗佈 t 注封材，用以密封塗佈著該表面保護材之前述高頻元 件； 金屬層，配設於該注封材之上，連結於前述接地基板 絕緣層，以覆蓋該金屬層之方式配設； 配線圖案，配設於該絕緣層之上，連結於前述電極； 以及 保護層，配設於該配線圖案之上。 7 ·如申請專利範圍第6項所記載之高頻元件模組，其 中 前述表面保護材係聚醯亞胺。 -13- (3) (3)1336510 8 .如申請專利範圍.第7項所記載之高頻元件模組，其 中 前述金屬層係鋁之薄膜。 9. 如申請專利範圍第8項項所記載之高頻元件模組’ 其中 前述高頻元件係單晶微波積體電路元件。 10. —種高頻元件模組，其特徵爲具有： 絕緣基板，具有孔部，於表面配設著電極； 接地基板，在該絕緣基板之背面至少覆蓋著前述孔部 » 高頻元件，配設於前述孔部內，其端子連結於前述電 極； 表面保護材，以保護該高頻元件之表面爲目的而塗佈 注封材，用以密封塗佈著該表面保護材之前述高頻元 件； 金屬層，配設於該注封材之上，連結於前述接地基板 » 絕緣層，以覆蓋該金屬層之方式配設； 配線圖案，配設於該絕緣層之上，連結於前述電極； 以及 保護層，配設於該配線圖案之上。 1 1.如申請專利範圍第1 0項所記載之高頻元件模組， 其中 -14- (4) (4)1336510 前述表面保護材係.聚醯亞胺。 1 2 ·如申請專利範圍第1 1項所記載之高頻元件模組， 其中 前述金屬層係鋁之薄膜。 1 3 ·如申請專利範圍第1 2項項所記載之高頻元件模組 ，其中 前述高頻元件係單晶微波積體電路元件。 14· 一種高頻元件模組之製造方法，其特徵爲： 於表面配設著電極且於背面配設著接地基板之絕緣基 板之上，配設其端子連結於前述電極之高頻元件， 利用注封材覆蓋該高頻元件， 於該注封材之上，配設金屬層， 將該金屬層連結至前述接地基板。 15. —種高頻元件模組之製造方法，其特徵爲： 於表面配設著電極且於背面配設著接地基板之絕緣基 板之上，配設其端子連結於前述電極之高頻元件， 於該高頻元件塗佈以保護其表面爲目的之表面保護材 j 利用注封材密封塗佈著該表面保護材之前述高頻元件 > 於該注封材之上，配設連結於前述接地基板之金屬層 ， 以覆蓋該金屬層之方式配設絕緣層， 於該絕緣層之上，配設連結於前述電極之配線圖案， -15- (5) (5)1336510
於該配線圖案之上.，配設保護層。 1 6 .如申請專利範圍第1 5項所記載之高頻元件模組之 製造方法，其中 前述表面保護材係聚醯亞胺。 -16-
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Families Citing this family (13)

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Publication number Priority date Publication date Assignee Title
US8186048B2 (en) 2007-06-27 2012-05-29 Rf Micro Devices, Inc. Conformal shielding process using process gases
US8959762B2 (en) 2005-08-08 2015-02-24 Rf Micro Devices, Inc. Method of manufacturing an electronic module
US8053872B1 (en) 2007-06-25 2011-11-08 Rf Micro Devices, Inc. Integrated shield for a no-lead semiconductor device package
US8062930B1 (en) 2005-08-08 2011-11-22 Rf Micro Devices, Inc. Sub-module conformal electromagnetic interference shield
US7956429B1 (en) 2007-08-02 2011-06-07 Rf Micro Devices, Inc. Insulator layer based MEMS devices
US9137934B2 (en) 2010-08-18 2015-09-15 Rf Micro Devices, Inc. Compartmentalized shielding of selected components
US8835226B2 (en) 2011-02-25 2014-09-16 Rf Micro Devices, Inc. Connection using conductive vias
US9627230B2 (en) 2011-02-28 2017-04-18 Qorvo Us, Inc. Methods of forming a microshield on standard QFN package
US9807890B2 (en) 2013-05-31 2017-10-31 Qorvo Us, Inc. Electronic modules having grounded electromagnetic shields
US11127689B2 (en) 2018-06-01 2021-09-21 Qorvo Us, Inc. Segmented shielding using wirebonds
US11219144B2 (en) 2018-06-28 2022-01-04 Qorvo Us, Inc. Electromagnetic shields for sub-modules
US11114363B2 (en) 2018-12-20 2021-09-07 Qorvo Us, Inc. Electronic package arrangements and related methods
US11515282B2 (en) 2019-05-21 2022-11-29 Qorvo Us, Inc. Electromagnetic shields with bonding wires for sub-modules

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2524202B1 (fr) * 1982-03-23 1985-11-08 Thomson Csf Module preadapte pour diode hyperfrequence, et procede de realisation de la connexion de polarisation de la diode
JP2987950B2 (ja) * 1991-01-25 1999-12-06 日立化成工業株式会社 ポリイミド系樹脂ペーストおよびこれを用いたｉｃ
JP2001035956A (ja) * 1999-07-19 2001-02-09 Sanyo Electric Co Ltd 半導体装置
JP3500335B2 (ja) * 1999-09-17 2004-02-23 株式会社東芝 高周波回路装置
JP2001345419A (ja) 2000-05-31 2001-12-14 Hitachi Ltd 一体型高周波無線回路モジュール
JP2003179181A (ja) * 2001-12-11 2003-06-27 Ngk Spark Plug Co Ltd 樹脂製配線基板
JP2003298004A (ja) 2002-04-04 2003-10-17 Fujitsu Ltd 素子間干渉電波シールド型高周波モジュール及び電子装置
JP2005109306A (ja) * 2003-10-01 2005-04-21 Matsushita Electric Ind Co Ltd 電子部品パッケージおよびその製造方法
JP2005340656A (ja) * 2004-05-28 2005-12-08 Matsushita Electric Ind Co Ltd 高周波集積回路装置及びその製造方法

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