CN101345199B - 一种封装结构及其形成方法 - Google Patents

一种封装结构及其形成方法 Download PDF

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Publication number
CN101345199B
CN101345199B CN2007103018933A CN200710301893A CN101345199B CN 101345199 B CN101345199 B CN 101345199B CN 2007103018933 A CN2007103018933 A CN 2007103018933A CN 200710301893 A CN200710301893 A CN 200710301893A CN 101345199 B CN101345199 B CN 101345199B
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package substrate
semiconductor die
projection
structure according
pad
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CN101345199A (zh
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李新辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及一种形成封装结构的方法和一种集成电路封装结构。该方法至少包含提供一半导体裸片、提供一封装衬底、形成凸块于封装衬底上、以及将半导体裸片接合到封装衬底上，其中凸块电性连接半导体裸片及封装衬底。

Description

一种封装结构及其形成方法
技术领域
本发明涉及一种集成电路封装工艺，且特别涉及一种利用凸块对半导体裸片进行倒装芯片封装的集成电路封装结构及其形成方法。
背景技术
现代集成电路由无数个有源器件，例如晶体管(transistors)，以及电容器(capacitors)组成。这些器件一开始是各自分离的，但后来会互连在一起形成功能电路。典型的互连结构包含横向互连，如金属线，以及垂直互连，如通孔(vias)及触点(contacts)。现代集成电路性能及密度的限制，越来越多地由互连决定。
互连结构的顶端会形成焊盘(bond pads)，并暴露于对应的芯片表面。通过焊盘将芯片电性连接到封装衬底，焊盘可用于引线接合(wire bonding)或倒装芯片接合。
图1至图2B说明传统的倒装芯片封装法。参照图1，裸片(die)10的表面包含焊盘12，其中焊盘12和裸片10中的集成电路相连接。通过一引线接合器(图中未示)的接合头(bond head)15，可在焊盘12上形成凸块(stud bumps)14。当裸片10上的每一接合完成后，引线接合器会施加一个力以剪断对应的接合线，使凸块14附着到焊盘12上。
参照图2A，裸片10倒装接合到封装衬底16。典型地，接合工艺包含将凸块14置于封装衬底16的焊盘18上，使焊锡球(solder balls)20位于凸块14和对应的焊盘18之间。接着执行再流(reflow)以熔化焊锡球20，使凸块14能电性连接到焊盘18。
图2B是另一倒装芯片接合图，其中裸片10通过各向异性导电膜(Anisotropic Conducting Film，ACF)22，倒装接合到封装衬底16。各向异性导电膜22可将凸块14电性连接到与其对应的焊盘18，而不用提供横向的电路(lateral electrical paths)来短接邻近的凸块14及焊盘18。
使用凸块封装半导体裸片具有降低封装成本的优势特征。然而，传统制造凸块的方法有其缺点。参照图1，欲切断凸块14各自的接合线时，需施加一个力，焊盘12可能会因此与裸片10分层。裸片10要形成互连结构通常需包含低k值的介电材料，而低k值的介电材料极可能会有分层的现象产生。随着集成电路制造技术的发展，所使用的介电材料的k值也越来越低，并因而增加了分层的可能性，因此需要该问题的解决办法。
发明内容
本发明所要解决的技术问题在于提供一种形成封装结构的方法，用以对半导体裸片进行倒装芯片封装。
本发明的另一目的是提供一种集成电路封装结构，该封装结构通过在封装衬底形成凸块，避免对半导体裸片造成损坏。
为了实现上述目的，本发明提供一种形成封装结构的方法，包含提供一半导体裸片、提供一封装衬底、以及形成电性连接于半导体裸片和封装衬底之间的凸块。每一个凸块都具有靠近半导体裸片的第一部分，以及靠近封装衬底的第二部分，其中第一部分的宽度小于第二部分的宽度。
为了实现上述目的，本发明还提供一种形成封装结构的方法，包含提供一半导体裸片、提供一封装衬底、以及形成位于封装衬底的凸块。并将半导体裸片接合到封装衬底，其中凸块电性连接半导体裸片及封装衬底。
为了实现上述目的，本发明又提供一种集成电路封装结构，包含一半导体裸片、一封装衬底、以及电性连接于半导体裸片和封装衬底之间的凸块。每一个凸块都具有靠近半导体裸片的第一部分，以及靠近封装衬底的第二部分，其中第一部分的宽度小于第二部分的宽度。
为了实现上述目的，本发明又提供一种集成电路封装结构，包含具有顶部表面及位于顶部表面的焊盘的一半导体裸片、一封装衬底、以及电性连接于半导体裸片和封装衬底之间的凸块。凸块以物理方式连接到封装衬底，其中至少一个凸块与其对应的焊盘以物理方式隔离开来。
因此，本发明通过先在封装衬底形成凸块，可以消除对半导体裸片造成损坏。
为使本发明和其优点能更明显易懂，下面结合附图进行描述。
附图说明
图1至图2B说明利用凸块形成集成电路封装结构的传统方法；
图3A至图7是制造本发明的凸块倒装芯片封装结构的一较佳实施例的中间步骤的剖面图；以及
图8A及图8B示出根据本发明的另一实施例，其中裸片接合到引线框架上。
【主要器件符号说明】
10：裸片              40：凸块
12：焊盘              401：基部
14：凸块              402：顶部
15：接合头            42：导电指状条
16：封装衬底          50：裸片
18：焊盘              52：焊盘
20：焊锡球            56：各向异性导电膜
22：各向异性导电膜    58：导电粒子
30：封装衬底          60：非导电基质
32：焊盘              62：焊锡球
34：重布线路          64：模材料
36：焊盘
具体实施方式
以下详细描述本发明较佳实施例的制造与使用。然而应可理解的是，本发明提供诸多可应用的发明概念，其能具体化于各种特定内容中。所描述的特定实施例仅以特定形式说明制造及使用本发明，并非用以限制本发明的范围。
本发明提供一种新颖的封装结构和形成该封装结构的方法。以下说明一种制造本发明的实施例的中间步骤。在本发明的不同附图和说明性实施例中，相似的元件使用相同的参考编号。
参照图3A，其中示出根据本发明一实施例的一种封装衬底30。在一实施例中，封装衬底30可以是双马来酰亚胺三嗪(Bismaleimide Triazine，BT)衬底、印刷电路板(Print Circuit Board，PCB)衬底、或其它可封装裸片的常用衬底。封装衬底30包含位于顶部表面的焊盘32。焊盘32进一步连接到重布线路(redistribution traces)34而到达底部表面，并和焊盘36相连接。重布线路34也连接封装衬底30顶部表面的焊盘。
以使用引线接合器为例，引线接合器会在焊盘32上面形成凸块40。凸块40和引线接合形成的方式相似，不同之处在于引线接合器会使接合线断裂，以让凸块40留在焊盘32上面。在一较佳实施例中，凸块40由具有良好导电及接合性质的金构成，凸块40也可以利用其它金属如铜构成。通过这种凸块形成方法，每一个凸块40包含一基部401(第二部分)及一顶部402(第一部分)，基部401宽度W1远大于顶部402宽度W2。
参照图3B的另一实施例，封装衬底30为具有多个导电指状条(conductivefingers)42的引线框架(lead frame)，利用类似于前述段落所述的方法，在导电指状条42上面形成凸块40。
参照图4，其中示出一种半导体裸片50。如本领域公知的技术，半导体裸片形成在半导体晶片(wafer)中，每一个晶片具有多个相同的裸片。当一半导体晶片形成后，该晶片会进行晶片研磨(wafer-grinding)以减少其厚度，并进行晶片测试和晶片切割(sawing)。因此裸片50是优质裸片(Kown-good-die)，包含位于顶部表面的焊盘52，其中焊盘52和裸片50内部的集成电路相连接。
参照图5，其中示出裸片50与封装衬底30的接合图。焊盘52与凸块40利用各向异性导电膜56电性连接较佳。各向异性导电膜56包含许多导电粒子(conductive particles)58，导电粒子58彼此之间会被环氧树脂(epoxies)所组成的非导电基质(non-conductive base material)60所隔离开来。在本发明的一个实施例中，各向异性导电膜56会形成在裸片50上。然后通过施加一压力压缩裸片50及封装衬底30，并加热，于是裸片50上的焊盘52通过导电粒子58和凸块40电性连接。各向异性导电膜56有利于使相邻的凸块40及相邻的焊盘32彼此绝缘。
图6与图7示出根据本发明的另一实施例。参照图6，裸片50置于封装衬底30对面，凸块40与焊盘52之间具有焊锡球62。焊锡球62可随着焊剂(Flux)(图中未示)先置于裸片50的焊盘32或凸块40上，接着执行再流而形成如图7所示的结构。经过再流的焊锡球62电性连接焊盘52及凸块40，并应用模材料(molding compound)64以保护该封装结构。
图8A与图8B示出根据本发明的又一实施例，其中裸片50和引线框架相接合。参照图8A，裸片50通过一各向异性导电膜56电性连接凸块40。参照图8B，裸片50通过焊锡(如焊锡球)62电性连接凸块40。
在上述实施例中，封装衬底30与半导体晶片的大小可能类似。在这种情况下，封装衬底30会包含许多子区域，每一个子区域用以接合裸片。不管是整个晶片或是多个彼此隔离的个别裸片，都可接合在封装衬底30上。
本发明的实施例具有以下优点。由于凸块40形成于封装衬底30而非裸片50上，因此在形成凸块的过程中，可避免所施加的力对于裸片50造成的损坏。另一方面，由于封装衬底30不具有低k值的介电材料，因此在凸块形成过程中不容易被损坏。同时，即使是具有k值极低的介电层的裸片，也可以使用本发明的凸块技术。此外，封装裸片的产量也有所提高。因为在传统封装技术中，形成凸块于裸片上的步骤需在裸片和衬底接合之前。然而，在本发明的实施例中，凸块可先形成于衬底上，因此可降低装配工艺的循环时间。
虽然本发明及其优点已详细描述，但在不脱离本发明后附的权利要求书的精神和范围的情况下，可以作出各种改变、替代与改进。此外，本发明的应用范围并不局限于上述说明书中的特定实施例的工艺、机器、制造、要素组成、工具、方法及步骤。从本发明的公开范围中，本领域内的任何普通技术人员容易理解，与在此描述的相应的实施例执行大体上相同功能或达到大体上相同的结果的、已存在或以后将被开发的工艺、机械、制造、要素组成、工具、方法或步骤可以根据本发明加以利用。因此，所附权利要求书旨在包含该工艺、机械、制造、要素组成、工具、方法或步骤的范围。

Claims (15)

1.一种形成封装结构的方法，其特征在于，至少包含：
提供一半导体裸片；
提供一封装衬底；以及
形成多个凸块电性连接于该半导体裸片和该封装衬底之间，其中每一个该凸块都具有靠近该半导体裸片的第一部分，以及靠近该封装衬底的第二部分，其中该第一部分的宽度小于该第二部分的宽度。
2.根据权利要求1所述的形成封装结构的方法，其特征在于，所述形成这些凸块于所述半导体裸片和所述封装衬底之间的步骤包含：
形成所述凸块于所述封装衬底上；以及
在形成所述凸块于所述封装衬底的步骤后，将所述半导体裸片固定在所述封装衬底上。
3.根据权利要求2所述的形成封装结构的方法，其特征在于，所述凸块通过一各向异性导电膜电性连接所述半导体裸片。
4.根据权利要求2所述的形成封装结构的方法，其特征在于，所述半导体裸片通过多个焊锡电性连接到所述凸块。
5.根据权利要求1所述的形成封装结构的方法，其特征在于，所述半导体裸片位于一半导体晶片内，且该方法包含：在形成所述凸块电性连接于所述半导体裸片和所述封装衬底之间的步骤后，将所述半导体裸片从该半导体晶片上切割下来。
6.根据权利要求1所述的形成封装结构的方法，其特征在于，还包含：在形成所述凸块电性连接于所述半导体裸片和所述封装衬底之间的步骤前，将该半导体裸片从一半导体晶片上切割下来。
7.一种集成电路封装结构，其特征在于，该结构至少包含：
一半导体裸片；
一封装衬底；以及
多个凸块电性连接于该半导体裸片和该封装衬底之间，其中每一个该凸块都具有靠近该半导体裸片的第一部分，以及靠近该封装衬底的第二部分，其中该第一部分的宽度小于该第二部分的宽度。
8.根据权利要求7所述的集成电路封装结构，其特征在于，所述半导体裸片具有多个焊盘位于顶部表面，且所述集成电路封装结构包含多个焊锡位于所述凸块和所述焊盘之间。
9.根据权利要求7所述的集成电路封装结构，其特征在于，还包含一各向异性导电膜位于所述半导体裸片和所述封装衬底之间，其中该半导体裸片具有多个焊盘位于顶部表面，且所述凸块通过该各向异性导电膜内的多个导电粒子电性连接所述焊盘。
10.根据权利要求7所述的集成电路封装结构，其特征在于，所述封装衬底包含印刷电路板衬底。
11.根据权利要求10所述的集成电路封装结构，其特征在于，该印刷电路板衬底是玻璃衬底或双马来酰亚胺三嗪衬底。
12.根据权利要求7所述的集成电路封装结构，其特征在于，所述封装衬底为一引线框架，所述凸块形成于该引线框架的多个指状条上。
13.一种集成电路封装结构，其特征在于，所述结构至少包含：
一半导体裸片，其具有一顶部表面及多个位于该顶部表面的焊盘；
一封装衬底；以及
多个凸块电性连接所述半导体裸片的所述焊盘及所述封装衬底，且该多个凸块每一个皆具有靠近该半导体裸片的一第一部分，以及靠近该封装衬底的一第二部分，其中该第一部分的宽度小于该第二部分的宽度，其中所述凸块和所述封装衬底相连接，且该多个凸块中至少一个该凸块和其对应的该焊盘彼此间隔一段距离。
14.根据权利要求13所述的集成电路封装结构，其特征在于，还包含一焊接材料位于所述焊盘及所述凸块之间。
15.根据权利要求13所述的集成电路封装结构，其特征在于，还包含一各向异性导电膜，其中该各向异性导电膜内的多个导电粒子连接所述焊盘及所述凸块。
CN2007103018933A 2007-07-11 2007-12-20 一种封装结构及其形成方法 Active CN101345199B (zh)

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