CN101330064A - 半导体封装及其制造方法 - Google Patents
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Abstract
本发明涉及一种半导体封装及其制造方法,能够轻松地供应电能而不增加用于电能供应的垫片的数量。半导体封装可包括:具有安置在中心部分包括用于电能供应的垫片的多个垫片以及安置成暴露在外面的内部引线的半导体芯片;形成在半导体芯片上的绝缘膜从而暴露用于电能供应的垫片和内部引线;和形成在绝缘膜上的再分配线从而在用于电能供应的垫片的暴露的部分和内部引线之间相连接。
Description
技术领域
本发明涉及一种半导体封装,和特别地涉及一种半导体封装及其制造方法,其能够轻松地供应电能而不增加电能供应所需要的垫片的数量。
背景技术
最新的半导体器件,例如动态随机存取存储器(DRAM)已经制造成具有高密度和高速度。更高速度和性能的芯片需要低电压的运行特性从而减小所用电能的量和源于所用电能的量所产生的热量。
然而,为了满足这些特性,需要更大量的垫片用于电能供应。在芯片内增加垫片的数量的能力是有限的且这使得整个芯片的尺寸更大,导致提高了产品成本。
更高速度和性能的最新的半导体芯片需要更大量的垫片用于电能供应,且这些垫片必须只能形成于在装配工艺中能够引线键合的特定的位置上。然而,为了在特定位置容纳更大量的垫片,芯片的尺寸必然会增长。这造成产品成本的增加。
此外,在典型的DRAM器件中,采用具有窗口的基板,垫片布置在中心部分以制造成为芯片上板(board on chip,BOC)型的封装。由于电能经由连接到在中心部分的垫片的金属线供应到芯片的边缘部分,所以很难供应足够的电能。
另外,由于采用精密工艺制造半导体芯片,对于垫片的尺寸、数量和节距的方案受到很大的限制。由于工艺的限制,对于用于封装半导体芯片的引线框架或基板的节距是很大的。因此,虽然在半导体芯片上形成了足够数量的垫片以供应电能,但是由于垫片的节距和引线框架的节距之间的差异不可能经由引线连接所有的垫片。
此外,由于为了准备附加的电能或信号引线,整个半导体芯片必须重新设计或附加的金属引线必须经由Fab工艺形成,牵涉了许多时间和成本。
发明内容
本发明的实施例涉及一种半导体封装,其在不增加芯片尺寸的情况下能够达到低电压特性。
进而,本发明的实施例涉及一种能够供应足够电能的半导体封装。
此外,本发明的实施例提供一种尽管保证了低电压特性也能够缩减生产时间和成本的半导体封装。
依照本发明的一个实施例,半导体封装可包括:具有安置在中心部分包括用于电能供应的垫片的多个垫片以及安置成暴露在外面的内部引线的半导体芯片;形成在半导体芯片上的绝缘膜从而暴露用于电能供应的垫片和内部引线;和形成在绝缘膜上的再分配线从而在用于电能供应的垫片的暴露的部分和内部引线之间相连接。
用于电能供应的垫片的数量至少为二,和暴露的内部引线至少为一。
内部引线和再分配线全部互相连接,至少一条内部引线和再分配线分别暴露出来。
再分配线由金属膜组成,且金属膜形成有Au层或具有形成在其上的Au的Cu/Ni/Au、Cu/Au和Ni/Au中任一合金层。
半导体封装还包括形成在绝缘膜和再分配线上的覆盖膜从而暴露再分配线的一部分和电能供应键合垫片。
依照本发明的另一实施例,半导体封装的制造方法包括如下步骤:在半导体芯片上形成绝缘膜,该半导体芯片具有安置在中心部分的包括用于电能供应的垫片的多个垫片和安置成暴露在外面的内部引线;通过刻蚀绝缘膜暴露用于电能供应的垫片和一部分内部引线;和在绝缘膜上形成再分配线从而在用于电能供应的垫片和内部引线的暴露的部分之间相连接。
经由再分配线连接的用于电能供应的垫片和暴露的内部引线中每个的数量至少为一。
以一种方式形成再分配线从而在暴露的内部引线和再分配线之间相连接,该暴露的内部引线和再分配线的数量分别至少为一。
形成再分配线的步骤经由电解镀覆工艺而进行。
采用电解镀覆工艺形成再分配线的步骤包括如下步骤:在钝化膜上形成种子金属膜,包括用于供应电能的暴露的垫片和内部引线的暴露的部分;在种子金属膜上形成掩模图形从而选择性地暴露再分配线形成区域;在暴露的种子金属膜上镀覆金属膜;和除去掩模图形和掩模图形下面的一部分种子金属膜。
掩模图形形成光敏膜图形。
金属膜形成有Au或具有形成在其上的Au的Cu/Ni/Au、Cu/Au和Ni/Au中任一合金层。
半导体封装的制造方法还包括在包括再分配线的绝缘膜上形成覆盖膜从而暴露再分配线的一部分和电能供应键合垫片中的每一个的步骤。
半导体封装的制造方法还包括在形成覆盖膜之后背研磨半导体芯片的背表面的步骤。
半导体封装的制造方法在晶片级进行形成绝缘膜的步骤至背研磨半导体芯片的背表面的步骤。
半导体封装的制造方法还包括在晶片级背研磨半导体的背表面之后在芯片级划片的步骤。
附图说明
图1为说明与本发明的一个实施例一致的半导体封装的平面图。
图2A至2E为说明与本发明的一实施例一致的半导体封装的制造方法的工艺步骤的横截面图。
具体实施方式
依照本发明的优选的实施例,暴露了形成在半导体芯片上的一部分内部引线,在晶片级用来互相连接暴露的内部引线和用于电能供应的垫片的再分配线通过再分配线工艺形成,且此后可进行熟知的封装工艺。
由于电能能经由再分配线直接供应到内部引线,所以不必增加垫片的数量用于电能供应。因此,依照本发明的半导体芯片能够为高速度和高性能且具有低电压特性,而没有为了电能供应增加垫片的数量引起增加芯片的尺寸。
此外,由于本发明允许电能经由再分配线供应到边缘部分中的内部引线,和不供应到金属线,所以供应足够的电能变为可能。
另外,与用于键合引线的键合垫片形成时不同,由于本发明不需要限制内部引线暴露的部分的尺寸,所以能够轻松的供应电能。
此外,由于不需要重新设计整个半导体芯片或为了供应电能经由Fab工艺形成分离的金属引线,利用本发明可防止生产时间和成本的增加。
图1为说明与本发明的一实施例一致的半导体封装的平面图。参考图1将具体描述半导体封装。
如图1所示,半导体芯片包括100包括多个键合垫片102和引线104,该键合垫片102包括用于电能供应的垫片102a。包括用于电能供应的垫片102a的多个键合垫片102在半导体芯片100的中心部分布置成一行或两行。用于电能供应的垫片102a的数量至少为二。在芯片生产工艺中,形成引线104以布置在例如半导体芯片100内的边缘部分,且引线的数量至少为一。
半导体芯片100具有形成在其表面上的钝化膜106,以及形成钝化膜以暴露包括用于电能供应的垫片102a的键合垫片102和内部引线104。
绝缘膜110形成在半导体芯片100的钝化膜106上,以露出包括用于电能供应的垫片102a的多个键合垫片102和内部引线104的一部分。
此外,再分配线120形成在绝缘膜110上,从而相互连接内部引线104的暴露的部分和用于电能供应的垫片102a。再分配线120通过电解镀覆工艺形成,并且负责传输经由用于电能供应的垫片102a提供的电能到内部引线104。形成该再分配线120从而在分别数量至少为一的内部引线104和用于电能供应的垫片102a之间相连接。再分配线由金属膜组成,例如Au膜或具有安置在其上的Au的Cu/Ni/Au、Cu/Au和Ni/Au中任一合金膜。
虽然没有示出,覆盖膜形成在其上形成了再分配线120的绝缘膜110上以保护再分配线120。形成覆盖膜以暴露包括用于电能供应的垫片102a的键合垫片102和一部分再分配线120。
此外,如上所述的半导体芯片100贴装在例如具有包括电极终端和球焊盘的电路图形的基板上,基板的电极终端和包括用于电能供应的垫片102a的键合垫片102经由金属线键合,包括金属线的半导体芯片100的上表面用压模材料密封,且焊料球贴装到在基板的底表面上的球焊盘上从而作为外部连接终端,由此形成半导体封装。
依照本发明的一实施例的半导体封装,通过经由再分配线连接用于电能供应的垫片和内部引线,能够允许电能更轻松的供应到半导体芯片而不增加用于电能供应的垫片的数量,由此制造具有低电压特性的半导体芯片。
在下文中,参考图2A至2E将描述上面提到的依照本发明的一实施例的半导体封装的制造方法。
参考图2A,提供了半导体芯片100,其具有安置在其中心部分中的包括用于电能供应的垫片102a的多个键合垫片和安置在内部边缘的内部引线104,和具有形成在其表面上的钝化膜106从而暴露电能供应键合垫片102a。通过刻蚀半导体芯片100表面上的钝化膜106暴露内部引线104。
参考图2B,在半导体芯片100的钝化膜106上形成绝缘膜110之后,包括用于电能供应的垫片102a的多个键合垫片以及内部引线104通过刻蚀绝缘膜110而允许暴露出来。
参考图2C,种子金属膜122形成在半导体芯片100的钝化膜106上以用于电镀覆盖,包括暴露的电能供应键合垫片102a和内部引线104。此后,掩模图形124形成在种子金属膜122上从而只选择性的暴露再分配线形成区域。掩模图形124优选地为经由光刻工艺形成的光敏膜图形。
参考图2D,经由电解镀覆工艺,金属膜126镀覆在种子金属膜122的暴露的部分。金属膜126形成有Au的单一膜或具有形成在最上层上的Au的Cu/Ni/Au、Cu/Au和Ni/Au中任一合金膜。
参考图2E,通过除去掩模图形和在掩模图形之下的一部分种子金属122形成再分配线120,以相互连接所有用于电能供应的垫片102和内部引线104。此后,形成覆盖膜(未显示)以暴露用于电能供应的垫片102a和在绝缘膜110上的一部分再分配线120。
随后,虽然未示出,通过背研磨形成有覆盖膜130的半导体芯片100的背表面减小了半导体芯片100的厚度。接着,半导体芯片将贴装到基板上。基板的电极终端和包括用于电能供应的垫片102a的多个键合垫片102经由金属线彼此连接。然后,包括金属线的半导体芯片100的上表面填充有压模材料,且焊料球贴装到基板的底表面从而作为外部连接终端,由此完成制造半导体封装。
所有暴露内部引线的步骤、形成绝缘膜的步骤和背研磨(back-grinding)半导体芯片的背表面的步骤都在晶片级进行。然后在晶片级背研磨(back-grinding)半导体芯片的背表面之后在芯片级进行划片的步骤。
由于本发明在经由制造的半导体芯片的晶片级工艺形成再分配线从而在键合垫片和内部引线之间连接起来的状态下进行随后的封装工艺,所以可轻松的提供具有低电压特性的半导体封装。
此外,由于本发明能经由再分配线直接供应电能到内部引线,所以可防止芯片尺寸的增加。
而且,由于电能能直接供应到内部引线,所以本发明能供应足够的电能。
另外,整个半导体芯片不需要进行再设计或不需要为了供应电能的目的经由Fab工艺形成分离的金属线,由此防止用于半导体芯片的生产时间和成本的增加。
虽然已经描述了本发明的特定的实施例用于说明效果,然而本领域的一般技术人员可以理解在不脱离由权利要求所界定的本发明的精神和范围的情况下,可以作出各种修改、添加和替换。
本申请要求于2007年6月20日提交的韩国专利申请号10-2007-0060261的优选权,其在此全文引用作为参考。
Claims (17)
1.一种半导体封装,包括:
半导体芯片,具有安置在中心部分包括用于电能供应的垫片的多个垫片以及暴露在该半导体芯片外面的内部引线;
形成在该半导体芯片上的绝缘膜,从而暴露所述用于电能供应的垫片和该内部引线;和
形成在该绝缘膜上的再分配线,从而在所述用于电能供应的垫片的暴露的部分和暴露的内部引线之间相连接。
2.如权利要求1的半导体封装,其中用于电能供应的垫片的数量至少为二,和该暴露的内部引线至少为一。
3.如权利要求2的半导体封装,其中该暴露的内部引线和再分配线全部互相连接,至少一条该内部引线和再分配线分别暴露出来。
4.如权利要求1的半导体封装,其中该再分配线由金属膜组成。
5.如权利要求4的半导体封装,其中该金属膜形成有Au膜或具有形成在其上的Au的Cu/Ni/Au、Cu/Au和Ni/Au中任一合金膜。
6.如权利要求1的半导体封装,还包括形成在该绝缘膜上的覆盖膜从而暴露一部分该再分配线和暴露电能供应键合垫片。
7.一种半导体封装的制造方法,包括如下步骤:
在半导体芯片上形成绝缘膜,该半导体芯片具有安置在中心部分的包括用于电能供应的垫片的多个垫片和暴露在该半导体芯片外面的内部引线;
通过刻蚀该绝缘膜暴露所述用于电能供应的垫片和一部分该内部引线;和
在该绝缘膜上形成再分配线从而在暴露的用于电能供应的垫片和该内部引线的暴露的部分之间相连接。
8.如权利要求7的半导体封装的制造方法,其中经由该再分配线连接的所述用于电能供应的垫片和暴露的内部引线中每个的数量至少为一。
9.如权利要求8的半导体封装的制造方法,其中以一种方式形成该再分配线,从而在暴露的内部引线和所述再分配线之间相连接,该暴露的内部引线和再分配线的数量分别至少为一。
10.如权利要求7的半导体封装的制造方法,其中形成该再分配线的步骤经由电解镀覆工艺而进行。
11.如权利要求10的半导体封装的制造方法,其中采用该电解镀覆工艺形成该再分配线的步骤包括如下步骤:
在贴装到半导体芯片的钝化膜上形成种子金属膜,包括在暴露的用于供应电能的垫片和该内部引线的暴露的部分上;
在该种子金属膜上形成掩模图形从而暴露再分配线形成区域;
在该种子金属膜的暴露的部分上镀覆该金属膜;和
除去该掩模图形和该掩模图形下面的一部分该种子金属膜。
12.如权利要求11的半导体封装的制造方法,其中该掩模图形形成光敏膜图形。
13.如权利要求11的半导体封装的制造方法,其中该金属膜形成有Au或具有形成在其上的Au的Cu/Ni/Au、Cu/Au和Ni/Au的任一种合金膜。
14.如权利要求7的半导体封装的制造方法,还包括在该绝缘膜上形成覆盖膜从而暴露该再分配线的一部分和电能供应键合垫片中每一个的步骤。
15.如权利要求14的半导体封装的制造方法,还包括在形成该覆盖膜之后背研磨该半导体芯片的背表面的步骤。
16.如权利要求15的半导体封装的制造方法,其中形成该绝缘膜的步骤至背研磨该半导体芯片的该背表面的步骤是在晶片级进行的。
17.如权利要求16的半导体封装的制造方法,还包括在晶片级背研磨该半导体的该背表面之后在芯片级划片的步骤。
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KR1020070060261A KR100826989B1 (ko) | 2007-06-20 | 2007-06-20 | 반도체 패키지 및 그의 제조방법 |
KR60261/07 | 2007-06-20 |
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JP (1) | JP2009004721A (zh) |
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US7898092B2 (en) | 2007-11-21 | 2011-03-01 | Alpha & Omega Semiconductor, | Stacked-die package for battery power management |
JP4776975B2 (ja) * | 2005-05-11 | 2011-09-21 | キヤノン株式会社 | 撮像装置 |
KR101065165B1 (ko) * | 2008-09-11 | 2011-09-19 | 알파 앤드 오메가 세미컨덕터, 인코포레이티드 | 반도체 장치 패키지의 본드 와이어 재 루트를 위한 디스크리트 도전층을 사용한 반도체 장치 |
US9257375B2 (en) | 2009-07-31 | 2016-02-09 | Alpha and Omega Semiconductor Inc. | Multi-die semiconductor package |
US8164199B2 (en) | 2009-07-31 | 2012-04-24 | Alpha and Omega Semiconductor Incorporation | Multi-die package |
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- 2007-07-13 US US11/777,407 patent/US7595268B2/en not_active Expired - Fee Related
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