CN101317273B - 电阻减小的finfet及其制造方法 - Google Patents

电阻减小的finfet及其制造方法 Download PDF

Info

Publication number
CN101317273B
CN101317273B CN2006800440556A CN200680044055A CN101317273B CN 101317273 B CN101317273 B CN 101317273B CN 2006800440556 A CN2006800440556 A CN 2006800440556A CN 200680044055 A CN200680044055 A CN 200680044055A CN 101317273 B CN101317273 B CN 101317273B
Authority
CN
China
Prior art keywords
source
substrate
silicon
drain diffusion
finfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2006800440556A
Other languages
English (en)
Chinese (zh)
Other versions
CN101317273A (zh
Inventor
J·A·曼德尔曼
程慷果
路易斯·L-C·许
杨海宁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN101317273A publication Critical patent/CN101317273A/zh
Application granted granted Critical
Publication of CN101317273B publication Critical patent/CN101317273B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/62Fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/62Fin field-effect transistors [FinFET]
    • H10D30/6219Fin field-effect transistors [FinFET] characterised by the source or drain electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6704Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/015Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135Manufacturing their gate conductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/96Porous semiconductor

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
CN2006800440556A 2005-12-22 2006-12-05 电阻减小的finfet及其制造方法 Active CN101317273B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/316,244 2005-12-22
US11/316,244 US7531423B2 (en) 2005-12-22 2005-12-22 Reduced-resistance finFETs by sidewall silicidation and methods of manufacturing the same
PCT/EP2006/069339 WO2007071555A1 (en) 2005-12-22 2006-12-05 Reduced-resistance finfets and methods of manufacturing the same

Publications (2)

Publication Number Publication Date
CN101317273A CN101317273A (zh) 2008-12-03
CN101317273B true CN101317273B (zh) 2012-08-22

Family

ID=37771049

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2006800440556A Active CN101317273B (zh) 2005-12-22 2006-12-05 电阻减小的finfet及其制造方法

Country Status (8)

Country Link
US (2) US7531423B2 (enExample)
EP (1) EP1964179B1 (enExample)
JP (1) JP4550146B2 (enExample)
KR (1) KR100992037B1 (enExample)
CN (1) CN101317273B (enExample)
AT (1) ATE441938T1 (enExample)
DE (1) DE602006008984D1 (enExample)
WO (1) WO2007071555A1 (enExample)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7479437B2 (en) * 2006-04-28 2009-01-20 International Business Machines Corporation Method to reduce contact resistance on thin silicon-on-insulator device
KR100864928B1 (ko) * 2006-12-29 2008-10-22 동부일렉트로닉스 주식회사 모스펫 소자의 형성 방법
US20090001426A1 (en) * 2007-06-29 2009-01-01 Kangguo Cheng Integrated Fin-Local Interconnect Structure
US8004045B2 (en) 2007-07-27 2011-08-23 Panasonic Corporation Semiconductor device and method for producing the same
US8063437B2 (en) * 2007-07-27 2011-11-22 Panasonic Corporation Semiconductor device and method for producing the same
US8021939B2 (en) * 2007-12-12 2011-09-20 International Business Machines Corporation High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods
EP2311072B1 (en) 2008-07-06 2013-09-04 Imec Method for doping semiconductor structures
US20110001169A1 (en) * 2009-07-01 2011-01-06 International Business Machines Corporation Forming uniform silicide on 3d structures
US8653608B2 (en) * 2009-10-27 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design with reduced current crowding
US8278179B2 (en) 2010-03-09 2012-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. LDD epitaxy for FinFETs
US8431995B2 (en) * 2010-05-13 2013-04-30 International Business Machines Corporation Methodology for fabricating isotropically recessed drain regions of CMOS transistors
US8716798B2 (en) 2010-05-13 2014-05-06 International Business Machines Corporation Methodology for fabricating isotropically recessed source and drain regions of CMOS transistors
JP5837307B2 (ja) * 2011-02-07 2015-12-24 公益財団法人神奈川科学技術アカデミー 多孔性微粒子の製造方法
US8614134B2 (en) * 2011-03-21 2013-12-24 Globalfoundries Inc. Shallow source and drain architecture in an active region of a semiconductor device having a pronounced surface topography by tilted implantation
US10629900B2 (en) 2011-05-04 2020-04-21 Corning Incorporated Porous silicon compositions and devices and methods thereof
CN103137478A (zh) * 2011-11-21 2013-06-05 中芯国际集成电路制造(上海)有限公司 FinFET器件的制造方法及结构
US8637931B2 (en) 2011-12-27 2014-01-28 International Business Machines Corporation finFET with merged fins and vertical silicide
KR101894221B1 (ko) 2012-03-21 2018-10-04 삼성전자주식회사 전계 효과 트랜지스터 및 이를 포함하는 반도체 장치
US8664072B2 (en) 2012-05-30 2014-03-04 Globalfoundries Inc. Source and drain architecture in an active region of a P-channel transistor by tilted implantation
KR20140097569A (ko) * 2012-07-09 2014-08-06 도호쿠 다이가쿠 3차원 구조의 mosfet 및 그 제조 방법
US8975125B2 (en) * 2013-03-14 2015-03-10 International Business Machines Corporation Formation of bulk SiGe fin with dielectric isolation by anodization
US8859379B2 (en) 2013-03-15 2014-10-14 International Business Machines Corporation Stress enhanced finFET devices
US8940602B2 (en) 2013-04-11 2015-01-27 International Business Machines Corporation Self-aligned structure for bulk FinFET
KR102083493B1 (ko) 2013-08-02 2020-03-02 삼성전자 주식회사 반도체 소자의 제조방법
US9583590B2 (en) 2013-09-27 2017-02-28 Samsung Electronics Co., Ltd. Integrated circuit devices including FinFETs and methods of forming the same
US9711645B2 (en) * 2013-12-26 2017-07-18 International Business Machines Corporation Method and structure for multigate FinFET device epi-extension junction control by hydrogen treatment
US9391173B2 (en) * 2014-04-22 2016-07-12 International Business Machines Corporation FinFET device with vertical silicide on recessed source/drain epitaxy regions
CN105702729B (zh) * 2014-11-27 2019-01-15 中国科学院微电子研究所 半导体器件及其制造方法
CN105702725B (zh) * 2014-11-27 2018-12-11 中国科学院微电子研究所 半导体器件及其制造方法
US9741811B2 (en) 2014-12-15 2017-08-22 Samsung Electronics Co., Ltd. Integrated circuit devices including source/drain extension regions and methods of forming the same
US9666716B2 (en) 2014-12-15 2017-05-30 Sang U. Kim FinFET transistor
CN105789301B (zh) * 2014-12-25 2018-09-11 中国科学院微电子研究所 鳍式场效应晶体管、鳍结构及其制造方法
US9837277B2 (en) 2015-08-12 2017-12-05 International Business Machines Corporation Forming a contact for a tall fin transistor
US9397197B1 (en) 2015-09-23 2016-07-19 International Business Machines Corporation Forming wrap-around silicide contact on finFET
US9484251B1 (en) * 2015-10-30 2016-11-01 Lam Research Corporation Contact integration for reduced interface and series contact resistance
EP3380436B1 (en) 2015-11-25 2023-07-26 Corning Incorporated Porous silicon alloy compositions, methods for making them and devices thereof
CN107452792A (zh) * 2016-06-01 2017-12-08 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US9853127B1 (en) * 2016-06-22 2017-12-26 International Business Machines Corporation Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process
CN108155236B (zh) * 2016-12-05 2020-08-07 上海新昇半导体科技有限公司 具有黑磷沟道层的低接触电阻率FinFET及其制备方法
US10707331B2 (en) * 2017-04-28 2020-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device with a reduced width

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297135B1 (en) 1997-01-29 2001-10-02 Ultratech Stepper, Inc. Method for forming silicide regions on an integrated device
JP3209164B2 (ja) * 1997-10-07 2001-09-17 日本電気株式会社 半導体装置の製造方法
US6133124A (en) * 1999-02-05 2000-10-17 Advanced Micro Devices, Inc. Device improvement by source to drain resistance lowering through undersilicidation
US6255214B1 (en) * 1999-02-24 2001-07-03 Advanced Micro Devices, Inc. Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions
CA2455565C (en) * 2001-07-25 2007-11-06 Philmac Pty Ltd Coupling or transition fitting for the connection of metal or plastic pipes
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US6864519B2 (en) * 2002-11-26 2005-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS SRAM cell configured using multiple-gate transistors
US7105894B2 (en) * 2003-02-27 2006-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts to semiconductor fin devices
KR100559572B1 (ko) * 2003-09-01 2006-03-10 동부아남반도체 주식회사 살리사이드를 갖는 반도체 소자 제조 방법
US20050090067A1 (en) * 2003-10-27 2005-04-28 Dharmesh Jawarani Silicide formation for a semiconductor device
KR100526889B1 (ko) * 2004-02-10 2005-11-09 삼성전자주식회사 핀 트랜지스터 구조
KR20050108916A (ko) * 2004-05-14 2005-11-17 삼성전자주식회사 다마신 공정을 이용한 핀 전계 효과 트랜지스터의 형성 방법
JP3964885B2 (ja) * 2004-05-19 2007-08-22 株式会社東芝 半導体装置及びその製造方法
US7015126B2 (en) * 2004-06-03 2006-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming silicided gate structure
JP2006012898A (ja) * 2004-06-22 2006-01-12 Toshiba Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
KR20080086458A (ko) 2008-09-25
EP1964179A1 (en) 2008-09-03
EP1964179B1 (en) 2009-09-02
JP4550146B2 (ja) 2010-09-22
US20080054349A1 (en) 2008-03-06
US7531423B2 (en) 2009-05-12
US20070148836A1 (en) 2007-06-28
WO2007071555A1 (en) 2007-06-28
CN101317273A (zh) 2008-12-03
ATE441938T1 (de) 2009-09-15
KR100992037B1 (ko) 2010-11-05
JP2009521113A (ja) 2009-05-28
DE602006008984D1 (de) 2009-10-15

Similar Documents

Publication Publication Date Title
CN101317273B (zh) 电阻减小的finfet及其制造方法
US8685847B2 (en) Semiconductor device having localized extremely thin silicon on insulator channel region
US10134892B2 (en) High voltage device with low Rdson
US9184283B2 (en) High voltage device
US7381649B2 (en) Structure for a multiple-gate FET device and a method for its fabrication
US8822291B2 (en) High voltage device
US6509241B2 (en) Process for fabricating an MOS device having highly-localized halo regions
US10079279B2 (en) FET with local isolation layers on S/D trench sidewalls
US8159024B2 (en) High voltage (>100V) lateral trench power MOSFET with low specific-on-resistance
US20160197075A1 (en) Fin field effect transistors and fabrication method thereof
US20050116289A1 (en) Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
US20120061774A1 (en) Semiconductor device and manufacturing method of the same
US6888176B1 (en) Thyrister semiconductor device
US10043804B2 (en) LDMOS design for a FinFET device
US20070032029A1 (en) Lateral trench power MOSFET with reduced gate-to-drain capacitance
US20020086505A1 (en) Transistor structure having silicide soure/drain extensions
US20080169505A1 (en) Structure of Trench MOSFET and Method for Manufacturing the same
US20130224922A1 (en) UMOS Semiconductor Devices Formed by Low Temperature Processing
US7217976B2 (en) Low temperature process and structures for polycide power MOSFET with ultra-shallow source
US10403741B2 (en) Channel stop imp for FinFET device
US20160093731A1 (en) Method of Manufacturing a Semiconductor Device and Semiconductor Device
US6849546B1 (en) Method for improving interlevel dielectric gap filling over semiconductor structures having high aspect ratios
WO2012106833A1 (en) Semiconductor device and related fabrication methods
JP4374866B2 (ja) 半導体装置の製造方法
US20240113164A1 (en) Film modification for gate cut process

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant