CN101256934B - 半导体基板的制造方法 - Google Patents

半导体基板的制造方法 Download PDF

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Publication number
CN101256934B
CN101256934B CN2008100057324A CN200810005732A CN101256934B CN 101256934 B CN101256934 B CN 101256934B CN 2008100057324 A CN2008100057324 A CN 2008100057324A CN 200810005732 A CN200810005732 A CN 200810005732A CN 101256934 B CN101256934 B CN 101256934B
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CN
China
Prior art keywords
film
substrate
semiconductor substrate
manufacturing approach
sige
Prior art date
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Expired - Fee Related
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CN2008100057324A
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English (en)
Chinese (zh)
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CN101256934A (zh
Inventor
秋山昌次
久保田芳宏
伊藤厚雄
田中好一
川合信
飞坂优二
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Shin Etsu Chemical Co Ltd
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Shin Etsu Chemical Co Ltd
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Publication of CN101256934A publication Critical patent/CN101256934A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
CN2008100057324A 2007-02-08 2008-02-04 半导体基板的制造方法 Expired - Fee Related CN101256934B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007029484 2007-02-08
JP2007-029484 2007-02-08
JP2007029484A JP2008198656A (ja) 2007-02-08 2007-02-08 半導体基板の製造方法

Publications (2)

Publication Number Publication Date
CN101256934A CN101256934A (zh) 2008-09-03
CN101256934B true CN101256934B (zh) 2012-05-16

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Family Applications (1)

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CN2008100057324A Expired - Fee Related CN101256934B (zh) 2007-02-08 2008-02-04 半导体基板的制造方法

Country Status (4)

Country Link
US (1) US7855127B2 (fr)
EP (1) EP1956639A1 (fr)
JP (1) JP2008198656A (fr)
CN (1) CN101256934B (fr)

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US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
EP2062290B1 (fr) 2006-09-07 2019-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Réduction des défauts par piégeage basé sur le rapport de forme
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US8502263B2 (en) 2006-10-19 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Light-emitter-based devices with lattice-mismatched semiconductor structures
WO2008124154A2 (fr) 2007-04-09 2008-10-16 Amberwave Systems Corporation Photovoltaïque sur silicium
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
DE112008002387B4 (de) 2007-09-07 2022-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Struktur einer Mehrfachübergangs-Solarzelle, Verfahren zur Bildung einer photonischenVorrichtung, Photovoltaische Mehrfachübergangs-Zelle und Photovoltaische Mehrfachübergangs-Zellenvorrichtung,
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
JP5416212B2 (ja) 2008-09-19 2014-02-12 台湾積體電路製造股▲ふん▼有限公司 エピタキシャル層の成長によるデバイス形成
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
US8138066B2 (en) * 2008-10-01 2012-03-20 International Business Machines Corporation Dislocation engineering using a scanned laser
US8551862B2 (en) * 2009-01-15 2013-10-08 Shin-Etsu Chemical Co., Ltd. Method of manufacturing laminated wafer by high temperature laminating method
JP5067381B2 (ja) * 2009-02-19 2012-11-07 東京エレクトロン株式会社 熱処理装置の運転方法
EP2221853B1 (fr) * 2009-02-19 2012-04-25 S.O.I. TEC Silicon Relaxation et transfert de couches de matériaux sous contrainte
CN102379046B (zh) 2009-04-02 2015-06-17 台湾积体电路制造股份有限公司 从晶体材料的非极性平面形成的器件及其制作方法
SG169921A1 (en) * 2009-09-18 2011-04-29 Taiwan Semiconductor Mfg Improved fabrication and structures of crystalline material
JP5643509B2 (ja) 2009-12-28 2014-12-17 信越化学工業株式会社 応力を低減したｓｏｓ基板の製造方法
CN103177134A (zh) * 2011-12-22 2013-06-26 北京邮电大学 抑制异变外延生长中贯穿位错的结构与方法
CN103570001B (zh) * 2012-07-19 2016-09-07 中国科学院微电子研究所 一种绝缘体上二维薄膜材料的制备方法
US9583364B2 (en) 2012-12-31 2017-02-28 Sunedison Semiconductor Limited (Uen201334164H) Processes and apparatus for preparing heterostructures with reduced strain by radial compression
US9343303B2 (en) 2014-03-20 2016-05-17 Samsung Electronics Co., Ltd. Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices
GB2541146B (en) * 2014-05-23 2020-04-01 Massachusetts Inst Technology Method of manufacturing a germanium-on-insulator substrate
SG11201802818VA (en) * 2015-10-13 2018-05-30 Univ Nanyang Tech Method of manufacturing a germanium-on-insulator substrate
JP6759626B2 (ja) * 2016-02-25 2020-09-23 株式会社Sumco エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ
EP3486940A4 (fr) * 2016-07-15 2020-02-19 National University Corporation Tokyo University of Agriculture and Technology Procédé de fabrication de film stratifié semi-conducteur et film stratifié semi-conducteur
US12094930B2 (en) * 2021-04-15 2024-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure and method for forming the same

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WO2002015244A2 (fr) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Procede de production d'articles semiconducteurs par croissance epitaxiale graduelle
JP3648466B2 (ja) * 2001-06-29 2005-05-18 株式会社東芝 電界効果トランジスタ、半導体基板、電界効果トランジスタの製造方法及び半導体基板の製造方法
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EP1593145A2 (fr) * 2002-10-30 2005-11-09 Amberwave Systems Corporation Procedes de conservation de couches de substrats semi-conducteurs sous contrainte au cours d'un traitement cmos
JP2004349522A (ja) * 2003-05-23 2004-12-09 Toshiba Ceramics Co Ltd 半導体基板の製造方法
US7279369B2 (en) * 2003-08-21 2007-10-09 Intel Corporation Germanium on insulator fabrication via epitaxial germanium bonding
FR2867310B1 (fr) * 2004-03-05 2006-05-26 Soitec Silicon On Insulator Technique d'amelioration de la qualite d'une couche mince prelevee
WO2006012544A2 (fr) * 2004-07-22 2006-02-02 The Board Of Trustees Of The Leland Stanford Junior University Materiaux de type substrat de germanium et approche associee
US7235812B2 (en) * 2004-09-13 2007-06-26 International Business Machines Corporation Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques
JP4617820B2 (ja) * 2004-10-20 2011-01-26 信越半導体株式会社 半導体ウェーハの製造方法
US7247545B2 (en) * 2004-11-10 2007-07-24 Sharp Laboratories Of America, Inc. Fabrication of a low defect germanium film by direct wafer bonding

Non-Patent Citations (1)

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M.Halbwax,M.Rouviere,Y.Zheng,et al..UHV-CVD growth and annealing of thin fully relaxed Ge film on (001)Si.《Optical materials》.2004,第27卷 *

Also Published As

Publication number Publication date
EP1956639A1 (fr) 2008-08-13
US7855127B2 (en) 2010-12-21
US20080194078A1 (en) 2008-08-14
CN101256934A (zh) 2008-09-03
JP2008198656A (ja) 2008-08-28

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