CN101252121A - 堆叠封装及其制造方法 - Google Patents

堆叠封装及其制造方法 Download PDF

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Publication number
CN101252121A
CN101252121A CNA2007101691219A CN200710169121A CN101252121A CN 101252121 A CN101252121 A CN 101252121A CN A2007101691219 A CNA2007101691219 A CN A2007101691219A CN 200710169121 A CN200710169121 A CN 200710169121A CN 101252121 A CN101252121 A CN 101252121A
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China
Prior art keywords
semiconductor chip
stacked package
interconnect
inserter
terminals
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CNA2007101691219A
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English (en)
Inventor
郑显秀
张东铉
郑泰敬
金南锡
柳承官
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN101252121A publication Critical patent/CN101252121A/zh
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Abstract

提供了一种堆叠封装及其制造方法。堆叠封装包括在其中插入具有键合衬垫的半导体芯片的至少一个或多个插入器，由于半导体芯片与半导体芯片插入的空腔之间的面积差而形成的互连端子槽，以及在互连端子槽中形成与键合衬垫连接的互连端子。在堆叠封装中，插入器彼此堆叠，并且互连端子相互连接，以使得一个或多个半导体芯片彼此堆叠并电连接。

Description

堆叠封装及其制造方法
相关申请的交叉引用
本申请基于35USC§119，要求享有于2007年1月23日在韩国知识产权局提交的韩国专利申请No.10-2007-0007253的优先权，其全部内容在此引入作为参考。
技术领域
本发明涉及一种堆叠封装及其制作方法，并且尤其涉及到一种能够提高在彼此堆叠的半导体芯片之间的电连接特性、并提高封装产量的堆叠封装，以及该堆叠封装的制作方法。
背景技术
最近几年，消费者需求已经逐渐转向小、轻、高速和高容量的电子产品。为了满足对小型电子产品的需求，半导体芯片封装已变得越来越小和越来越轻。为了满足上述需求，研究方向已逐渐转移到封装技术，比如其中不再使用现有引线键合方法的倒装芯片，以使得半导体芯片不与晶片分离的状态来封装的晶片级封装，等等。
特别是，以如下结构开发了堆叠封装，在所述结构中，利用在半导体芯片中形成的贯通通孔来形成金属贯通电极，这些金属贯通电极随后彼此直接连接，使得半导体芯片彼此直接连接。在这样的情况下，由于没有使用键合引线，所以堆叠封装能够具有小的外形因数(form-factor)。另外，因为金属贯通电极的长度比键合引线的长度短，所以高性能、高速和低能耗的堆叠封装成为可能。
图1是显示传统堆叠封装的结构的截面图，图2是显示在切割成单个半导体芯片之前的晶片的平面视图。
参考图1和2，金属衬垫40和钝化层(未表示)首先被堆叠在半导体芯片90上，随后被图案化。接下来，在半导体芯片90上形成再分布图案35，该再分布图案35将金属衬垫40电连接到在与金属衬垫40分开的位置处的金属贯通电极30。
形成再分布图案35的方法如下：首先，在由划线80所定义的区域中设置金属贯通电极30的位置，该划线80是单独边界线或半导体芯片90的切割线，并且利用激光钻孔在金属贯通电极30的位置处形成贯通通孔95。籽晶金属层34被沉积在贯通通孔95中，并随后通过包括曝光和显影工艺的光刻工艺图案化成预定的形状以形成再分布图案35。即，再分布图案35通过光刻工艺来形成，并且除了再分布图案35之外的其他部分都被刻蚀工艺移除。
如果再分布图案35是通过在包括有贯通通孔95和金属衬垫40的预定区域中沉积籽晶金属层34、然后对籽晶金属层34进行图案化而形成的，则通过用电镀工艺在贯通通孔95中填充金属材料来形成金属贯通电极30。接下来，实施背叠(back lap)工艺，以降低半导体芯片90的厚度，并且随后使用焊球或凸块20将半导体芯片90的金属贯通电极30彼此连接起来，以便半导体芯片90能够彼此电连接。通过使用焊球或凸块20，将彼此电连接的半导体芯片90连接到基底10的各电极。
然而，根据该常规方法，由于金属贯通电极30的位置是通过划线80来定义的，所以对于金属衬垫40或金属贯通电极30的位置设置就只有有限的方案可供选用。而且，当沿着划线80来切割半导体芯片90时，在再分布图案35或金属贯通电极30的位置处可能产生裂缝。这会导致如下的几个问题：可能降低产量，在为了形成贯通通孔95而进行钻孔期间可能破坏晶片或半导体芯片90，需要用于除去与形成贯通通孔95相关的杂质的工艺，杂质可能会引起电流漏泄，并且整个工艺会变得更复杂。本发明解决了现有技术中的上述和其他不足。
发明内容
本发明提供了一种堆叠封装，该堆叠封装不仅能够提高堆叠封装的电学性质，而且能够通过简单的工艺提高堆叠封装的可靠性和批量生产的产量，还提供了一种制造该堆叠封装的方法。
根据本发明的一个方面，提供了一种堆叠封装，该堆叠封装包括：每一个具有键合衬垫的多个半导体芯片；每一个具有用于插入半导体芯片的空腔和位于半导体芯片与空腔的侧壁之间的互连端子槽的多个插入器；一把键合衬垫连接到形成于互连端子槽内的互连端子的再分布图案，其中研磨插入器的背面从而使互连端子暴露出来。
附图说明
本发明的以上和其他特征以及优点将通过其中参照附图的的详细实施例的描述变得更明显，其中：
图1是显示传统堆叠封装的结构的截面图；
图2是显示切割成单个半导体芯片之前的晶片的平面视图；
图3是显示根据本发明一些实施例的堆叠封装的结构的截面图；
图4至6是说明根据本发明一些实施例的堆叠封装的制作方法的截面图；
图7是图3的堆叠封装的平面视图。
具体实施方式
现在将在下文中参考附图对本发明进行更充分的描述，在图中示出了本发明的优选的实施例。但是本发明可以以不同的形式来具体实现，并且不应仅限于在此阐明的各实施例。
图3是显示根据本发明一些实施例的堆叠封装200的结构的截面图。参考此图，堆叠封装200包括半导体芯片110和插入器100。每个半导体芯片110被插入到相应的一个插入器100中。在堆叠封装200中，以垂直的布局来堆叠半导体芯片110和插入器100。在每个半导体芯片110上形成有键合衬垫130，该键合衬垫130被暴露出以便为了提供信号或电力的目的而被连接到引线(未示出)或再分布图案150，还形成有钝化层120，该钝化层120用于保护半导体芯片110的表面。例如，可以以铝层的形式来形成键合衬垫130，可以以氮化硅层(SiN)的形式来形成钝化层120。
半导体芯片110可以被垂直堆叠，同时每个半导体芯片110被插入到插入器100中。插入器100包括面积比半导体芯片110宽的空腔102(图4所示)，作为在其中插入半导体芯片110的位置，还包括互连端子槽170，该互连端子槽170是由于空腔102和半导体芯片110之间的面积差异而在空腔102中产生的空间。换句话说，互连端子槽包括在半导体芯片110和空腔102侧壁之间的空腔102的一部分。互连端子槽170的一部分被填充金属材料，以形成互连端子160。在插入器100中形成的互连端子160经由再分布图案150连接到键合衬垫130。
图4到6是说明根据本发明一些实施例的用于制造堆叠封装200的方法的截面图。图7是图3的堆叠封装200的平面视图。在下文中，将根据图3至7来描述堆叠封装200及其制作方法。
参照图4，准备了半导体芯片110，该半导体芯片11例如被测试工艺判定为合格产品(半导体芯片110可被描述为已知合格芯片(KGD))。堆叠多个插入器100，以及通过每一个都是对插入器100的背面进行研磨而被暴露出来的每个互连端子160相互连接起来，以便多个半导体芯片110互相堆叠并互相电连接。在本图中以通过切割工艺而从晶片分割下来的单个芯片的形式示出了半导体芯片110。但是，根据本发明的一些实施例，晶片状态的半导体芯片110被插入到插入器100中，并且在插入器100和晶片之间的间隙中形成互连端子160。因此，可以形成如下的晶片-晶片堆叠结构，在该结构中，每一个都具有互连端子160的多个插入器100彼此堆叠。
可以使用硅晶片、玻璃基底、或印刷电路板(PCB)来作为本发明的插入器100。而且，还可以使用任何能够形成互连端子160、并能够允许通过研磨插入器100的背面而暴露出互连端子160的材料来作为插入器100。尽管在本图中示出了通过切割晶片而形成的插入器100，但未切割的硅晶片本身也可以作为本发明的实施例。即，在通过切割晶片而形成的插入器的情况下、或在硅晶片本身的情况下，均可以堆叠本发明的插入器100。当堆叠的插入器是晶片状态时，在该晶片状态的插入器上形成再分布图案，并且通过研磨插入器的背面暴露出互连端子。然后，晶片状态的插入器被堆叠、并随后被切割，或被切割、并随后被堆叠。
在插入器100中形成空腔102，随后半导体芯片110被插入到该空腔102中。尽管空腔102的深度没有受到限制，但是空腔102的面积应该比半导体芯片110的面积大。这是因为，互连端子槽170是在由于空腔102和半导体芯片110之间的面积差而形成的空间内提供的。同样，半导体芯片110的扇出(fan out)是指，如果半导体芯片110的尺寸小到难以设置大量的引脚和焊球的程度，则使用附加的部件对将在其中设置引脚或焊球等互连元件的区域进行延展。在本发明中，半导体芯片110的扇出可以通过插入器100来实现。至此，插入器100比半导体芯片110的面积宽，宽出的面积是在实现芯片110的扇出时所需要的面积。
参照图5，通过在互连端子槽170中电镀金属形成互连端子160。根据一些实施例，可以通过对位于半导体芯片110和互连端子槽170表面上的籽晶金属层140进行图案化、并在籽晶金属层140上电镀金属，来形成把互连端子160与键合衬垫130相连接的再分布图案150。例如，通过溅射工艺，在钝化层120或互连端子槽170上沉积Ti/Cu层，然后通过包括曝光和刻蚀工艺在内的光刻工艺，将籽晶金属层图案化为期望的形状。根据其他的实施例，可以在钝化层和互连端子槽170上直接对再分布图案150进行图案化，而不需要形成籽晶金属层140。使用光刻工艺、电镀或类似的工艺进行图案化的任意方法都可以用来直接形成再分布图案150。
如果插入器100的背面B被研磨直到线A-A’，则暴露出互连端子160。当多个插入器100彼此堆叠时，外部连接端子180将暴露出的互连端子160彼此连接起来，或者将互连端子160连接到基底衬垫197。外部连接端子180可以是由铜、金、镍等制成的焊球或金属凸块。模块基底190包括光阻焊层195和基底衬垫197。作为绝缘钝化层的光阻焊层195被形成，以使得在模块基底190上形成的基底衬垫197暴露出来。基底衬垫197连接到模块基底190的配线，以将信号和电源传送到基底衬垫197。
在堆叠封装200中，半导体芯片110被插入到具有空腔102的插入器100，并且金属被填充在由于空腔102与半导体芯片110之间的面积差而形成的互连端子槽170中，从而形成互连端子160。接下来，通过研磨插入器100的背面而暴露出互连端子160，插入器100彼此堆叠，然后相对于互连端子160来实现电连接。这样的结构比在其中利用激光切割而形成贯通通孔并随后在该贯通通孔中形成金属贯通电极的传统结构简单得多。根据本发明的实施例中的结构，能够显著减少由于激光切割而产生的杂质和裂缝，能够提高晶片堆叠封装的产量，并能够避免晶片破损。此外，由于能够实现诸如晶片-晶片和单芯片-单芯片的堆叠之类的各种实施例，因此本结构具有很好的工艺适用性。同样，由于可以使用本发明的堆叠结构将半导体芯片110嵌入到插入器100中，所以本发明的结构的可靠性要比在其中形成贯通通孔的传统堆叠结构优越得多。互连端子160和外部连接端子180的互连长度都缩短了，其互连密度得到了提高，并且堆叠封装200的电学性质得到了显著提高。因此，实现了高速、高容量和多功能的封装。
参照图7，在互连端子槽170的一部分中填充弹性体175。弹性体175指的是如果受到外力拉伸便会延长、而如果外力撤销便会恢复到原始长度的聚合体。替代地，具有显著弹性的聚合体材料也可称为塑性体(plastomer)。弹性体175的代表性例子为弹性橡胶，比如丁二烯或苯乙烯，和弹性纤维，比如氨纶(spandex)。弹性体175用来保护互连端子160免受外力，并且保护互连端子160的互连稳定性。
此外，还可以在空腔102中提供对准器115。当将半导体芯片110插入到空腔102中时，对准器115用来对准半导体芯片110的位置。对准器115不限于图示的形状，而可以有各种其它形状和或不规则的形状。
根据本发明的一些实施例的堆叠封装的制作方法将简要描述如下：首先，将半导体芯片110插入至具有空腔102的插入器100中。形成将互连端子160连接到键合衬垫130的再分布图案150，以及在互连端子槽170中形成互连端子160。通过研磨插入器100的背面而暴露出互连端子160。根据需要，可以在互连端子槽170的一部分中填充弹性体175。然后，至少一个或多个插入器100彼此堆叠，互连端子160互相连接。当将堆叠的插入器100装配到模块基底190上时，互连端子160连接至基底衬垫197，从而完成堆叠封装。
如上所述，在根据本发明的一些实施例的堆叠封装和制作堆叠封装的方法中，能够显著减少由于激光切割产生的杂质和裂缝，能够提高晶片堆叠封装的产量，并避免晶片的破损。此外，由于能够实现诸如晶片-晶片和单芯片-单芯片之类的堆叠的各种实施例，所以本发明的结构具有很好的工艺适用性。同样，由于可以使用本发明的堆叠结构来将半导体芯片嵌入到插入器中，因此该结构的可靠性要比在其中形成贯通通孔的传统堆叠结构优越得多。由于互连端子与外部连接端子的互连长度和互连密度得到了改进，并且堆叠封装的电学性质得到显著提高，因此实现了高速、高容量和多功能的封装。
根据本发明的一个方面，提供了一种堆叠封装，该堆叠封装包括：每一个具有键合衬垫的多个半导体芯片；多个插入器，每个均具有在其中放置半导体芯片的空腔、以及位于半导体芯片与空腔的侧壁之间的互连端子槽；以及把键合衬垫连接到位于互连端子槽内的互连端子的再分布图案，其中通过插入器的背面暴露出互连端子。
这里，多个插入器可以相互堆叠，并且暴露出的互连端子可以相互连接，以使得多个半导体芯片相互堆叠并且电连接。堆叠封装可以进一步包括在互连端子槽的一部分中填充的弹性体。插入器可以是硅晶片、玻璃基底和印刷电路板(PCB)中的一种。插入器可包括从晶片切割下的一部分，或者包括硅晶片本身。插入器的面积可以比半导体芯片的面积宽，宽出的面积是在实现半导体芯片的扇出时所需的面积。堆叠封装可以进一步包括从键合衬垫到互连端子槽的图案化的籽晶金属层。再分布图案和互连端子可被镀在籽晶金属层上。堆叠封装可进一步包括在半导体芯片和籽晶金属层之间形成的钝化层。堆叠封装可以进一步包括当多个插入器彼此堆叠时，将暴露出的互连端子彼此互连起来的外部连接端子。堆叠封装可以进一步包括具有在其上堆叠了一个或多个插入器的基底衬垫的模块基底。互连端子可以连接至基底衬垫。堆叠封装可进一步包括当将半导体芯片插入至空腔中时，用来对准半导体芯片的位置的对准器。
根据本发明的一个方面，提供了一种堆叠封装，该堆叠封装包括至少一个或多个插入器，在该插入器中插入具有键合衬垫的半导体芯片，由于半导体芯片与其中插入半导体芯片的空腔之间的面积差而形成的互连端子槽，以及在互连端子槽中形成被连接到键合衬垫的互连端子，其中插入器彼此堆叠，并且互连端子相互连接，使得至少一个或多个半导体芯片彼此堆叠并相互电连接。
可以通过研磨插入器的背面直至暴露出互连端子槽，来暴露出互连端子。堆叠封装可以进一步包括在互连端子槽的一部分中填充的弹性体。插入器可以是硅晶片、玻璃基底和印刷电路板(PCB)中的一种。插入器可以包括被切割的晶片的一部分，或者包括硅晶片本身。插入器的面积比半导体芯片的面积宽，宽出的面积是在实现半导体芯片的扇出时所需的面积。堆叠封装可进一步包括当将半导体芯片插入至空腔时用来对准半导体芯片的位置的对准器。
根据本发明的一个方面，提供了一种制作堆叠封装的方法，该方法包括：将半导体芯片插入到具有空腔的插入器中；在由于空腔和半导体芯片之间的面积差而形成的互连端子槽中形成互连端子，以及将互连端子连接到在半导体芯片上形成的键合衬垫；研磨插入器的背面以暴露出互连端子；以及堆叠至少一个或多个插入器，并将互连端子彼此连接起来。
这里，封装堆叠封装的方法可以进一步包括在互连端子槽的一部分中填充弹性体。插入器可以包括被切割的晶片的一部分，或者包括硅晶片本身。
虽然已参考示例性实施例具体示出并描述了本发明，但本领域技术人员能够理解在不脱离通过所附的权利要求书限定的本发明的精神和范围的情况下，可以在其中做出各种形式与细节上的变动。

Claims (18)

1.一种堆叠封装，包括：
多个半导体芯片，每个半导体芯片均具有键合衬垫；
多个插入器，每个插入器均具有：在其中设置有所述半导体芯片的空腔、以及在所述半导体芯片与所述空腔侧壁之间的互连端子槽；以及
再分布图案，所述再分布图案将所述键合衬垫连接到在所述互连端子槽中设置的互连端子，
其中，所述互连端子通过插入器的背面而暴露出来。
2.如权利要求1所述的堆叠封装，其中，所述多个插入器相互堆叠，并且所述暴露出来的互连端子相互连接，以使得所述多个半导体芯片相互堆叠并电连接。
3.如权利要求1所述的堆叠封装，进一步包括弹性体，所述弹性体填充在所述互连端子槽的一部分中。
4.如权利要求1所述的堆叠封装，其中，所述插入器包括硅晶片、玻璃基底和印刷电路板(PCB)中的一种。
5.如权利要求1所述的堆叠封装，其中，所述插入器包括从晶片切割下的部分，或者包括硅晶片本身。
6.如权利要求1所述的堆叠封装，其中，每个插入器的面积比所述半导体芯片的面积宽，宽出的面积是在实现所述半导体芯片的扇出时所需的面积。
7.如权利要求1所述的堆叠封装，进一步包括从所述键合衬垫至所述互连端子槽设置的籽晶金属层，
其中，所述再分布图案和所述互连端子被镀在所述籽晶金属层上。
8.如权利要求7所述的堆叠封装，进一步包括钝化层，所述钝化层设置在所述半导体芯片和所述籽晶金属层之间。
9.如权利要求1所述的堆叠封装，进一步包括外部连接端子，所述外部连接端子将所述暴露出来的互连端子相互电连接起来。
10.如权利要求1所述的堆叠封装，进一步包括模块基底，所述模块基底具有基底衬垫，在其上堆叠一个或多个插入器，
其中，所述互连端子被连接至所述基底衬垫。
11.如权利要求1所述的堆叠封装，进一步包括对准器，所述对准器用于当将所述半导体芯片插入到所述空腔中时对准所述半导体芯片的位置。
12.一种堆叠封装，包括：
一个或多个插入器，每个插入器包括：
空腔，在所述空腔中设置具有键合衬垫的半导体芯片；
互连端子槽，所述互连端子槽被设置在所述半导体芯片和所述空腔的侧壁之间；以及
互连端子，所述互连端子被设置在所述互连端子槽中，并被连接到所述键合衬垫，
其中，所述插入器互相堆叠，并且所述互连端子相互连接，以使得所述半导体芯片堆叠并电连接。
13.如权利要求12所述的堆叠封装，其中，所述互连端子通过所述插入器的背面暴露出来。
14.如权利要求12所述的堆叠封装，进一步包括弹性体，所述弹性体设置在所述互连端子槽的一部分中。
15.如权利要求12所述的堆叠封装，其中，所述插入器是硅晶片、玻璃基底和印刷电路板(PCB)中的一种。
16.如权利要求12所述的堆叠封装，其中，所述插入器包括被切割的晶片的一部分，或者包括硅晶片本身。
17.如权利要求12所述的堆叠封装，其中，所述插入器的面积比所述半导体芯片的面积宽，宽出的面积是在实现所述半导体芯片的扇出时所需的面积。
18.如权利要求12所述的堆叠封装，进一步包括对准器，所述对准器用于当将所述半导体芯片插入到所述空腔中时对准所述半导体芯片的位置。
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