CN101154653A - 功率半导体模块 - Google Patents

功率半导体模块 Download PDF

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CN101154653A
CN101154653A CNA2007100921942A CN200710092194A CN101154653A CN 101154653 A CN101154653 A CN 101154653A CN A2007100921942 A CNA2007100921942 A CN A2007100921942A CN 200710092194 A CN200710092194 A CN 200710092194A CN 101154653 A CN101154653 A CN 101154653A
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power semiconductor
conductive pattern
circuit substrate
dielectric constant
housing
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CN101154653B (zh
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川口安人
林田幸昌
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Mitsubishi Electric Corp
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Abstract

本发明得到一种通过减少部分放电从而可实现产品的长寿命化的功率半导体模块。本发明的功率半导体模块具有:散热板(1);电路衬底(2),安装在散热板(1)上;导电图形(10),设置在电路衬底(2)上;低介电常数膜(11),覆盖导电图形(10);壳体(7),以包围电路衬底(2)的方式设置在散热板(1)上;以及柔软绝缘物(9),填充在壳体(7)内。低介电常数膜(11)优选是硅橡胶、聚酰亚胺和环氧树脂的任意一种。

Description

功率半导体模块
技术领域
本发明涉及通过减少部分放电从而可实现产品的长寿命化的功率半导体模块。
背景技术
作为现有的功率半导体模块(power semiconductor module),其具有散热板、安装在散热板上的电路衬底、设置在电路衬底上的导电图形、以包围电路衬底的方式设置在散热板上的壳体、以及填充在壳体内的柔软绝缘物,而且,从提高绝缘耐压特性的可靠性的观点来看,提出有与导电图形的外周部相接触地在电路衬底的上表面设置固体绝缘物的方案(例如,参照专利文献1)。
【专利文献1】特开2002-76197号公报
但是,功率半导体模块在高施加电压中使用,由此,存在从功率半导体模块内部的浮置电位部分发生部分放电、产生绝缘不良的情况。特别是发现在做成复杂形状的两面带电极驱动电路衬底上容易发生部分放电。
发明内容
本发明是为了解决如上所述的问题而进行的,其目的是:得到一种通过减少部分放电(partial discharge)从而可实现产品的长寿命化的功率半导体模块。
本发明的功率半导体模块具有:散热板;电路衬底,安装在散热板上;导电图形,设置在电路衬底上;低介电常数膜,覆盖导电图形;壳体,以包围电路衬底的方式设置在散热板上;以及柔软绝缘物,填充在壳体内。本发明的其他的特征可由以下内容得知。
按照本发明,通过减少部分放电,从而可实现产品的长寿命化。
附图说明
图1是表示本发明的实施方式1的功率半导体模块的剖面图。
图2是表示本发明的实施方式1的功率半导体模块的俯视图。
图3是图2所示的功率半导体模块中的一个电路块的等效电路。
图4是图1的A部的放大剖面图。
图5是表示本发明的实施方式2的驱动电路衬底的俯视图。
图6是表示本发明的实施方式3的驱动电路衬底的俯视图。
图7是表示本发明的实施方式4的驱动电路衬底的俯视图。
具体实施方式
实施方式1
图1是表示本发明的实施方式1的功率半导体模块的剖面图,图2是其俯视图。该功率半导体模块内置有多个电路块,该电路块构成为:并联连接多个IGBT,具备共用的集电极端子、发射极端子和栅极端子,由此,得到高耐压、大电流特性。作为参考,如图3所示,以等效电路表示出其一个块。
在金属制的底板(base plate)1(散热板)上安装有驱动电路衬底2(电路衬底)、功率半导体电路衬底3和中继电路衬底13。以在陶瓷等绝缘衬底的两面设置由铜或者铝等构成的导电(电极)图形10的方式构成各个电路衬底,在功率半导体电路衬底3的导电图形上使用焊料等导电性粘接部件接合有绝缘栅双极型晶体管(IGBT)4a和续流二极管(FWDi)4b等功率半导体元件(芯片)4,此外,在驱动电路衬底2的导电图形上使用焊料等导电性粘接部件接合有芯片电阻14。功率半导体元件4中的电极(IGBT4a的发射极、栅极以及FWDi 4b的阳极)使用Al等引线5电连接到驱动电路衬底2或者中继电路衬底13上。此处,预先进行整理,使得IGBT4a的发射极和FWDi 4b的阳极经由引线5与中继电路衬底的导电图形10连接,IGBT4a的栅极经由引线5与驱动电路村底2的导电图形10连接,IGBT4a的集电极和FWDi 4b的阴极经由功率半导体电路衬底3的导电图形10相互连接。而且,以包围驱动电路衬底2、功率半导体电路衬底3以及中继电路衬底13的方式在底板1上设置树脂壳体(case)7,在壳体7的上部配置有盖(lid)8。进而,为了保持气密性和绝缘,在壳体7内填充硅胶9(柔软绝缘物)。此外,各个电路衬底具备电极端子接合区域15,在该电极端子接合区域15中安装有实现与装置外部的电连接的电极端子(未图示)。另外,虽然在该说明中,功率半导体电路衬底3和中继电路衬底13被分离为不同的衬底,但是,也可以在同一个绝缘衬底上分开导电图形的形成区域来构成。
图4是图1的A部的放大剖面图。在驱动电路衬底2上设置有由铜、铝等金属构成的导电图形10。而且,以覆盖导电图形10的方式设置有低介电常数膜11。由此,可减少做成复杂形状的驱动电路衬底2处的部分放电,因此,能够实现产品的长寿命化。另外,对于功率半导体电路衬底3以及中继电路衬底13,与现有技术相同,与导电图形的外周部相接触地在绝缘衬底的上表面设置低介电常数膜11,由此,可希望绝缘耐压的提高,无需如驱动电路衬底2那样覆盖导电图形。
此处,作为低介电常数膜11,可使用硅橡胶、聚酰亚胺和环氧树脂等。特别是,作为低介电常数膜11,若使用硅橡胶则容易装配,若使用聚酰亚胺则耐热性会提高,若使用环氧树脂则热循环性会提高。
另外,简单地对低介电常数膜11的形成步骤进行说明,在驱动电路衬底2的情况下,首先,通过焊料等将芯片电阻14接合在驱动电路衬底2的导电图形上的预定位置上,通过铝引线的超声波接合等来连接驱动电路衬底2的导电图形中的引线键合位置和功率半导体电路衬底3上的功率半导体元件4具体地说是与IGBT4a的栅电极之间。接着,通过焊料等将电极端子接合在导电图形10中的电极端子接合区域15上之后,以覆盖导电图形10的方式涂敷低介电常数膜11。另一方面,功率半导体电路衬底3或者中继电路村底13中的低介电常数膜11的形成如下:以焊料等将功率半导体元件4接合在功率半导体电路衬底3的导电图形上的预定位置上之后,在进行引线键合或者电极端子的接合之前,与导电图形的外周部相接触地涂敷在绝缘衬底的上表面上。
实施方式2
图5是表示本发明的实施方式2的驱动电路衬底的俯视图。在本实施方式中,导电图形10的角(corner)部为圆形(round)。其他结构与实施方式1相同。由此,与实施方式1相比,可更减少部分放电,所以,可实现产品的进一步长寿命化。
实施方式3
图6是表示本发明的实施方式3的驱动电路衬底的俯视图。在本实施方式中,导电图形10为圆形。而且,没有以低介电常数膜11覆盖导电图形10。其他结构与实施方式1相同。由此,可减少做成复杂形状的驱动电路村底2处的部分放电,所以,可实现产品的长寿命化。
实施方式4
图7是表示本发明的实施方式4的驱动电路衬底的俯视图。在本实施方式中,以低介电常数膜11覆盖导电图形10。其他结构与实施方式3相同。由此,与实施方式3相比,可更减少部分放电,所以,可实现产品的进一步长寿命化。

Claims (5)

1.一种功率半导体模块,其特征在于,具有:
散热板;
电路衬底,安装在所述散热板上;
导电图形,设置在所述电路衬底上;
低介电常数膜,覆盖所述导电图形;
壳体,以包围所述电路衬底的方式设置在所述散热板上;
盖,配置在所述壳体的上部;以及
柔软绝缘物,填充在所述壳体内。
2.如权利要求1记载的功率半导体模块,其特征在于,
所述低介电常数膜是硅橡胶、聚酰亚胺和环氧树脂的任意一种。
3.如权利要求1或2记载的功率半导体模块,其特征在于,
所述导电图形的角部为圆形。
4.一种功率半导体模块,其特征在于,具有:
散热板;
电路衬底,安装在所述散热板上;
圆形的导电图形,设置在所述电路衬底上;
壳体,以包围所述电路衬底的方式设置在所述散热板上;以及
柔软绝缘物,填充在所述壳体内。
5.如权利要求4记载的功率半导体模块,其特征在于,
还具有覆盖所述导电图形的低介电常数膜。
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