CN105830204B - 功率半导体模块 - Google Patents

功率半导体模块 Download PDF

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CN105830204B
CN105830204B CN201380081727.0A CN201380081727A CN105830204B CN 105830204 B CN105830204 B CN 105830204B CN 201380081727 A CN201380081727 A CN 201380081727A CN 105830204 B CN105830204 B CN 105830204B
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power semiconductor
semiconductor chip
dielectric constant
insulating substrate
film
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CN105830204A (zh
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川口安人
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

本发明缓和功率半导体芯片表面的电场强度，实现制造工序内缺陷的减少、以及可靠性的提高。本发明具有配置在绝缘基板(2)之上的功率半导体芯片(4)，本发明还具有：配线(5)，其与功率半导体芯片的元件区域(4A)处的表面导体图案连接；低介电常数膜(8)，其配置在配线与周边区域(4B)之间；以及封装材料(6)，其是覆盖绝缘基板、功率半导体芯片、配线以及低介电常数膜而形成的，低介电常数膜具有比封装材料低的介电常数。

Description

功率半导体模块
技术领域
本发明涉及一种功率半导体模块，该功率半导体模块被用于对电动机等电气设备进行控制的电力转换装置等。
背景技术
关于作为对电动机等电气设备进行控制的电力转换装置而使用的功率半导体模块，在制造工序内对该功率半导体模块实施出货筛选试验。作为该出货筛选试验，具有例如被称为CBS(Cold Bias Stability)试验的常温(25℃)下的电压施加试验(参照专利文献1)。
专利文献1：日本特公昭63-28346号公报
发明内容
在进行作为出货筛选试验的CBS试验的情况下，在试验中功率半导体模块的漏电流增加，有时会导致功率半导体模块的破坏。
该破坏被认为是因为下述情况而发生的，即，由于施加高电压，功率半导体模块内成为高电场，硅凝胶中产生电荷，由于该电荷，功率半导体芯片表面的电场强度分布变得不稳定，漏电流局部地增加。并且，作为电场强度分布变得不稳定的要因，被认为是由功率半导体芯片的表面状态或导线键合的高度等带来的影响。
本发明就是为了解决上述这样的问题而提出的，其目的在于提供一种功率半导体模块，该功率半导体模块不仅限于CBS试验，在以通常的状态对功率半导体模块施加电压的情况下，也通过缓和功率半导体芯片表面的电场强度，从而实现功率半导体模块的制造工序内缺陷的减少、以及功率半导体模块的可靠性的提高。
本发明的一个方式涉及的功率半导体模块具有：绝缘基板；以及功率半导体芯片，其配置在所述绝缘基板之上，在所述绝缘基板的表面之上，形成上表面电极，在所述功率半导体芯片的表面之上，形成表面导体图案，在所述功率半导体芯片的背面之上，形成背面导体图案，在所述功率半导体芯片的表面规定元件区域和周边区域，该周边区域在俯视观察时包围所述元件区域，所述绝缘基板的所述上表面电极和所述功率半导体芯片的所述背面导体图案经由焊料而连接，该功率半导体模块还具有：配线，其与所述功率半导体芯片的所述元件区域处的所述表面导体图案连接；低介电常数膜，其配置在所述配线与所述周边区域之间；以及封装材料，其是覆盖所述绝缘基板、所述功率半导体芯片、所述配线以及所述低介电常数膜而形成的，所述低介电常数膜具有比所述封装材料低的介电常数。
本发明的其他方式涉及的功率半导体模块具有：绝缘基板；以及功率半导体芯片，其配置在所述绝缘基板之上，在所述绝缘基板的表面之上，形成上表面电极，在所述功率半导体芯片的表面之上，形成表面导体图案，在所述功率半导体芯片的背面之上，形成背面导体图案，在所述功率半导体芯片的表面规定元件区域和周边区域，该周边区域在俯视观察时包围所述元件区域，所述绝缘基板的所述上表面电极和所述功率半导体芯片的所述背面导体图案经由焊料而连接，该功率半导体模块还具有：配线，其与所述功率半导体芯片的所述元件区域处的所述表面导体图案连接；屏蔽基板，其为导体，配置在所述配线与所述周边区域之间；以及封装材料，其是覆盖所述绝缘基板、所述功率半导体芯片、所述配线以及所述屏蔽基板而形成的。
本发明的其他方式涉及的功率半导体模块具有：绝缘基板；以及功率半导体芯片，其配置在所述绝缘基板之上，在所述绝缘基板的表面之上，形成上表面电极，在所述功率半导体芯片的表面之上，形成表面导体图案，在所述功率半导体芯片的背面之上，形成背面导体图案，在所述功率半导体芯片的表面规定元件区域和周边区域，该周边区域在俯视观察时包围所述元件区域，所述绝缘基板的所述上表面电极和所述功率半导体芯片的所述背面导体图案经由焊料而连接，该功率半导体模块还具有：配线，其与所述功率半导体芯片的所述元件区域处的所述表面导体图案连接；以及封装材料，其是覆盖所述绝缘基板、所述功率半导体芯片以及所述配线而形成的，所述配线沿从所述功率半导体芯片的表面离开的方向延伸而进行配线。
发明的效果
根据本发明的上述方式，由于能够抑制由配线引起的电场对功率半导体芯片表面造成的影响，因此功率半导体芯片表面的电场强度变得稳定，能够实现功率半导体模块的制造工序内缺陷的减少、以及功率半导体模块的可靠性的提高。
本发明的目的、特征、技术方案以及优点通过以下的详细的说明和附图会变得更加明白。
附图说明
图1是实施方式涉及的功率半导体模块的剖视图。
图2是实施方式涉及的功率半导体模块的放大剖视图。
图3是实施方式涉及的功率半导体模块的放大剖视图。
图4是对图3的构造进行俯视观察的图。图5是实施方式涉及的功率半导体模块的放大剖视图。
图6是实施方式涉及的功率半导体模块的放大剖视图。
图7是实施方式涉及的功率半导体模块的放大剖视图。
图8是实施方式涉及的功率半导体模块的放大剖视图。
图9是实施方式涉及的功率半导体模块的放大剖视图。
图10是对图9的构造进行俯视观察的图。
具体实施方式
下面，一边参照附图，一边对实施方式进行说明。
此外，在本实施方式中，使用了表面、背面、上表面或下表面等用语，但这些用语是为了便于区分各表面而使用的，与实际的上下左右的方向无关。
<第1实施方式>
<结构>
图1是本实施方式涉及的功率半导体模块的整体的剖视图。
如图1所示，功率半导体模块具有：散热板1；绝缘基板2，其与散热板1相接合；铝线5(配线)，其被配线至绝缘基板2之上的功率半导体芯片；壳体7，其是包围这些结构而形成的；以及硅凝胶6(封装材料)，其被填充在壳体7内且为绝缘物。
图2是本实施方式涉及的功率半导体模块的放大剖视图。图2对应于放大后的图1中的A部。
如图2所示，功率半导体模块具有：散热板1；绝缘基板2，其与散热板1相接合；以及功率半导体芯片4，其配置在绝缘基板2之上。
绝缘基板2具有：上表面电极2A，其形成在上表面；以及下表面电极2B，其形成在上表面的相反侧的面即下表面。
散热板1和下表面电极2B经由焊料3而相接合。另外，上表面电极2A和功率半导体芯片4的背面导体图案经由焊料3而相接合。
功率半导体芯片4之上的表面导体图案(即，在与背面导体图案相反侧的面配置的导体图案)与铝线5连接。并且，覆盖功率半导体芯片4的整个表面而形成有低介电常数膜8。
低介电常数膜8是硅橡胶、聚酰亚胺及环氧树脂中任意方，作为绝缘物而起作用。介电常数例如为2.0～3.0(F/m)。
并且，覆盖散热板1、绝缘基板2、功率半导体芯片4、铝线5以及低介电常数膜8而形成有作为绝缘物的硅凝胶6。硅凝胶6与低介电常数膜8相比介电常数高。换言之，低介电常数膜8与作为封装材料的硅凝胶6相比介电常数低。
在图2中虽未图示，但硅凝胶6是被填充于壳体7而形成的。
<效果>
根据本实施方式，功率半导体模块具有：绝缘基板2；以及功率半导体芯片4，其配置在绝缘基板2之上。
在绝缘基板2的表面之上，形成有上表面电极2A。在功率半导体芯片4的表面之上，形成有表面导体图案。在功率半导体芯片4的背面之上，形成有背面导体图案。在功率半导体芯片4的表面规定有元件区域4A和周边区域4B，该周边区域4B在俯视观察时包围元件区域4A。绝缘基板2的上表面电极2A和功率半导体芯片4的背面导体图案经由焊料3而连接。
并且，功率半导体模块具有：作为配线的铝线5，其与功率半导体芯片4的元件区域4A处的表面导体图案连接；低介电常数膜8，其配置在铝线5与周边区域4B之间；以及作为封装材料的硅凝胶6，其是覆盖绝缘基板2、功率半导体芯片4、铝线5以及低介电常数膜8而形成的。
并且，低介电常数膜8具有比硅凝胶6低的介电常数。
根据这样的结构，低介电常数膜8配置在铝线5与周边区域4B之间，由此能够利用低介电常数膜8缓和由铝线5引起的电场，抑制该电场对功率半导体芯片4表面(尤其是周边区域4B)造成的影响，因此功率半导体芯片4表面的电场强度变得稳定，能够实现功率半导体模块的制造工序内缺陷的减少、以及功率半导体模块的可靠性的提高。
<第2实施方式>
<结构>
图3是本实施方式涉及的功率半导体模块的放大剖视图。下面，对与图2所示的结构相同的结构标注相同的标号而示出，适当省略相同的说明。图4是对图3的构造进行俯视观察的图。其中，为了简化而省略了硅凝胶6的图示。
如图3及图4所示，在该功率半导体模块，横跨功率半导体芯片4表面的元件区域4A的局部及周边区域4B的局部而形成有低介电常数膜8A，该周边区域4B形成为在俯视观察时包围元件区域4A。在这里，元件区域是指主要作为有源元件而起作用的区域。
更具体地说，至少将俯视观察时与铝线5的配线路径重叠的部分的周边区域4B覆盖而形成有低介电常数膜8A。
低介电常数膜8A是硅橡胶、聚酰亚胺及环氧树脂中任意方，作为绝缘物而起作用。
<效果>
根据本实施方式，低介电常数膜8A是覆盖所述功率半导体芯片4的表面的、俯视观察时与铝线5的配线路径重叠的部分的周边区域4B而形成的。
根据这样的结构，由于能够抑制由铝线5引起的电场对尤其是周边区域4B造成的影响，因此功率半导体芯片4表面的电场强度变得稳定，能够实现功率半导体模块的制造工序内缺陷的减少、以及功率半导体模块的可靠性的提高。
<第3实施方式>
<结构>
图5是本实施方式涉及的功率半导体模块的放大剖视图。下面，对与图2所示的结构相同的结构标注相同的标号而示出，适当省略相同的说明。
如图5所示，在该功率半导体模块，覆盖铝线5的表面而形成有低介电常数膜8B。
更优选的是，至少将俯视观察时与功率半导体芯片4表面的周边区域4B重叠的部分的铝线5覆盖而形成有低介电常数膜8B即可。
低介电常数膜8B是硅橡胶、聚酰亚胺及环氧树脂中任意方，作为绝缘物而起作用。
<效果>
根据本实施方式，低介电常数膜8B是覆盖作为所述配线的铝线5的表面而形成的。
根据这样的结构，能够利用覆盖铝线5表面的低介电常数膜8B抑制由铝线5引起的电场，缓和该电场对功率半导体芯片4表面的电场强度造成的影响，因此功率半导体芯片4表面的电场强度变得稳定，能够实现功率半导体模块的制造工序内缺陷的减少、以及功率半导体模块的可靠性的提高。
<第4实施方式>
<结构>
图6是本实施方式涉及的功率半导体模块的放大剖视图。下面，对与图2所示的结构相同的结构标注相同的标号而示出，适当省略相同的说明。
如图6所示，在该功率半导体模块未设置低介电常数膜。另外，与上述其他实施方式的情况相比，铝线5A在更上方进行配线。
即，与上述其他实施方式的情况相比，功率半导体芯片4表面的周边区域4B与铝线5A之间的距离X更大。具体地说，优选周边区域4B与铝线5A之间的距离(在图6中为垂直方向的距离)大于或等于3mm。
<效果>
根据本实施方式，功率半导体模块具有：绝缘基板2；以及功率半导体芯片4，其配置在绝缘基板2之上。
在绝缘基板2的表面之上，形成有上表面电极2A。在功率半导体芯片4的表面之上，形成有表面导体图案。在功率半导体芯片4的背面之上，形成有背面导体图案。在功率半导体芯片4的表面规定有元件区域4A和周边区域4B，该周边区域4B在俯视观察时包围元件区域4A。绝缘基板2的上表面电极2A和功率半导体芯片4的背面导体图案经由焊料3而连接。
另外，功率半导体模块具有：铝线5A，其与功率半导体芯片4的元件区域4A处的表面导体图案连接；以及硅凝胶6，其是覆盖绝缘基板2、功率半导体芯片4以及铝线5A而形成的。
铝线5A沿从功率半导体芯片4的表面离开的方向延伸而进行配线。
根据这样的结构，铝线5A与周边区域4B之间的距离变大，由此能够抑制由铝线5A引起的电场对功率半导体芯片4表面(尤其是周边区域4B)造成的影响，因此功率半导体芯片4表面的电场强度变得稳定，能够实现功率半导体模块的制造工序内缺陷的减少、以及功率半导体模块的可靠性的提高。
<第5实施方式>
<结构>
图7是本实施方式涉及的功率半导体模块的放大剖视图。下面，对与图2所示的结构相同的结构标注相同的标号而示出，适当省略相同的说明。
如图7所示，在该功率半导体模块未设置低介电常数膜。另外，代替铝线，将铜电极9与功率半导体芯片4之上的表面导体图案直接连接，该铜电极9是向上方延伸而形成的。
即，与上述第1～3实施方式的情况相比，功率半导体芯片4表面的周边区域4B与铜电极9之间的距离更大。
此外，铜电极9延伸的方向优选与功率半导体芯片4表面正交。
<效果>
根据本实施方式，配线是与功率半导体芯片4的表面导体图案直接连接的铜电极9。
根据这样的结构，铜电极9与周边区域4B之间的距离变大，由此能够抑制由铜电极9引起的电场对功率半导体芯片4表面(尤其是周边区域4B)造成的影响，因此功率半导体芯片4表面的电场强度变得稳定，能够实现功率半导体模块的制造工序内缺陷的减少、以及功率半导体模块的可靠性的提高。
<第6实施方式>
<结构>
图8是本实施方式涉及的功率半导体模块的放大剖视图。下面，对与图2所示的结构相同的结构标注相同的标号而示出，适当省略相同的说明。
如图8所示，在该功率半导体模块未设置低介电常数膜。另外，铝线5B与功率半导体芯片4之上的表面导体图案连接，该铝线5B是向上方延伸而形成的。
即，与上述第1～3实施方式的情况相比，功率半导体芯片4表面的周边区域4B与铝线5B之间的距离更大。
此外，铝线5B延伸的方向优选与功率半导体芯片4表面正交。
<效果>
根据本实施方式，铝线5B沿与功率半导体芯片4的表面正交的方向延伸而进行配线。
根据这样的结构，铝线5B与周边区域4B之间的距离变大，由此能够抑制由铝线5B引起的电场对功率半导体芯片4表面(尤其是周边区域4B)造成的影响，因此功率半导体芯片4表面的电场强度变得稳定，能够实现功率半导体模块的制造工序内缺陷的减少、以及功率半导体模块的可靠性的提高。
<第7实施方式>
<结构>
图9是本实施方式涉及的功率半导体模块的放大剖视图。下面，对与图2所示的结构相同的结构标注相同的标号而示出，适当省略相同的说明。图10是对图9的构造进行俯视观察的图。其中，为了简化而省略了硅凝胶6的图示。
如图9及图10所示，在该功率半导体模块，横跨功率半导体芯片4之上的局部及绝缘基板2之上的局部而形成有屏蔽基板10。在图10中，示出了具有开口部10A的屏蔽基板10，该开口部10A用于对铝线5进行配线。
更优选的是，至少横跨于俯视观察时与铝线5的配线路径重叠的部分的功率半导体芯片4之上的周边区域4B之上而形成有屏蔽基板10即可。
屏蔽基板10为导体，例如由铜构成。
<效果>
根据本实施方式，功率半导体模块具有：绝缘基板2；以及功率半导体芯片4，其配置在绝缘基板2之上。
在绝缘基板2的表面之上，形成有上表面电极2A。在功率半导体芯片4的表面之上，形成有表面导体图案。在功率半导体芯片4的背面之上，形成有背面导体图案。在功率半导体芯片4的表面规定有元件区域4A和周边区域4B，该周边区域4B在俯视观察时包围元件区域4A。绝缘基板2的上表面电极2A和功率半导体芯片4的背面导体图案经由焊料3而连接。
另外，功率半导体模块具有：铝线5，其与功率半导体芯片4的元件区域4A处的表面导体图案连接；屏蔽基板10，其为导体，配置在铝线5与周边区域4B之间；以及作为封装材料的硅凝胶6，其是覆盖绝缘基板2、功率半导体芯片4、铝线5以及屏蔽基板10而形成的。
根据这样的结构，作为导体的屏蔽基板10配置在铝线5与周边区域4B之间，由此能够利用屏蔽基板10截断由铝线5引起的电场，抑制该电场对功率半导体芯片4表面(尤其是周边区域4B)造成的影响，因此功率半导体芯片4表面的电场强度变得稳定，能够实现功率半导体模块的制造工序内缺陷的减少、以及功率半导体模块的可靠性的提高。
在上述实施方式中，虽然还记载了各结构要素的材质、材料或者实施条件等，但这些在所有方案中都仅是例示，并不限于所记载的内容。因此，在本发明的范围内可以设想出未例示的无数的变形例(包含任意结构要素的变形或者省略、以及不同实施方式间的自由组合)。
标号的说明
1散热板，2绝缘基板，2A上表面电极，2B下表面电极，3焊料，4功率半导体芯片，4A元件区域，4B周边区域，5、5A、5B铝线，6硅凝胶，7壳体，8、8A、8B低介电常数膜,9铜电极,10屏蔽基板,10A开口部。

Claims (4)

1.一种功率半导体模块，其具有：
绝缘基板；以及
功率半导体芯片，其配置在所述绝缘基板之上，
在所述绝缘基板的表面之上，形成上表面电极，
在所述功率半导体芯片的表面之上，形成表面导体图案，
在所述功率半导体芯片的背面之上，形成背面导体图案，
在所述功率半导体芯片的表面规定元件区域和周边区域，该周边区域在俯视观察时包围所述元件区域，
所述绝缘基板的所述上表面电极和所述功率半导体芯片的所述背面导体图案经由焊料而连接，
该功率半导体模块还具有：
配线，其与所述功率半导体芯片的所述元件区域处的所述表面导体图案连接；
低介电常数膜，其配置在所述配线与所述周边区域之间；以及
封装材料，其是覆盖所述绝缘基板、所述功率半导体芯片、所述配线以及所述低介电常数膜而形成的，
所述低介电常数膜具有比所述封装材料低的介电常数，
所述低介电常数膜位于所述功率半导体芯片的表面之上。
2.根据权利要求1所述的功率半导体模块，其中，
所述低介电常数膜是覆盖所述功率半导体芯片的表面的、俯视观察时与所述配线的配线路径重叠的部分的所述周边区域而形成的。
3.根据权利要求1或2所述的功率半导体模块，其中，
所述低介电常数膜是覆盖所述功率半导体芯片的整个表面而形成的。
4.一种功率半导体模块，其具有：
绝缘基板；以及
功率半导体芯片，其配置在所述绝缘基板之上，
在所述绝缘基板的表面之上，形成上表面电极，
在所述功率半导体芯片的表面之上，形成表面导体图案，
在所述功率半导体芯片的背面之上，形成背面导体图案，
在所述功率半导体芯片的表面规定元件区域和周边区域，该周边区域在俯视观察时包围所述元件区域，
所述绝缘基板的所述上表面电极和所述功率半导体芯片的所述背面导体图案经由焊料而连接，
该功率半导体模块还具有：
配线，其与所述功率半导体芯片的所述元件区域处的所述表面导体图案连接；
低介电常数膜，其配置在所述配线与所述周边区域之间；以及
封装材料，其是覆盖所述绝缘基板、所述功率半导体芯片、所述配线以及所述低介电常数膜而形成的，
所述低介电常数膜具有比所述封装材料低的介电常数，
所述低介电常数膜是覆盖所述配线的表面而形成的。
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