JP5732955B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5732955B2 JP5732955B2 JP2011067769A JP2011067769A JP5732955B2 JP 5732955 B2 JP5732955 B2 JP 5732955B2 JP 2011067769 A JP2011067769 A JP 2011067769A JP 2011067769 A JP2011067769 A JP 2011067769A JP 5732955 B2 JP5732955 B2 JP 5732955B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- conductive plate
- bus bar
- electrode
- outer peripheral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 108
- 230000002093 peripheral effect Effects 0.000 claims description 33
- 238000013459 approach Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 description 31
- 230000007423 decrease Effects 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 239000003566 sealing material Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910016525 CuMo Inorganic materials 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Wire Bonding (AREA)
Description
(1)上記の実施例では、導電板材50の各外周面106、108、110、112がいずれも底面102から上面104に向かう方向に傾斜している。これに代えて、導電板材50の各外周面106、108、110、112のうち少なくとも1面を傾斜させずに半導体素子40に対して鉛直になるように形成してもよい。このようにしても、他の外周面を傾斜させることで、導電板材50の上面104の面積を底面102の面積より大きくすることができる。
(2)導電板材50の材料は、Cuに限らず、CuMo、Mo等、他の材料であってもよい。また、導電板材50と表面電極44とを接続する接合材料も、Ag等、他の材料であってもよい。
(3)半導体素子40には、IGBTに限らず、MOSFETやダイオード等の他のパワー半導体素子が用いられていてもよい。また、半導体素子40は、SiC材料製のものに限られず、Si材料製のものであってもよい。
10:放熱板
12:はんだ
14:絶縁層
20:信号端子
30:小電流用ワイヤ
40:半導体素子
42:信号電極
44:表面電極
45:絶縁層
50:導電板材
60:大電流用ワイヤ
70:ハウジング
80:バスバー
102:底面
104:上面
106:第1外周面
108:第3外周面
110:第2外周面
112:第4外周面
Claims (1)
- 半導体装置であって、
表面に主電極が形成されている半導体素子と、
前記主電極の上面に接合される導電板材と、
前記半導体素子と並んで配置されるバスバーと、
を有しており、
前記導電板材は、前記主電極と対向する第1面と、前記第1面と反対側であって、第1ワイヤがボンディングされる領域を有する第2面とを備え、
前記半導体素子の表面には、第2ワイヤがボンディングされる領域を有する信号電極がさらに形成されており、その信号電極は、前記信号電極と前記バスバーの間に前記主電極が位置するように配置されており、
前記第1ワイヤは、一端が前記第2面にボンディングされるとともに、他端が前記バスバーにボンディングされ、
前記導電板材は、一端縁が前記第1面の周縁に接続されると共に他端縁が前記第2面の周縁に接続される外周面を有しており、前記外周面のうち前記バスバー側の第1外周面が、前記半導体素子から離れるに従って前記バスバーに近づくように形成されており、前記外周面のうち前記信号電極側の第2外周面が、前記半導体素子から離れるに従って前記バスバーに近づくように形成されており、前記第2面の面積は前記第1面の面積より大きい、
半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011067769A JP5732955B2 (ja) | 2011-03-25 | 2011-03-25 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011067769A JP5732955B2 (ja) | 2011-03-25 | 2011-03-25 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012204600A JP2012204600A (ja) | 2012-10-22 |
JP5732955B2 true JP5732955B2 (ja) | 2015-06-10 |
Family
ID=47185245
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011067769A Active JP5732955B2 (ja) | 2011-03-25 | 2011-03-25 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP5732955B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016171122A1 (ja) * | 2015-04-21 | 2016-10-27 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2865099B1 (ja) * | 1997-10-15 | 1999-03-08 | 日本電気株式会社 | 半導体装置 |
JP3559468B2 (ja) * | 1999-03-29 | 2004-09-02 | 京セラ株式会社 | 薄膜配線基板の製造方法 |
-
2011
- 2011-03-25 JP JP2011067769A patent/JP5732955B2/ja active Active
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JP2012204600A (ja) | 2012-10-22 |
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