CN101131984A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 78
- 239000002184 metal Substances 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 230000004888 barrier function Effects 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 229910008482 TiSiN Inorganic materials 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 description 27
- 238000005516 engineering process Methods 0.000 description 23
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000005518 electrochemistry Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
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Abstract
本发明提供一种半导体器件及其制造方法。该高效的制造方法涉及分别单独制造具有晶体管层的第一衬底和具有金属线层的第二衬底,并叠置该第一和第二衬底。在该第一衬底上的晶体管通过连接电极与在该第二衬底上的金属线电连接。
Description
技术领域
本发明涉及一种半导体器件及其制造方法。
背景技术
半导体器件制造工艺通常可以分成两个步骤。第一个步骤是形成晶体管层的步骤,例如衬底制造工艺或前端(FEOL)制造工艺。第二个步骤是形成金属线(metal wire)的步骤,例如布线工艺或后端(BEOL)制造工艺。
完整的制造工艺包含:制备半导体衬底、在硅晶片上形成晶体管的工艺以及连接金属电极引线并使其绝缘的工艺。当在硅晶片上顺序执行这些步骤时,完整的器件制造变得非常费时。
发明内容
本发明实施例涉及一种半导体器件以及可提高产量的简化制造方法。
在本发明实施例中,一种半导体器件可包含:第一衬底,其包含具有至少一个晶体管的晶体管层。第二衬底可包含具有至少一条金属线的金属线层。连接电极可用于使得该第一衬底的晶体管与该第二衬底的金属线电连接。
在本发明实施例中,一种半导体器件的制造方法,包含下列步骤:形成具有晶体管层的第一衬底,其中该晶体管层包含晶体管。形成具有金属线层的第二衬底,其中该金属线层具有金属线、将该第二衬底叠置于该第一衬底上,并将该晶体管电连接至该金属线。
附图说明
图1为示出通过根据本发明实施例的半导体器件制造方法形成的具有晶体管层的衬底的示意图。
图2为示出通过根据本发明实施例的半导体器件制造方法形成的具有金属线层的衬底的示意图。
图3为示出通过根据本发明实施例的半导体器件制造方法形成的具有晶体管层和金属线层的半导体器件的示意图。
具体实施方式
本发明实施例引入了一种高效的半导体器件的制造方法,该半导体器件制造方法可以分别单独制造具有晶体管层的第一衬底和具有金属线层的第二衬底;并叠置该第一衬底和该第二衬底。在该第一衬底上的晶体管通过连接电极电连接至在该第二衬底上的金属布线。
如图1的实例所示,通过根据本发明实施例的方法制造第一衬底100,其具有晶体管层110和金属线层120。在晶体管层110中形成晶体管115。晶体管115可通过接触塞117电连接至金属线层120的金属线121。
尽管图1的实例示出了在晶体管层110上的一金属线层120,但是根据本方法的其它实施例还可以形成多个金属线层。可选地,制造第一衬底100的步骤可以仅延续至接触塞117的形成。
如图2的实例所示,通过根据本发明实施例的方法制造第二衬底200,其具有半导体衬底205、穿透电极207、第一金属线层210、第二金属线层220、第三金属线层230、第四金属线层240、第五金属线层250以及第六金属线层260。
第一、第二、第三、第四、第五以及第六金属线层210至260可以形成用以处理信号的一条或多条布线。尽管图2的实例以示例性实施例的方式示出六个金属线层210至260,但是根据设计要求金属线层的个数可以增加或减少。
在下文中,将描述第二衬底200的制造工艺。首先,可以形成穿透电极,以穿透半导体衬底205。可以通过在半导体衬底205上顺序执行图案化工艺、蚀刻工艺、金属成形工艺以及化学机械抛光(CMP)工艺来形成穿透电极207。
穿透电极207可以由从W、Cu、Al、Ag和Au的组中选取的材料制成。可以通过化学气相沉积(CVD)工艺、物理气相沉积(PVD)工艺、蒸发工艺以及电化学注入(ECP)工艺来沉积穿透电极207。此外,TaN、Ta、TiN、Ti和/或TiSiN可以用作对于穿透电极207的阻挡金属。可以通过CVD工艺、PVD工艺和/或原子层沉积(ALD)工艺来形成该阻挡金属。该穿透电极可以暴露在半导体衬底205的表面上。
在半导体衬底205上形成至少一个金属线层。金属线层使得在半导体衬底205上的金属线层的最低金属线电连接至穿透电极207。可以使用多种金属线层形成方法,例如嵌入工艺。
金属线可以由从W、Cu、Al、Ag和Au组成的组中选取的材料制成。可以通过CVD工艺、PVD工艺、蒸发工艺和/或ECP工艺来沉积金属线。此外,TaN、Ta、TiN、Ti和/或TiSiN可以用作对于金属线的阻挡金属。可以通过CVD工艺、PVD工艺和/或ALD工艺来形成阻挡金属。根据本发明实施例,首先在半导体衬底205上可形成至少一个金属线层,以及可以形成穿透电极207,以穿透半导体衬底205,从而连接至金属线。
如图3所示,在如上所述制造第一衬底100和第二衬底200之后,可将第一衬底100和第二衬底200叠置起来。根据本发明实施例的半导体器件包含:第一衬底100、第二衬底200以及连接电极300。连接电极300可以连接第一衬底100的晶体管与第二衬底200的金属线。连接电极300可以通过第二衬底的穿透电极207电连接至第二衬底200的金属线。连接电极300可以连接至第一衬底100的晶体管。
根据本发明实施例利用系统级封装的半导体器件的制造方法具有下列优点。在根据本发明实施例的制造方法中,可分别单独执行第一衬底制造工艺和第二衬底制造工艺。这可以防止由于在用于金属线层的第二衬底制造工艺中出现错误或故障而引起的具有晶体管层的第一衬底被丢弃的情况。
根据本发明实施例,由于金属线层制造步骤(例如后端(BEOL)工艺)可以与晶体管层制造步骤(例如前端(FEOL)工艺)分开单独执行,因此可以在不受金属层制造工艺的影响的情况下来制造晶体管层。
由于金属线层可以分开单独制造,所以可以选择用于执行热处理的更宽温度范围的工艺。半导体器件及其制造方法可以简化制造工艺并提高产量。
对于本领域技术人员应该明显和清楚的是,可以对本发明所公开的实施例进行各种改变和变化。因此,本发明公开的实施例覆盖各种明显和清楚的改变和变化,前提是这些改变和变化落于所附的权利要求及其相等物的范围之内。
Claims (20)
1.一种装置,该装置包含:
第一半导体衬底,其包含晶体管层,其中该晶体管层包含至少一个晶体管;
第二半导体衬底,其包含金属线层,其中该金属线层包含至少一条金属线;以及
连接电极,其使得所述至少一个晶体管与所述至少一条金属线电连接。
2.如权利要求1所述的装置,其中该第一衬底包含:在该晶体管层上的具有金属线层的半导体器件。
3.如权利要求1所述的装置,其中该第一衬底包含:连接于所述晶体管的接触塞。
4.如权利要求1所述的装置,其中该第二衬底包含:穿透电极,其连接于所述金属线,其中该穿透电极穿透该第二半导体衬底。
5.如权利要求4所述的装置,其中至少一条金属线和该穿透电极包含W、Cu、Al、Ag和Au的至少其中之一。
6.如权利要求4所述的装置,其中该连接电极通过该穿透电极电连接至该第二衬底的金属线。
7.如权利要求4所述的装置,其中该穿透电极暴露在该第二半导体衬底的表面上。
8.如权利要求4所述的装置,其包含由TaN、Ta、TiN、Ti和TiSiN的至少其中之一形成的用于该穿透电极的阻挡金属。
9.如权利要求1所述的装置,其包含由TaN、Ta、TiN、Ti和TiSiN的至少其中之一形成的用于该金属线的阻挡金属。
10.一种方法,其包含下列步骤:
形成第一半导体衬底,其包含晶体管层,其中该晶体管层包含至少一个晶体管;
形成第二半导体衬底,其包含金属线层,其中该金属线层包含至少一条金属线;以及
将该第二半导体衬底叠置于该第一半导体衬底上,其中所述叠置步骤包含将所述至少一个晶体管电连接至所述至少一条金属线。
11.如权利要求10所述的方法,其中通过至少一个连接电极将所述至少一个晶体管电连接至所述至少一条金属线。
12.如权利要求10所述的方法,其中所述形成该第一半导体衬底的步骤包含:在该晶体管层上形成金属线层。
13.如权利要求10所述的方法,其中所述形成该第一半导体衬底的步骤包含:形成接触塞,其连接于所述晶体管。
14.如权利要求10所述的方法,其中所述形成该第二半导体衬底的步骤包含:
形成穿透电极,其穿透该第二半导体衬底;以及
在该第二半导体衬底上形成金属线,该金属线连接至该穿透电极。
15.如权利要求11所述的方法,其中所述形成该第二衬底的步骤包含:
在半导体衬底上形成金属线;以及
形成穿透电极,其穿透该半导体衬底并连接至该金属线。
16.如权利要求15所述的方法,其中通过该穿透电极使得该连接电极电连接于该金属线。
17.如权利要求16所述的方法,其中该穿透电极暴露在该第二半导体衬底的表面上。
18.如权利要求11所述的方法,其中该金属线和该穿透电极包含W、Cu、Al、Ag和Au的至少其中之一。
19.如权利要求14所述的方法,包含:形成用于该穿透电极的阻挡金属,该阻挡金属包含TaN、Ta、TiN、Ti和TiSiN的至少其中之一。
20.如权利要求11所述的方法,包含:使用TaN、Ta、TiN、Ti和TiSiN的至少其中之一形成用于该金属线的阻挡金属。
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