CN101110411A - 半导体封装体及其制造方法 - Google Patents

半导体封装体及其制造方法 Download PDF

Info

Publication number
CN101110411A
CN101110411A CNA2007101275586A CN200710127558A CN101110411A CN 101110411 A CN101110411 A CN 101110411A CN A2007101275586 A CNA2007101275586 A CN A2007101275586A CN 200710127558 A CN200710127558 A CN 200710127558A CN 101110411 A CN101110411 A CN 101110411A
Authority
CN
China
Prior art keywords
wafer
filler
adhesion coating
substrate
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2007101275586A
Other languages
English (en)
Other versions
CN100539129C (zh
Inventor
赵特宗
李明机
林忠毅
张国钦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN101110411A publication Critical patent/CN101110411A/zh
Application granted granted Critical
Publication of CN100539129C publication Critical patent/CN100539129C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/29387—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/29388—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/2939—Base material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Abstract

本发明涉及一种半导体封装体及其制造方法，具体为一种多晶片堆叠型的半导体封装体及其制造方法，包含：将多个堆叠的半导体晶片置于一基板，其中一上晶片的横向周围悬于一下晶片的横向周围外，而形成一凹部；将含有一填充物的一支持粘着层置于上述板上，位于上述下晶片的横向周围旁，并填入上述凹部。上述填充物可包含多个微球体；上述填充物亦可包含空白晶片、有源晶片或无源晶片。本发明所述半导体封装体及其形成方法可减少焊线制程所造成的震动，使得晶片堆叠型封装体中，晶片间的悬空部分能够得到支持。

Description

半导体封装体及其制造方法
本申请是申请日为2005年5月10日、申请号为200510069446.0、发明名称为“半导体封装体及其形成方法”的申请的分案申请。
技术领域
本发明是关于一种半导体封装元件及其制造方法，特别是关于一种含堆叠的半导体晶片的封装体及其制造方法。
背景技术
随着对电子元件的小型化、轻量化及多功能化的需求日渐增加，而导致半导体封装体密度的增加，以缩小其尺寸及组装时所占的面积。为满足上述的需求所发展出的技术中，其中一种便是将多个裸晶或已封装的晶片堆叠在一封装体中，例如美国专利US6,650,019所揭示。
图1为一剖面图，是显示一已知的半导体封装体100，具有堆叠的晶片102与104。封装体100为一球栅阵列(ball gridarray；BGA)封装体，其基板110的下表面形成有多个软焊料球状接点(solder ball；业界通称“锡球”)106，是作为封装体100的I/O接点。封装体100包含传统的互联基板110及固定于其上表面的第一半导体晶片102。第二晶片104则堆叠、固定于第一晶片102的上表面。晶片102与104通常具有多个I/O焊垫112于个别的上表面的边缘周边部。
基板110则包含可挠式的树脂基板、刚性的玻璃纤维-铜箔层积基板、可剥离式的共烧陶瓷(co-fired ceramics)基板、金属导线架或是其它业界通用的基板，视封装体100的封装形式而定。图1所示用于BGA封装体100的互联基板110包含一绝缘层114例如为聚酰亚胺树脂，层积于导电层116与118之间。导电层116与118各包含铜或铝等金属，是分别作为基板110的上表面与下表面。
导电层116与118的图案化通常是使用微影与蚀刻的技术，以定义焊线焊垫120与上层电路116的连接线、及下层电路118的焊垫122。焊垫120与上层电路116的连接线(未绘示)通常经由贯穿绝缘层114的贯穿孔123，例如镀有导电层(未绘示)的贯穿孔，电性连接于软焊料焊垫122。可在导电层116及/或118上涂覆一绝缘的防焊层(未绘示)，上述防焊层具有一开口，曝露焊线焊垫120及/或焊垫122，上述防焊层可防止因软焊料异常的扰动所导致各焊垫120之间或各焊垫122之间的桥接。
在图1中，第一晶片102通常是使用一粘着层124固定于基板110上。第一晶片102并借由多个导电焊线126电性连接于基板110，其中导电焊线126通常为金或铝，连接于晶片102上的焊垫112与基板110上的焊垫120之间。
第二晶片104是以粘着层128固定于第一晶片102的上表面，其水平边缘是大体上位于第一晶片102的中央区域内，并在第一晶片的焊垫112的内侧。如此，粘着层128实质上不会接触或覆盖焊垫112或连接于其上的导电焊线126。粘着层128的位置是使位于第一晶片102上的第二晶片104与连接于焊垫112上的导电焊线126保持适当的距离，避免与其接触，可防止焊垫112与导电焊线126发生短路或受到破坏，并因此定义出位于粘着层128的周围、第一晶片102与第二晶片104之间的周边区域130。第二晶片104可以和第一晶片102一样，以焊线的方式电性连接至基板110。亦可以再增加一或更多的晶片，以相同的手段，依序堆叠于第二晶片104的表面上。
图2为一剖面图，是显示一已知的封装体，其具有两个堆叠的晶片150与152及和上述晶片交错配置的粘着剂154。例如，如果晶片粘着的机台的精确度控制不佳时，较好为引进另一种机制，以精确控制分布于晶片150与152相对表面间的粘着剂154的接合厚度(bond line thickness)。上述机制可借由如图2所示的方式来达成，其使用未硬化而成流体状的粘着剂154，具有一定数量的微球体156，微球体156的直径与所需要的粘着剂154的厚度大体相同。在图2中，是将第二晶片152压至粘着剂154上，使得第二晶片152的下表面接触到微球体156。第二晶片152的下表面与第一晶片150的上表面之间是介有大体上单层的微球体156。
适用于微球体156的材料很广泛，例如玻璃、聚合物、二氧化硅、氮化硅或聚四氟乙烯(polytetrafluorethylene；PTFE)。微球体156的制造方面，可使用许多已知的技术，例如以吸取或吹送的方式，驱动一熔融的材料经过一喷嘴，在高压下散成雾状，然后借由空气、水或油浴，将不同尺寸的球体冷却或硬化。接下来可将微球体156过筛，经过不同尺寸的筛网，依照不同的直径将其分类。
请再参考图1，晶片堆叠型封装体100中，晶片102与104通常是以焊线接合，其是以自动焊线的机台施以已知的热压或超音波的焊线技术而成。如图1所示，在焊线的制程中，晶片102或104上的焊垫112，与其接触的导电焊线126受到来自一焊线机台的焊针132所施以的向下的压应力，使得导电焊线126接合于焊垫112。
因为焊垫112是分别位于晶片102与104的周边区，焊线接合时会使晶片的外围部分承担如图1的箭号方向的局部且较大的应力。对下方的晶片102而言，其受到其下方的基板110与粘着层124的支持，而不会造成问题。然而，对上方的晶片104而言，其是借由粘着层128使其周边的部分悬于晶片104的周边部分之外，而未受到来自下方的支持。因此，上方的晶片104可能会在焊线的过程中崩裂或损坏，而使得整个封装体必须报废。
已知的堆叠技术所可能引发的另一个问题，就是在第一晶片102与第二晶片104之间的悬空区域130，也就是在粘着层128的周边。封胶体134所使用的塑料封装材料会在封装的过程中，包覆第一晶片102与第二晶片104、并进入悬空区域130中，而成为第一晶片102与第二晶片104不安定的因素。当封胶体134的热膨胀系数与粘着层128不同时，在封装体100历经剧烈的温度变化时，第一晶片102与第二晶片104之间的封胶体134会有较大的膨胀量，可能会毁损第一晶片102及/或第二晶片104，而使得整个封装体必须报废。
已知的堆叠技术所可能引发的又另一个问题，就是在第一晶片102与第二晶片104之间的悬空区域130，以及焊针132所施加的应力。换句话说，焊针132所施加的向下的应力，会使第二晶片104发生形变，而导致第二晶片104的下表面与粘着层128的上表面之间的分离或脱层。
已知的堆叠技术所可能引发的又另一个问题，还是在第一晶片102与第二晶片104之间的悬空区域130，以及焊针132所导致的挠曲。导电焊线126或焊垫112本身可能会发生形变，而可能导致两者间的断路。换句话说，在焊线的制程中会反复地使晶片104发生形变与弯曲，会造成整个封装体的震动，而使导电焊线126与焊垫112之间的电性连结受到疲劳破坏。即使在制程中两者间并未因疲劳破坏而断路，仍然会减少元件的使用寿命与可靠度。
发明内容
有鉴于此，本发明的主要目的是提供一种半导体装置、封装体、及其形成方法、与减少焊线制程所造成的震动的方法，使得晶片堆叠型封装体中，晶片间的悬空部分能够得到支持，而克服上述已知技术的缺点。
为达成本发明的上述目的，本发明提供一种将不同尺寸的晶片堆叠在一起的晶片堆叠方法，使两晶片相对的表面相接，而使上晶片水平方向的长度或宽度大于下晶片的水平方向的尺寸。因此，上晶片至少部分的周边部是悬于下晶片的周边部外。本发明的一较佳实施例在上晶片的焊线制程前，对上晶片的周边部提供支持，以避免悬空的周边部在焊线的过程中发生前述的问题。
在另一实施例中，一半导体装置是具有多个堆叠的晶片，连接于一基板。上述晶片以边缘交错的方式相互堆叠，而使一上晶片悬于一下晶片上，而形成一凹部。上述凹部内含有一支撑物，以避免悬空的周边部在焊线的过程中发生前述的问题。
在另一实施例中，是将含有填充物的支持粘着层填入由悬空的上晶片所构成的凹部中。上述支持粘着层围绕下晶片的周围，并位于上晶片悬空的周边部之下。在本发明的一较佳实施例中，可以是多个粘着剂层。
在又另一实施例中，支持粘着层中的填充物为一空白晶片(dum my die)。上述空白晶片的厚度与堆叠在封装体中的其中一晶片的厚度一致。而又在另一实施例中，可使用一被动元件例如电容器、电阻器或电感器，取代上述空白晶片。
本发明的一项优点，在于可适用广泛用于半导体业界的粘着剂与填充物。其中将晶片粘着于基板时，是使用一般的技术；而所使用的球体例如塑料、玻璃、陶瓷、聚合物、无机化合物、环氧树脂、以及其它材料，都是常用于制作均一粒径的球体，并可将其混合使用。
本发明的另一目的为制程简单且成本低廉。几乎不需要修改现有的焊线机台。
本发明是这样实现的：
本发明提供一种半导体封装体，所述半导体封装体包含：一基板；多个堆叠的半导体晶片连接于该基板，该些半导体晶片具有一上晶片与一下晶片，分别具有相反的上表面与下表面，该下晶片的横向周围(lateral periphery)小于该上晶片的横向周围，而使该上晶片的横向周围悬于该下晶片的横向周围外，而形成一凹部；以及一支持粘着层于该下晶片的横向周围旁，并填入该凹部，该支持粘着层含有第一填充物与第二填充物，该第一填充物与第二填充物包含多个微球体。
本发明所述的半导体封装体，该第二填充物的尺寸实质上大于该第一填充物的尺寸。
本发明所述的半导体封装体，该第二填充物高于该凹部高度的30％。
本发明所述的半导体封装体，更包含：一粘着层连接该下晶片的上表面与该上晶片的下表面，该粘着层包含多个间隔物，介于相连的该下晶片的上表面与该上晶片的下表面之间。
本发明所述的半导体封装体，该些间隔物包含一材料，该材料是择自下列所组成的族群：玻璃、金属、陶瓷、二氧化硅、氮化硅、环氧树脂与聚合物。
本发明所述的半导体封装体，该些间隔物包含实质上呈单层排列的微球体。
本发明所述的半导体封装体，该第一填充物与第二填充物包含一材料，该材料是择自下列所组成的族群：玻璃、金属、陶瓷、二氧化硅、氮化硅、环氧树脂与聚合物。
本发明所述的半导体封装体，该下晶片的上表面与该上晶片的下表面的间距小于125μm。
本发明所述的半导体封装体，该第一填充物与第二填充物包含多个大微球体与小微球体，该些大微球体与该些小微球体的直径比为1.1至10。
本发明另提供一种半导体封装体的制造方法，所述半导体封装体的制造方法包含：提供一基板；将多个堆叠的半导体晶片连接于该基板，该些半导体晶片具有一上晶片与一下晶片，分别具有相反的上表面与下表面、及横向周围(lateral periphery)，该下晶片的横向周围小于该上晶片的横向周围，一粘着层连接该下晶片的上表面与该上晶片的下表面，而使该上晶片的横向周围悬于该下晶片的横向周围外，而形成一凹部；以及以一支持粘着层支持于该下晶片的横向周围，该支持粘着层含有第一填充物与第二填充物，该支持粘着层是置于该下晶片的横向周围旁的该基板上，而大体上填满该凹部，该第一填充物与第二填充物包含多个微球体。
本发明所述的半导体封装体的制造方法，该粘着层更包含多个间隔物，介于相接的该下晶片的上表面与该上晶片的下表面。
本发明所述的半导体封装体的制造方法，该些间隔物包含一材料，择自下列所组成的族群：玻璃、金属、陶瓷、二氧化硅、氮化硅、环氧树脂与聚合物。
本发明所述的半导体封装体的制造方法，该些间隔物包含微球体。
本发明所述的半导体封装体的制造方法，该些间隔物包含微球体，大体排列成一单层结构。
本发明所述的半导体封装体的制造方法，该第一填充物与第二填充物包含一材料，择自下列所组成的族群：玻璃、二氧化硅、氮化硅、环氧树脂与聚合物。
本发明所述的半导体封装体的制造方法，介于该下晶片的上表面与该上晶片的上表面之间的堆叠间距(mounting pitch)小于125μm。
本发明所述的半导体封装体的制造方法，该第一填充物与第二填充物包含多个直径比为1.1至10的大微球体与小微球体，该些大微球体的直径大体等于该凹部。
本发明所述的半导体封装体的制造方法，该支持粘着层更包含多个间隔物介于该第一填充物与第二填充物之间。
本发明所述的半导体封装体的制造方法，该些间隔物为微球体。
本发明所述半导体封装体及其形成方法可减少焊线制程所造成的震动，使得晶片堆叠型封装体中，晶片间的悬空部分能够得到支持。
附图说明
图1为一剖面图，显示一已知的晶片堆叠型的封装体；
图2为一剖面图，显示一已知的半导体装置，包含堆叠的两个晶片与含微球体的粘着剂；
图3为一剖面图，显示本发明第一实施例的半导体封装体；
图4为一剖面图，显示本发明第二实施例的一对堆叠的晶片；
图5为一剖面图，显示本发明第三实施例的一对堆叠的晶片；
图6为一剖面图，显示本发明第四实施例的三个堆叠的晶片。
具体实施方式
为了让本发明的上述和其它目的、特征和优点能更明显易懂，下文特举一较佳实施例，并配合所附图示，作详细说明如下：
以下的实施例虽以包含两个堆叠的晶片与一基板的半导体封装体为例，来说明本发明，但不代表本发明就受现在上述应用中，本领域技术人员亦可以将本发明应用在具有两个以上的堆叠晶片的半导体装置中。
请参考图3，为一剖面图，是显示本发明第一实施例中，堆叠在基板184上的上晶片182与下晶片180。上晶片182与下晶片180各具有相反的上、下表面与横向轮廓。上晶片182的横向轮廓是大于下晶片180的横向轮廓，因此上晶片182的至少一个边缘204是悬于下晶片180的至少一个边缘210之外。在本实施例中，上晶片182的周边部是悬于下晶片180之外。可使用一传统的焊线装置200沿着上晶片182上表面的周边，打上焊线202。
图3所示的堆叠晶片封装体是包含一基板184与第一粘着层186，第一粘着层186是贴在下晶片180与基板184的相接处。基板184可为单一材质或包含第一材料与第二材料，两者之一可择自下列所组成的族群：玻璃、金属、陶瓷、聚合物、硅基板、绝缘层覆硅基板(silicon on insulator；SOI)、印刷电路板、与硅锗基板。基板184可包含一导电的连接线形成于其上。基板184可包含多个形成于其下方的导电凸块(bump)或导电针脚(pin)。上晶片182与下晶片180的相接面之间是使用第二粘着层188来接合。第一粘着层186与第二粘着层188较好是含有一填充物，其包含实质上具均一尺寸的一层非导体的微球体196，如此可在基板184与下晶片180的相接面之间、及下晶片180与上晶片182的相接面之间，形成均一的间隔。微球体196较好是排列成一个单层。上述填充物可包含第一材料与第二材料，是择自下列所组成的族群：玻璃、金属、陶瓷、二氧化硅、氮化硅、环氧树脂与聚合物。
决定微球体196的尺寸所考虑的一个因素为封装节距(mounting pitch)。封装节距是为两相邻晶片的上表面间的垂直距离。例如图3中的封装节距为粘着层188与上晶片182的厚度和。封装节距对封装体的微型化而言是项重要的指标，应该愈小愈好，较好为不大于125μm。缩小封装节距包含缩小晶片厚度或缩小粘着剂填充物的尺寸。另一方面，亦可以接受封装节距在125μm至750μm的情形，将封装节距缩小至125μm以下则是目前的趋势。
如图3所示，在一较佳实施例中，上晶片182的悬空的周边部是由三个粘着层190、192、194所支撑。粘着层190、192、194是置于粘着层186、188与下晶片180的外侧，并可以亦围绕粘着层186、188与下晶片180。粘着层190、192、194并连接下晶片180。在一实施例中，粘着层190、192、194的横向延伸范围较好是等于悬空的上晶片182的边缘204。
第一支持粘着层190是包含一层的微球体206，其尺寸是实质上与第一粘着层186的微球体196相等。在一较佳的实施例中，第一粘着层186与第一支持粘着层190各包含一个单层的微球体，其具有实质上相同的尺寸。下晶片180的下表面是置于第一粘着层186的微球体196上。第一支持粘着层190是形成于基板184的表面上，而使其尺寸与第一粘着层186实质上相同。在本实施例中，第一粘着层186与第一支持粘着层190可形成实质上具均匀厚度如图3所示的薄膜。
第二支持粘着层192是置于第一支持粘着层190上，并包含一填充物，其包含一较大的微球体208，其尺寸是实质上等于下晶片180的厚度。
在一较佳实施例中，第二支持粘着层192中较大的微球体208，不一定需要绝对均匀的尺寸，也不一定要成单层的分布；而如图3所示，其混入不同尺寸的填充物。另外，在第二支持粘着层192中加入较小尺寸的填充物198可取代粘着剂来填满较大填充物之间的空隙。在第二支持粘着层192中，较大的微球体与较小的微球体的直径比为1.1至10。在一范例中，填充物的大小是大于凹部高度的30％。
第三支持粘着层194是置于第二支持粘着层192上，并包含一填充物，其尺寸较佳与第一粘着层的微球体196相同。第三支持粘着层194是置于第二支持粘着层192上，而足以实质上填满上晶片182悬空的周边部。
如图3所示，较大的上晶片182是置于下晶片180上，其周边部的至少一部分是悬于下晶片180外，而使得上述堆叠晶片的边缘交错配置。较佳的实施例是使用含填充物的粘着剂，填满由上晶片182悬空的周边部所构成的凹部，而能够使焊线制程稳定。
以有限元素法所建构的计算机模型已证实了上述本发明的实施例的功效。上述的模型是聚焦于堆叠晶片中，悬空的晶片模型所承受的主要应力(principal stress)。上述的模型是显示，上述主要应力是随着悬空的长度增加而增加，或是随着晶片厚度的减少而增加。当上述主要应力超过180Mpa时，会使得悬空的硅晶片毁损。由上述的模型得知，在已知的封装体中，其晶片的悬空部分未受到支撑，当悬空长度为1.75mm且晶片厚度为100μm时，已超出其制程能力。
悬空晶片的失效模式有很多种，但大体上是与悬空晶片的挠曲与震动相关。经由上述实施例的改善后，封装体的失效原因变为金属的空孔、焊线尾部的残留、锡球的形变、晶片的破损、晶片的崩裂、晶片与封胶体之间的空隙、脱层及其它的制程瓶颈。
在本发明的其它实施例中，是以一单一的粘着层取代图3的粘着层190、192、194，其中上述单一的粘着层是含有一填充物，其尺寸实质上与悬空的晶片所造成的凹部相同。另外，亦可以使用含有两种尺寸的填充物的单一粘着层。
在图4所示的第二实施例中，是使用固态的支持构件230取代图3的第二粘着层192。如同前述的实施例，在图4中是具有一基板220、一下晶片222、与一较大的上晶片224。具有微球体228的粘着层226则连接上述元件。在本实施例中，是以晶片形状的填充物230取代图3所示的较大微球体208来作为填充物。本实施例的优点在于填充物230可以是空白晶片、有源晶片(active die)或无源晶片(passive die)，例如电容器、电阻器或电感器。在其它的实施例中，可将小的微球体232置于晶片形状的填充物230与下晶片222中作为间隔物。
图5是显示本发明的第三实施例，其中晶片形状的填充物250的横向轮廓超出支持上晶片悬空的周边部所需的尺寸。在实施时，横向轮廓252可大于或小于上晶片悬空的部分。本实施例可借由调整横向轮廓252的大小，来控制堆叠型封装体的参数，例如信号分布、电源分布或是散热性能。横向轮廓252小于上晶片悬空的部分，留下来的悬空部分较好为小于会在焊线制程时导致失效或其它可靠度问题所需的长度。
图6是显示本发明第四实施例的堆叠型的球栅阵列封装体300，在堆叠在基板上的晶片中，至少有两个晶片具有不同的横向轮廓。
基板312具有一上表面，是典型地适用于堆叠型的球栅阵列封装体300的基板。第一晶片304具有相反的上下表面、一特定的横向宽度、与一边缘322。第一晶片304的下表面是借由第一粘着层314粘着于基板312的上表面，其制程是使用一自动粘晶的机台来完成。
第二晶片302是具有相反的上下表面、一特定的横向宽度、一边缘324、与多个位于上表面周边部的焊垫320。第二晶片302的横向宽度是大于第一晶片304的横向宽度。第二晶片302的下表面是借由第二粘着层316粘着于第一晶片304的上表面。多个细小的导电焊线306提供堆叠型的球栅阵列封装体300内部的电性连接。
如图6所示，晶片304与302的边缘是交错配置，如此第二晶片302的周边部是悬于第一晶片304之外，而使第二晶片302的下表面、第一晶片304的边缘322、与基板312的上表面形成一凹部。本发明的较佳实施例是借由填满上述凹部，来对悬空的边缘部305提供支持。
如图6所示，是使用一支持粘着剂326来填满悬空的周边部305下的凹部。支持粘着剂326是含有一填充物，其具有具特定直径的微球体308。微球体308的直径是足以实质上填满基板312的上表面与第二晶片302的下表面之间的空间。将支持粘着剂326加入第二晶片302悬空的周边部305下的凹部，直到实质上填满上述凹部，而使第二晶片302悬空的周边部305得到来自下方的支持。
用以制造图6所示的封装体300的材料可广泛地自半导体业界取得。例如粘着剂可使用Ablestik公司出品的Ablestik2000B，而Henkel公司所出品的QMI536可分别作为第一粘着层314与第二粘着层316。
如图6所示，本发明的实施例并不限于两个堆叠晶片的情况。在本实施例中，第三晶片310是借由粘着剂318连接在第二晶片302的上表面。而亦可以以另外的多个堆叠的晶片(未绘示)，其具有交错的边缘或悬空的周边部，来取代第三晶片310。本发明并不限于上述实施例所述的特定材料，例如玻璃、陶瓷、金属、聚合物或是其它材料均可适用于上述基板。上述实施例包含未特别列出的，都包含在本发明的范围内。例如可将本发明应用于图1所示的装置；又如本领域技术人员当了解，即使改变堆叠晶片的数量、晶片的悬空量、晶片厚度、材料或方法等，还是落于本发明的范围内。
上述的实施例亦提供一种减少焊线制程所造成的震动的方法，包含：提供一基板；将多个堆叠的半导体晶片连接于上述基板，上述半导体晶片具有一上晶片与一下晶片，分别具有相反的上表面与下表面，一粘着层连接上述下晶片的上表面与上述上晶片的下表面，而使上述上晶片的横向周围悬于上述下晶片的横向周围外，而形成一凹部；以及借由减少晶片厚度或缩小在上述堆叠的晶片之间的填充物尺寸来降低该些堆叠的晶片的高度，其中的封装节距不大于125μm。
半导体晶片堆叠的技术已充分应用于业界中，例如美国专利US6,717,251、US6,680,219、US6,650,019、US6,472,758等专利所揭示。上述的实施例是可以有效地解决：在悬空的晶片周边进行焊线制程时所发生的问题。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
附图中符号的简单说明如下：
100：半导体封装体
102：晶片
104：晶片
106：软焊料球状接点
110：基板
112：I/O焊垫
114：绝缘层
116：导电层
118：导电层
120：焊线焊垫
122：焊垫
123：贯穿孔
124：粘着层
126：导电焊线
128：粘着层
130：周边区域
132：焊针
134：封胶体
150：晶片
152：晶片
154：粘着剂
156：微球体
180：下晶片
182：上晶片
184：基板
186：第一粘着层
188：第二粘着层
190：粘着层
192：粘着层
194：粘着层
196：微球体
198：填充物
200：焊线装置
202：焊线
204：边缘
206：微球体
208：微球体
210：边缘
220：基板
222：下晶片
224：上晶片
226：粘着层
228：微球体
230：晶片形状的填充物
232：微球体
250：填充物
252：横向轮廓
300：堆叠型的球栅阵列封装体
302：第二晶片
304：第一晶片
305：边缘部
306：导电焊线
308：微球体
310：第三晶片
312：基板
314：第一粘着层
316：第二粘着层
318：粘着剂
320：焊垫
322：边缘
324：边缘
326：支持粘着剂。

Claims (4)

1.一种半导体封装体，其特征在于，所述半导体封装体包含：
一基板；
多个堆叠的半导体晶片连接于该基板，该半导体晶片具有一上晶片与一下晶片，分别具有相反的上表面与下表面，该下晶片的横向周围小于该上晶片的横向周围，而使该上晶片的横向周围悬于该下晶片的横向周围外，而形成一凹部；以及
一支持粘着层于该下晶片的横向周围旁，并填入该凹部，该支持粘着层含有第一填充物与第二填充物，该第一填充物与第二填充物中的至少一种是择自下列所组成的族群：  空白晶片、有源晶片、电阻器、电容器、二极管与电感器。
2.根据权利要求1所述的半导体封装体，其特征在于：该第一填充物与第二填充物中的至少一种的横向轮廓超出、小于或等于该上晶片悬于该下晶片之外的范围。
3.一种半导体封装体的制造方法，其特征在于，所述半导体封装体的制造方法包含：
提供一基板；
将多个堆叠的半导体晶片连接于该基板，该半导体晶片具有一上晶片与一下晶片，分别具有相反的上表面与下表面、及横向周围，该下晶片的横向周围小于该上晶片的横向周围，一粘着层连接该下晶片的上表面与该上晶片的下表面，而使该上晶片的横向周围悬于该下晶片的横向周围外，而形成一凹部；以及
以一支持粘着层支持于该下晶片的横向周围，该支持粘着层含有第一填充物与第二填充物，该支持粘着层是置于该下晶片的横向周围旁的该基板上，而填满该凹部，该第一填充物与第二填充物是择自下列所组成的族群：空白晶片、有源晶片、电阻器、电容器、二极管与电感器。
4.根据权利要求3所述的半导体封装体的制造方法，其特征在于：该第一填充物与第二填充物的横向轮廓超出、小于或等于该上晶片悬于该下晶片之外的范围。
CNB2007101275586A 2004-05-10 2005-05-10 半导体封装体及其制造方法 Active CN100539129C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US56969104P 2004-05-10 2004-05-10
US60/569,691 2004-05-10
US10/881,605 2004-06-30

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100694460A Division CN100424871C (zh) 2004-05-10 2005-05-10 半导体封装体及其制造方法

Publications (2)

Publication Number Publication Date
CN101110411A true CN101110411A (zh) 2008-01-23
CN100539129C CN100539129C (zh) 2009-09-09

Family

ID=35476405

Family Applications (2)

Application Number Title Priority Date Filing Date
CNB2007101275586A Active CN100539129C (zh) 2004-05-10 2005-05-10 半导体封装体及其制造方法
CNB2005100694460A Active CN100424871C (zh) 2004-05-10 2005-05-10 半导体封装体及其制造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CNB2005100694460A Active CN100424871C (zh) 2004-05-10 2005-05-10 半导体封装体及其制造方法

Country Status (4)

Country Link
US (1) US7116002B2 (zh)
JP (1) JP2005322887A (zh)
CN (2) CN100539129C (zh)
TW (1) TWI257162B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103871992A (zh) * 2012-12-17 2014-06-18 爱思开海力士有限公司 制造芯片封装的方法和装置
CN108701675A (zh) * 2016-02-29 2018-10-23 英帆萨斯公司 用于晶圆/晶粒堆叠的修正晶粒

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4343049B2 (ja) * 2004-07-13 2009-10-14 富士通株式会社 ハードディスクドライブのキャリッジアセンブリ
KR100593703B1 (ko) * 2004-12-10 2006-06-30 삼성전자주식회사 돌출부 와이어 본딩 구조 보강용 더미 칩을 포함하는반도체 칩 적층 패키지
US20070109756A1 (en) * 2005-02-10 2007-05-17 Stats Chippac Ltd. Stacked integrated circuits package system
US7365417B2 (en) * 2006-01-06 2008-04-29 Stats Chippac Ltd. Overhang integrated circuit package system
US8629537B2 (en) * 2006-01-23 2014-01-14 Stats Chippac Ltd. Padless die support integrated circuit package system
US7449369B2 (en) * 2006-01-23 2008-11-11 Stats Chippac Ltd. Integrated circuit package system with multiple molding
KR100764682B1 (ko) * 2006-02-14 2007-10-08 인티그런트 테크놀로지즈(주) 집적회로 칩 및 패키지.
JP4954569B2 (ja) * 2006-02-16 2012-06-20 日東電工株式会社 半導体装置の製造方法
TWI339436B (en) * 2006-05-30 2011-03-21 Advanced Semiconductor Eng Stackable semiconductor package
TWI298198B (en) * 2006-05-30 2008-06-21 Advanced Semiconductor Eng Stackable semiconductor package
US20080042265A1 (en) * 2006-08-15 2008-02-21 Merilo Leo A Chip scale module package in bga semiconductor package
TWI317993B (en) 2006-08-18 2009-12-01 Advanced Semiconductor Eng Stackable semiconductor package
JP5166716B2 (ja) * 2006-09-26 2013-03-21 積水化学工業株式会社 半導体チップ積層体及びその製造方法
US7772683B2 (en) * 2006-12-09 2010-08-10 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7635913B2 (en) * 2006-12-09 2009-12-22 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US8304874B2 (en) * 2006-12-09 2012-11-06 Stats Chippac Ltd. Stackable integrated circuit package system
TWI324817B (en) * 2006-12-20 2010-05-11 Advanced Semiconductor Eng Multiple chip package
SG148054A1 (en) * 2007-05-17 2008-12-31 Micron Technology Inc Semiconductor packages and method for fabricating semiconductor packages with discrete components
US8956914B2 (en) * 2007-06-26 2015-02-17 Stats Chippac Ltd. Integrated circuit package system with overhang die
US20090032926A1 (en) * 2007-07-31 2009-02-05 Advanced Micro Devices, Inc. Integrated Support Structure for Stacked Semiconductors With Overhang
TW200952149A (en) * 2008-06-02 2009-12-16 Kun Yuan Technology Co Ltd Stack structure of integrated circuit with caulking element
JP2010040835A (ja) * 2008-08-06 2010-02-18 Toshiba Corp 積層型半導体装置の製造方法
US20110193243A1 (en) * 2010-02-10 2011-08-11 Qualcomm Incorporated Unique Package Structure
US8436452B2 (en) * 2010-05-28 2013-05-07 Nanya Technology Corporation Carrier for chip packages
KR20110133945A (ko) * 2010-06-08 2011-12-14 삼성전자주식회사 스택 패키지 및 그의 제조 방법
JP5979565B2 (ja) * 2012-04-11 2016-08-24 パナソニックＩｐマネジメント株式会社 半導体装置
US20150221570A1 (en) * 2014-02-04 2015-08-06 Amkor Technology, Inc. Thin sandwich embedded package
JP6483498B2 (ja) * 2014-07-07 2019-03-13 ローム株式会社 電子装置およびその実装構造
TWI582916B (zh) * 2015-04-27 2017-05-11 南茂科技股份有限公司 多晶片封裝結構、晶圓級晶片封裝結構及其製程
US9947642B2 (en) 2015-10-02 2018-04-17 Qualcomm Incorporated Package-on-Package (PoP) device comprising a gap controller between integrated circuit (IC) packages
US10163871B2 (en) 2015-10-02 2018-12-25 Qualcomm Incorporated Integrated device comprising embedded package on package (PoP) device
KR102647175B1 (ko) 2016-12-13 2024-03-14 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
CN110235039A (zh) 2017-01-06 2019-09-13 洛克利光子有限公司 Asic与硅光子器件的共同封装
US10877217B2 (en) 2017-01-06 2020-12-29 Rockley Photonics Limited Copackaging of asic and silicon photonics
EP3662311A1 (en) 2017-08-01 2020-06-10 Rockley Photonics Limited Module with transmit optical subassembly and receive optical subassembly
US10629539B2 (en) * 2017-11-07 2020-04-21 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of fabricating the same
US11145575B2 (en) 2018-11-07 2021-10-12 UTAC Headquarters Pte. Ltd. Conductive bonding layer with spacers between a package substrate and chip
US20220093568A1 (en) * 2019-02-22 2022-03-24 Intel Corporation Film in substrate for releasing z stack-up constraint

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2596960B2 (ja) * 1988-03-07 1997-04-02 シャープ株式会社 接続構造
WO1996037913A1 (en) * 1995-05-22 1996-11-28 Hitachi Chemical Company, Ltd. Semiconductor device having a semiconductor chip electrically connected to a wiring substrate
US6054337A (en) * 1996-12-13 2000-04-25 Tessera, Inc. Method of making a compliant multichip package
US6087200A (en) * 1998-08-13 2000-07-11 Clear Logic, Inc. Using microspheres as a stress buffer for integrated circuit prototypes
CN1145211C (zh) * 1998-09-21 2004-04-07 大众电脑股份有限公司 一种多晶片半导体封装结构
JP3565319B2 (ja) * 1999-04-14 2004-09-15 シャープ株式会社 半導体装置及びその製造方法
KR100533673B1 (ko) * 1999-09-03 2005-12-05 세이코 엡슨 가부시키가이샤 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기
JP2001320014A (ja) * 2000-05-11 2001-11-16 Seiko Epson Corp 半導体装置及びその製造方法
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
JP2002176137A (ja) 2000-09-28 2002-06-21 Toshiba Corp 積層型半導体デバイス
US6680219B2 (en) 2001-08-17 2004-01-20 Qualcomm Incorporated Method and apparatus for die stacking
JP4123027B2 (ja) * 2003-03-31 2008-07-23 セイコーエプソン株式会社 半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103871992A (zh) * 2012-12-17 2014-06-18 爱思开海力士有限公司 制造芯片封装的方法和装置
CN108701675A (zh) * 2016-02-29 2018-10-23 英帆萨斯公司 用于晶圆/晶粒堆叠的修正晶粒

Also Published As

Publication number Publication date
JP2005322887A (ja) 2005-11-17
US7116002B2 (en) 2006-10-03
TWI257162B (en) 2006-06-21
US20050248019A1 (en) 2005-11-10
CN1700466A (zh) 2005-11-23
CN100424871C (zh) 2008-10-08
TW200537670A (en) 2005-11-16
CN100539129C (zh) 2009-09-09

Similar Documents

Publication Publication Date Title
CN100539129C (zh) 半导体封装体及其制造方法
US6965168B2 (en) Micro-machined semiconductor package
US7723839B2 (en) Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device
JP4188337B2 (ja) 積層型電子部品の製造方法
US7005743B2 (en) Semiconductor device using bumps, method for fabricating same, and method for forming bumps
KR100630741B1 (ko) 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법
KR101171842B1 (ko) 초미세 피치의 적층을 갖는 마이크로전자 조립체
US8987053B2 (en) Semiconductor package including flip chip controller at bottom of die stack
US6479321B2 (en) One-step semiconductor stack packaging method
TWI499017B (zh) 用於懸垂晶粒之環氧基凸塊
KR20080020069A (ko) 반도체 패키지 및 그 제조방법
EP1538669B1 (en) Thin package for stacking integrated circuits
US7497911B2 (en) Flip chip die assembly using thin flexible substrates
CN103946976A (zh) 具有翻转式球接合表面的双层级引线框架及装置封装
US7588963B2 (en) Method of forming overhang support for a stacked semiconductor device
KR100432867B1 (ko) 반도체장치,반도체장치용탭테이프,탭테이프제조방법및반도체장치제조방법
CN103367265B (zh) 多层半导体装置、印刷电路板和多层半导体装置制造方法
JP2007116030A (ja) 半導体装置とそれを用いた半導体パッケージ
KR100772103B1 (ko) 적층형 패키지 및 그 제조 방법
KR20050028313A (ko) 웨이퍼 레벨 ｃｓｐ의 제조방법
CN100514615C (zh) 具应力缓冲的微连凸块结构的制造方法
CN101452901A (zh) 具应力缓冲的微连凸块结构及制造方法
JP2007081127A (ja) 半導体装置及び半導体装置の製造方法
JP2005317862A (ja) 半導体素子の接続構造
TW201334151A (zh) 多晶粒封裝之黏著／間隙壁結構

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant