CN101103449A - 将半导体封装连接到印刷线路板上的方法 - Google Patents

将半导体封装连接到印刷线路板上的方法 Download PDF

Info

Publication number
CN101103449A
CN101103449A CNA2005800382096A CN200580038209A CN101103449A CN 101103449 A CN101103449 A CN 101103449A CN A2005800382096 A CNA2005800382096 A CN A2005800382096A CN 200580038209 A CN200580038209 A CN 200580038209A CN 101103449 A CN101103449 A CN 101103449A
Authority
CN
China
Prior art keywords
adhesive film
bump
metal bump
array package
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2005800382096A
Other languages
English (en)
Other versions
CN100550329C (zh
Inventor
川手恒一郎
佐藤义明
门间美和
川手良尚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3M Innovative Properties Co
Original Assignee
3M Innovative Properties Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3M Innovative Properties Co filed Critical 3M Innovative Properties Co
Publication of CN101103449A publication Critical patent/CN101103449A/zh
Application granted granted Critical
Publication of CN100550329C publication Critical patent/CN100550329C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0613Square or rectangular array
    • H01L2224/06134Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01011Sodium [Na]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/1579Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10977Encapsulated connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0278Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305Affixing by adhesive
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

一种将凸起阵列封装电连接到线路板上的方法,包括如下步骤:将热流态化、热固化粘结膜布置在具有多个金属凸起的凸起阵列封装的表面上;形成凸起阵列封装,该凸起阵列封装具有包括所述金属凸起和所述粘结膜的平面,并且通过在线路板上布置包括所述金属凸起和所述粘结膜的平面,然后在高到足以完成所述粘结膜的凝固并且高于所述焊料的熔点温度的温度下加热该粘结膜,从而将该凸起阵列封装连接到线路板上。

Description

将半导体封装连接到印刷线路板上的方法
技术领域
本发明涉将半导体封装连接到印刷线路板上的方法。
背景技术
区域凸起阵列封装例如具有半导体芯片的输入/输出端子作为以二维方式排列的金属凸起的球形网格阵列(BGA)或者芯片刻度封装(CSP)或者凸状晶片,在降低半导体装置的尺寸方面非常有效并且现在已经在许多半导体封装中使用。
当区域凸起阵列封装与印刷线路板连接时,在凸起连接部分上因为印刷线路板和封装之间的热膨胀系数不同而产生热应力效果。热应力经常破坏电连接,因此损坏连接的可靠性。为了避免这个问题,在半导体封装和印刷线路板之间的凸起连接部分上形成的间隙中填满未充满材料(under-filling material)。迄今为止,在金属凸起(例如焊球)连接到线路板上之后,在半导体封装和基板之间使用利用毛细现象注入液体树脂型未注满材料(该方法称为“后注入”)。
半导体封装已经实现了非常小的尺寸来满足高密度制造电子设备的需要,并且提供了增大数量的输入/输出端子来满足功能的增加。结果,凸起之间的距离必须减小,并且凸起的直径已经相应地减小了。因此,半导体封装和线路板之间的间隙变得很窄,因此变得难以注入液体型树脂。从高度集成的观点出发,因此,变得有必要在安装在印刷线路板上的半导体封装附近安装其他部件,这导致更加难以注入液体树脂。
在这种情况下,已经设计出先注入未充满技术在连接凸起之前导入密封树脂。专利文献1(美国专利No.6624216)和专利文献2(美国专利No.5128746)提出包含助熔剂组分的未充满粘结剂。然而在这种情况下,难以保持助熔剂所需要的性质和密封材料所需要的性质,并且认为与液体树脂的后注入得到的性质相比,先注入未充满粘结剂的性质受到破坏。先注入未充满粘结剂通常包括强酸例如酸酐。酸组分的残余物导致固化材料的电绝缘性质恶化。例如,作为酸残余物恶化电绝缘性质的结果,可以发生离子迁移。
专利文献3(美国专利No.6297560)和专利文献4(美国专利No.6228678)提出了如下方法,其中在形成焊球之前涂覆密封树脂,通过蚀刻或者激光加工除去半导体芯片的输入/输出端子部分来对树脂进行穿孔,然后将浆料导入孔中并且在回流步骤中熔化使得作为焊球连接在线路板上。这种方法适于在晶片级上加工成芯片,但是不能应用于包含单个芯片的封装。
专利文献5(美国专利No.6265776)公开另一种方法,其中将助熔剂用到焊球中,然后在其上涂覆未充满粘结剂使其连接到线路板上。由于具有低表面能的助熔剂存在于焊球末端,所以驱散了未充满粘结剂。也就是说,未充满剂存在于焊球的末端,并且仅其周边被粘结剂树脂密封。根据这种技术,为了使未充满粘结剂没有粘附到焊球的末端,未充满剂必须作为溶解在溶剂中的树脂溶液使用并且必须干燥,这使得工艺复杂。而且,焊球的末端被升高并且在连接时在线路板与封装上的焊球末端接触时,可能在线路板和封装之间产生间隙,这难以将未充满粘结剂填充到足够多的程度。
专利文献6(日本公开(Kokai)No.2003-243447)公开了一种通过将尖锐凸起的电极经由热固粘结剂层压入到线路板上然后热固,使半导体元件电连接到线路板上的方法。根据这种方法,电极必须是具有尖锐末端的凸起,以在压制时维持半导体元件侧面上的电极和线路板侧面上的焊盘之间的可靠电连接。在这种情况下,在连接的时候在将线路板和半导体元件上的凸起电极接触时,也可能在线路板和半导体元件之间产生间隙,这难以将未充满粘结剂填充到足够多的程度。
附图说明
图1是说明本发明的方法的步骤视图;
图2是凸起阵列封装的底视图;
图3是实施例中使用的电路的视图。
具体实施方式
因此本发明的目的是提供一种将半导体封装连接到印刷线路板上的方法,在连接方面保持可靠性并且需要简易的操作。
本发明的另一个目的是提供一种具有热固粘结膜的半导体封装,可以在上述电连接方法中使用。
根据本方面的一个方面,提供一种将凸起封装连接到线路板上的方法,包括如下步骤:
将热流态化、热固化粘结膜布置在具有多个金属凸起的凸起阵列封装的表面上;形成凸起阵列封装,该凸起阵列封装具有包括所述金属凸起和所述粘结膜的平面,以及
通过将包括所述金属凸起和所述粘结膜的平面布置在线路板上,并且在高到足以完成所述粘结膜的凝固并且高于所述固体的熔点温度的温度下,加热该粘结膜,从而将该凸起阵列连接到线路板上。
根据这种方法的更加具体的实施方案,如上所述提供一种将半导体封装连接到线路板上的方法,该凸起阵列封装在平面上具有多个金属凸起作为半导体芯片的输入/输出端子,包括如下步骤:
将热流态化、热固化粘结膜排列在具有多个金属凸起的凸起阵列封装的表面上;形成凸起阵列封装,该凸起阵列封装具有包括所述金属凸起和所述粘结膜的平面,其中在温度高到足以使所述粘结膜流态化但是没有高到完成所述粘结膜的凝固并且低于所述金属凸起的熔化温度的温度下,用具有扁平表面的板压制所述粘结膜,使所述金属凸起的末端部分地变平并且在表面上暴露出来;以及
通过将包括所述金属凸起和所述粘结膜的平面布置在线路板上,并且在高到足以完成所述粘结膜的凝固并且高于所述金属凸起的熔点温度的温度下,加热该粘结膜,从而将该凸起阵列连接到线路板上。
根据本方面的另一个方面,提供一种具有粘结膜的凸起阵列封装,其中金属凸起的末端被部分地压平并且暴露在表面上,由此具有包括所述金属凸起和所述粘结膜的平面。
根据更具体的实施方案,提供一种如上所述的具有粘结膜的凸起阵列封装,其中金属凸起的末端被部分地压平并且暴露在表面上,由此具有包括所述金属凸起和所述粘结膜的平面,该平面通过制备在平面上具有多个金属凸起作为半导体芯片输入/输出端子的凸起阵列封装,在具有金属凸起的所述凸起阵列封装的表面上布置热流态化、热固化粘结膜,并且在温度高到足以使所述粘结膜流态化但是没有高到完成所述粘结膜的凝固并且该温度低于所述金属凸起的熔化温度的温度下,用具有扁平表面的板压制所述粘结膜而获得。其中金属凸起包括焊料凸起、金凸起、铜凸起。
根据本发明的其他方面,提供一种金凸起半导体芯片。
与利用毛细现象使用液体树脂的方法不同,本发明的方法可以有效且有效率地将高密度集成的凸起阵列封装电连接到线路板上。
本发明的方法是干法而不使用溶剂。因此,不需要用于除去溶剂的步骤并且不存在封装受到溶剂污染的问题。
此外,由于粘结膜中不包含助熔剂,所以可以在将常规的助熔剂涂覆到线路板上之后进行连接步骤。
本发明的方法不需要精细加工例如激光加工,并且甚至可以容易地用于包括单个芯片的封装。
此外,在本发明的方法中,将粘结膜布置在凸起阵列封装的金属凸起表面上,然后对粘结膜进行加热并且压制使其流态化,从而得到使金属凸起暴露出来的平面。由于得到的表面是平的,所以可以实现与线路板的接触没有间隙。因此,在连接的下一个步骤中,在粘结膜的树脂被充分地填充的状态下实现安装以及熔化焊料。
现在对本发明的优选实施方案进行说明,但是这决不是限制本发明。
首先,结合附图对本发明进行说明。图1是说明将凸起阵列封装电连接到线路板上的方法的步骤视图。“凸起阵列封装”是在平面上具有多个金属凸起作为半导体芯片的输入/输出端子的半导体封装。准确地说,可以列举的有区域凸起阵列封装,例如球形网格阵列(BGA)、芯片刻度封装(CSP)和晶片级CSP、凸状晶片。这些凸起可以通过回流法或者电镀法或者引线结合法形成。凸起阵列封装1在其表面上具有金属凸起2,金属凸起2通常具有球形曲面。将热流态化、热固化粘结膜3布置在封装1的金属凸起2的侧面(图1(a)),并且此后通过具有平面的加热板4加热以及压制,使其流态化并且在金属凸起2的周围流动,使得金属凸起2的末端以扁平的状态暴露。由此得到具有粘结膜3的封装1,并且封装1具有包括粘结膜3和金属凸起2暴露出来的表面的平面(图1(b))。上述过程可以通过下述步骤实现。通常地,粘结膜设置在凸起阵列封装的金属凸起上,粘结膜由可剥离膜例如聚四氟乙烯(PTFE)膜或者经过硅酮处理的聚酯膜覆盖,然后对该膜施加升高的温度和压力。
加热板4加热的温度高到足以使粘结膜4流态化但是没有高到足以完成粘结膜3的凝固,而且低于金属凸起的熔化温度。
压制的压力大到足以使平金属凸起2的末端扁平并且暴露在表面上。上述温度和压力由所选择的粘结膜3的树脂组分和金属凸起的熔点确定,并且不限制。在本发明的方法中,通常,希望使用包含流态化温度为60到170℃并且凝固温度为170到260℃的树脂组分的粘结膜,并且希望使用熔点为180到300℃的焊料。优选地在这种情况下,加热温度在大约100到大约180℃,加热时间在1到10秒,并且压制压力为5到100N/cm2
“流态化温度”是聚合物树脂的粘度变成小于10000Pa·S的温度,并且粘度可以使用平板型粘度计(塑度计)或者粘度测量机测量,以及“凝固温度”是在60分钟内热固聚合物的热固反应进行大于50%的温度,并且可以通过使用粘度测量机或者差示扫描量热仪(DSC)测量。这里,词语“温度不足以完成凝固”,一般是指温度低于凝固温度。即使在温度高于凝固温度的时候,如果仅仅加热短时间也仅仅部分地发生凝固。因此,上述定义的温度包括在高于凝固温度的温度下短时间加热。
接下来,将具有粘结膜3的封装1中包括金属凸起2和粘结膜3的平面布置在线路板上(图1(c)),并且在高到足以完成粘结膜3的凝固并且高于金属凸起的熔化温度的温度下加热,从而将凸起阵列封装连接到线路板上(图1(d))。线路板通常是印刷线路板,并且具有通常在树脂基板例如玻璃环氧树脂基板上形成的铜线。还可以使用双马来酰亚胺三嗪树脂(BT树脂)的树脂板、聚酰亚胺芳族聚酰胺基树脂基板作为基板。用于将凸起阵列封装连接到线路板上的温度取决于所选择的粘结膜的树脂组分和焊料熔点,并且不限制。在本发明的方法中使用上述粘结膜和焊料时,加热温度在大约180到280℃并且加热时间在30到300秒以顺利完成连接。在该步骤中,粘结膜中的树脂组分延展开并且焊料熔化,由此熔融的焊料因粘结剂的热膨胀而被挤压出来并且连接在线路板上的布线上。在将具有粘结膜3的封装1布置在线路板5上之前,为了通过焊接促进连接,希望在要与线路板5连接到部分上涂覆助熔剂。迄今为止助熔剂在本技术领域中被广泛使用。在将具有粘结膜3的封装1布置在线路板5上之后,线路板5通过回流炉在上述温度下加热,从而完成连接步骤。
当在本发明的方法中使用上述粘结膜和金凸起时,凸起芯片优选热压在印刷电路板上,从而在凸起和PCB上的电路之间获得冶金接合或者物理接触。在连接点上实施超声波振动有益于加强内部连接。
本发明的方法使用加热到一定温度时流态化并且进一步加热到一定温度时固化的包含热流态化、热固化树脂(此后也称作“热固化树脂”)的粘结膜(此后也称作“热固化粘结膜”或者“粘结膜”)。上述热固化树脂包括热塑性组分和热固化组分。热塑性组分和热固化组分可以存在于同一种聚合物化合物中或者可以是热塑化树脂和热固化树脂的混合物。作为这种情况的例子,在热塑性组分和热固化组分存在于同一种聚合物化合物中的情况下,可以列举被热塑性组分改性的环氧树脂,例如聚己酸内酯改性环氧树脂、橡胶改性环氧树脂。其他例子包括在热塑性树脂的基本结构上具有热固化基团的共聚物树脂。作为上述共聚物树脂,可以列举例如乙烯和(甲基)丙烯酸缩水甘油酯的共聚物。包含热塑性组分和热固化组分的树脂可以单独使用,也可以与其他热塑性组分和/或热固化组分混合使用。例如,在己内酯改性环氧树脂的情况下,如果己内酯的分子量大,则不需要与其他热塑性树脂一起使用而单独使用,因为能够获得足够的流动性。另一方面,如果己内酯的分子量小,则将该树脂与其他热塑性树脂一起使用是有益的。树脂的组分应当由本领域技术人员适当地确定。
对于用于粘结膜来说是特别有利的粘性组分是包含己内酯改性环氧树脂的热固化粘性组分。
上述热固化粘性组分通常具有晶相。特别地,晶相包含己内酯改性环氧树脂(此后也称作“改性环氧树脂”)作为主要成分。改性环氧树脂赋予热固化粘性组分适当程度的柔韧性,以提高热固化粘结剂的黏弹性质。结果,热固化粘结剂甚至在固化之前就显示出了粘结力,并且受热显示出粘附力。此外,与普通环氧树脂一样,在加热赋予热固化粘结剂粘附力的时候,改性环氧树脂形成固化具有三维网格结构的主体。
从提高初始粘附力的观点来看,改性环氧树脂通常具有大约100到大约9000的环氧当量,优选大约200到大约5000,并且更优选大约500到3000。具有上述环氧当量的改性环氧树脂已经由Daicel ChemicalCo.,Ltd以商品标识PLUXCEL G series投放到市场中了。
热固化粘性组分优选包含三聚氰胺/异氰尿酸加合物(此后也称作“三聚氰胺/异氰尿酸络合物”)和上述改性环氧树脂。可使用的三聚氰胺/异氰尿酸络合物已经由例如Nissan Kagaku Kogyo Co.,以商品名MC-600投放市场,并且在使热固化粘性组分变坚韧方面、在热固化之前降低热固化粘性组分的缝隙方面以及在抑制热固化粘性组分的吸湿性质和流动性方面是有效的。可替换的,在焊接工艺中,这种组分对于调整粘结剂的粘度是有效的,在焊接工艺中对增大粘结剂的粘度特别有效。如果粘结剂的粘度太小,粘结剂会从芯片区域中展开。另一方面,如果粘结剂的粘度太大,它会破坏焊接工艺。因此,应当严格控制粘结剂的粘度并且上述组分用作粘度控制剂。为了阻止热固后的脆性而不削弱上述效果,热固化粘结组分可以每100重量份的改性环氧树脂包含通常1到200重量份的三聚氰胺/异氰尿酸络合物,优选2至100重量份,更优选3到50重量份。
热固化粘性组分还可以包括与苯氧基树脂相结合或与其独立的第二环氧树脂(此后也简称为“环氧树脂”)。不特别限制第二氧化树脂,只要它不脱离本发明的范围就可以,并且可以是使用的双酚A环氧树脂、双酚F环氧树脂、双酚A缩水甘油醚环氧树脂、苯酚酚醛清漆环氧树脂、甲酚酚醛清漆环氧树脂、芴环氧树脂、缩水甘油胺树脂(glycidylamine resin)、脂肪族环氧树脂、溴化环氧树脂和氟化环氧树脂。与改性环氧树脂一样,上述环氧树脂与苯氧基树脂相容,并且很少从热固化粘性组分中渗出。特别地,在热固化组分在每100重量份的改性环氧树脂中优选包含50到200重量份的第二环氧树脂,更优选60到140重量份时,有利地改善了耐热性。
在本发明的实施方案中,特别地,双酚A缩水甘油醚环氧树脂(此后也称作“缩水甘油醚环氧树脂”)可以优选用作第二环氧树脂。缩水甘油醚环氧树脂是液体并且用于改善热固化粘性组分的高温性质。例如,缩水甘油醚环氧树脂的使用可以改善依赖于高温固化的耐化学药品性,以及改善玻璃转化温度。此外,凝固(固化)剂可以广泛地选择并且凝固条件变得相对适度。上述缩水甘油醚环氧树脂已经由DOW Chemical(Japan)Co.,以商品名D.E.R.332投放市场了。另一个优选的第二环氧树脂是可以从市场上购买到的来自Tohto Chemical Ltd.的YD128。
如果需要,将凝固剂添加到热固化粘性组分中,使得改性环氧树脂和第二环氧树脂参与凝固反应。不特别限制凝固剂的数量和种类,只要它显示出所需要的效果即可。然而,从改善耐热性的观点出发,凝固剂的含量为每100重量份的改性环氧树脂和所需要的第二环氧树脂中包含1到50重量份,优选2到40重量份,更优选5到30重量份。虽然不局限于下面列出的那些,但是可以使用的凝固剂的例子包括胺凝固剂、酸酐、双氰胺、阳离子聚合催化剂、咪唑化合物、联氨化合物、苯酚等。特别地,双氰胺是所期望的在室温下具有热稳定性的凝固剂。还希望使用脂环族聚胺或者聚酰胺、酰胺胺或其改性产物用于缩水甘油醚环氧树脂。
基于粘结膜的总量,通过添加35到100%的有机颗粒,包括上述热固化粘结组分的粘结膜显示出下述效果。在添加有机颗粒时该树脂显示出塑料流动性。当金属凸起被相对高的压力推压时,具有上述性质的树脂流态化,能够使金属凸起穿透过以致于暴露在表面中。另一方面,有机颗粒抑制了热固化粘性组分的过度流动性,并且防止了热固化粘性组分在使用加热板使金属凸起暴露出来的步骤中流出来。此外,在连接到线路板上的步骤中,在加热过程可以使附着在线路板上的水蒸发而产生水蒸汽压。在这种情况下,树脂太流态化以致于不能夹住气泡。
此外,添加的有机颗粒是丙烯酸树脂、苯乙烯/丁二烯树脂、苯乙烯/丁二烯/丙烯酸树脂、三聚氰胺树脂、三聚氰胺/异氰尿酸酯加合物、聚酰亚胺、硅酮树脂、聚醚酰亚胺、聚醚砜、聚酯、聚碳酸酯、聚醚醚酮、聚苯并咪唑、液晶聚合物、烯烃树脂或者乙烯/丙烯酸共聚物,并且它们的尺寸不大于10μm,优选不大于5μm。
粘结膜可以包括无机填充物例如硅、氧化铝和玻璃珠。无机填充物抑制了凝固后粘结膜的热膨胀系数,这可以避免切线部分中的热应力。
希望粘结膜的厚度小于金属凸起的高度。这是因为如果粘结膜和凸起阵列封装被热压粘附在一起,金属凸起穿透过粘结膜,并且得到处于如下状态的具有粘结膜的封装:焊球的末端以扁平的方式暴露出来。虽然这不是强加任何限制,但是希望金属凸起的高度一般为50到1000μm并且粘结膜的厚度为25到500μm与其相应。粘结膜的厚度和金属凸起的高度的比率优选为0.3到0.8。
如上所述,金属凸起通常为高度为50到1000μm的球形或者高度为50到1000μm的圆锥形。希望将凸起压扁到原始高度的50到90%以部分地压平凸起的末端,即,凸起在平行于凸起高度的方向上变形10到50%。在这些范围内,熔融焊料在连接步骤中因粘结膜的膨胀而被挤压出来,并且顺利地完成连接。
[实施例]
现在通过实施例对本发明的方法进行说明。
凸起阵列封装和线路板
使用从Top.Line Co.购买的球形网格阵列(BGA)作为凸起阵列封装。图2为其底视图。BGA为包括聚酰亚胺(PI)内插物的半导体封装,测得尺寸为8×8mm,排列的焊球保持0.5mm的间距并且球高为0.31mm(锡/铅焊料),焊球沿着外周边排列成14×14并且沿着内周边排列成12×12。
使用其上具有导电图案的玻璃环氧树脂基板(厚度:0.5mm)作为线路板,其中该玻璃环氧树脂基板上具有与凸起阵列封装上的焊球间距相对应的间距。
粘结膜
制备表1中所示组分的粘结树脂溶液,通过刮刀涂覆施加到经过硅酮处理的聚对苯二甲酸乙二醇酯(PET)膜上,然后在烘箱中100℃加热干燥20分钟得到厚度为25μm的薄膜。再将同样的操作重复五次。在120℃将六片得到的薄膜叠压形成厚度为50μm的粘结膜。
表1
    组分     重量份
    YP50S     30
    YD128     34
    G402     30
    BAFL     16.4
    MC600     20
    EXL2314     80
    THF     600
苯氧基树脂:YP50S,Tohto Chemical,平均分子量11800
环氧树脂:YD128,Tohto Chemical,环氧当量=184-194
聚己内酯改性环氧树脂:G402,Daicel Chemical Co.Ltd.环氧当量1350
双苯胺芴:BAFL,Nippon Steel Chemical Co.,Ltd
丙烯酸颗粒:EXL2314,KUREHA PARALOID EXL KurehaChemical,Co.,Ltd
三聚氰胺异氰尿酸络合物:MC-600 Nissan Chemical Industries,Ltd
THF:四氢呋喃
使具有焊球的凸起阵列封装的表面朝上,将上述粘结膜布置在焊球上,并且通过负载为50N的脉冲热量接合器(由Nihon Abionics Co.制造的TCW-215/NA-66(商品名))的感热头经由硅酮处理的厚度为50μm的PET压制上述粘结膜将其热压粘结到焊球。使感热头的温度在两秒钟内从室温升高到130℃,并且在该温度保持一秒钟。此后,在一秒钟之内将温度升高到160℃,在该温度保持三秒钟。结果,得到具有如图1(b)中所示的横截面并且具有粘结膜的凸起阵列封装,图1(b)中焊球完全穿透过粘结膜并且具有扁平的末端。
将助熔剂(Deltalus 523H(商品名),由Senju Kinzoku Kogyo Co.制造)涂覆在线路板的连接部分上,该线路板具有与焊球间距相对应的导电图案,并且具有粘结膜的凸起阵列封装以如下方式重叠在其上:粘结膜与线路板的导电图案的连接部分一致。该组件在总计180秒钟内通过焊接回流炉(在预热区域中150℃,最大温度为240℃),从而实现焊接。
在图3中示出的四个位置A到D上实现与电路T1和T2连接的电连接。因此,在上述实施例中形成了24个连接T1和T2的电路。在焊接回流之后,测量线路板上的端子T1和T2之间的电阻,并且确认24个电路都已经连接。将该样品在-40和80℃之间进行热循环(每个温度30分钟)1000次,发现电阻的增大不大于5%。

Claims (10)

1.一种将凸起阵列封装电连接到线路板上的方法,包括如下步骤:
将热流态化、热固化粘结膜布置在具有金属凸起的凸起阵列封装的表面上;形成凸起阵列封装,该凸起阵列封装具有包括所述金属凸起和所述粘结膜的平面,以及
通过将包括所述金属凸起和所述粘结膜的平面布置在线路板上,并且在高到足以完成所述粘结膜的凝固并且高于所述焊料的熔点温度的温度下加热该粘结膜,从而将该凸起阵列封装连接到线路板上。
2.根据权利要求1的所述将凸起阵列封装电连接到线路板上的方法,该凸起阵列封装在平面上具有多个金属凸起作为半导体芯片的输入/输出端子,包括如下步骤:
将热流态化、热固化粘结膜布置在具有多个金属凸起的所述凸起阵列封装的表面上;形成凸起阵列封装,该凸起阵列封装具有包括所述金属凸起和所述粘结膜的平面,其中在温度高到足以使所述粘结膜流态化但是没有高到完成所述粘结膜的凝固并且低于所述金属凸起的熔化温度的温度下,用具有扁平表面的板压制所述粘结膜,使所述金属凸起的末端部分地压平并且在表面上暴露出来,以及
通过将包括所述金属凸起和所述粘结膜的平面布置在线路板上,并且在高到足以完成所述粘结膜的凝固并且高于所述金属凸起的熔点温度的温度下加热该粘结膜,从而将该凸起阵列封装连接到线路板上。
3.根据权利要求1或2的所述方法,其中所述热流态化、热固化粘结膜包括热塑性组分和热固化组分。
4.根据权利要求1到3中任意一项的所述方法,其中所述热流态化、热固化粘结膜包括包含己内酯改性环氧树脂的热固化粘结组分。
5.根据权利要求1到4中任意一项的所述方法,其中基于所述粘结膜的总量,所述热流态化、热固化粘结膜包含35到100%的有机颗粒。
6.根据权利要求1到5中任意一项的所述方法,进一步包括如下步骤:在将包括所述金属凸起和所述粘结膜的平面布置到线路板上之前,在要与所述线路板连接的部分上涂覆助熔剂。
7.根据权利要求1到6中任意一项的所述方法,其中在焊接回流炉中进行将凸起阵列封装连接到线路板上的步骤。
8.一种具有粘结膜的凸起阵列封装,其中金属凸起的末端被部分地压平并且暴露在表面上,由此具有包括所述金属凸起和所述粘结膜的平面
9.根据权利要求8的所述具有粘结膜的凸起阵列封装,其中金属凸起被压扁到金属凸起原始高度的50到90%,由此金属凸起的末端被部分地压平。
10.根据权利要求8或9的所述具有粘结膜的凸起阵列封装,其中金属凸起的末端被部分地压平并且暴露在表面上,由此具有包括所述金属凸起和所述粘结膜的平面,该平面是通过制备在平面上具有多个金属凸起作为半导体芯片的输入/输出端子的凸起封装阵列,将热流态化、热固化粘结膜布置在具有金属凸起的所述凸起阵列封装的表面上,并且在温度高到足以使所述粘结膜流态化但是没有高到完成所述粘结膜的凝固并且低于所述金属凸起的熔化温度的温度下,用具有平面的板子压制所述粘结膜而得到的。
CNB2005800382096A 2004-11-01 2005-10-14 将半导体封装连接到印刷线路板上的方法 Expired - Fee Related CN100550329C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004318225A JP2006128567A (ja) 2004-11-01 2004-11-01 半導体パッケージのプリント配線板への接続方法
JP318225/2004 2004-11-01

Publications (2)

Publication Number Publication Date
CN101103449A true CN101103449A (zh) 2008-01-09
CN100550329C CN100550329C (zh) 2009-10-14

Family

ID=36216812

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005800382096A Expired - Fee Related CN100550329C (zh) 2004-11-01 2005-10-14 将半导体封装连接到印刷线路板上的方法

Country Status (7)

Country Link
US (1) US20090127692A1 (zh)
EP (1) EP1810325A2 (zh)
JP (1) JP2006128567A (zh)
KR (1) KR20070084607A (zh)
CN (1) CN100550329C (zh)
TW (1) TW200620513A (zh)
WO (1) WO2006049853A2 (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102695373A (zh) * 2011-03-25 2012-09-26 株式会社日立工业设备技术 印刷基板的制造装置以及制造方法
CN102832327A (zh) * 2011-06-16 2012-12-19 日东电工株式会社 荧光粘接片、发光二极管元件及其装置、及它们的制法
TWI552994B (zh) * 2015-02-06 2016-10-11 Psk有限公司 裝置封裝方法
US9824998B2 (en) 2015-02-06 2017-11-21 Semigear, Inc. Device packaging facility and method, and device processing apparatus utilizing DEHT
CN108307591A (zh) * 2017-01-13 2018-07-20 奥特斯奥地利科技与系统技术有限公司 通过在安装于部件承载件材料之前用附着物覆盖部件制造的部件承载件
CN109047965A (zh) * 2018-09-20 2018-12-21 北京机械设备研究所 一种多管脚封装器件的焊接工装及其使用方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5336700B2 (ja) * 2006-11-30 2013-11-06 ローム株式会社 半導体装置およびそれを用いた電子機器
US8039305B2 (en) 2007-04-27 2011-10-18 Sumitomo Bakelite Company, Ltd. Method for bonding semiconductor wafers and method for manufacturing semiconductor device
US9024455B2 (en) 2010-05-26 2015-05-05 Hitachi Chemical Company, Ltd. Semiconductor encapsulation adhesive composition, semiconductor encapsulation film-like adhesive, method for producing semiconductor device and semiconductor device
KR100891537B1 (ko) * 2007-12-13 2009-04-03 주식회사 하이닉스반도체 반도체 패키지용 기판 및 이를 갖는 반도체 패키지
JP5970071B2 (ja) * 2011-09-30 2016-08-17 インテル・コーポレーション デバイス構造の製造方法および構造
US8815706B2 (en) * 2012-01-20 2014-08-26 Infineon Technologies Ag Methods of forming semiconductor devices
WO2017098736A1 (ja) * 2015-12-08 2017-06-15 リンテック株式会社 ダイシングシートおよびダイシングシートの製造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01263112A (ja) * 1988-04-15 1989-10-19 Fujitsu Ltd 半導体封止用エポキシ樹脂組成物
US5128746A (en) * 1990-09-27 1992-07-07 Motorola, Inc. Adhesive and encapsulant material with fluxing properties
US5543585A (en) * 1994-02-02 1996-08-06 International Business Machines Corporation Direct chip attachment (DCA) with electrically conductive adhesives
US5932682A (en) * 1995-12-19 1999-08-03 International Business Machines Corporation Cleavable diepoxide for removable epoxy compositions
US6121689A (en) * 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6260264B1 (en) * 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
JPH11289033A (ja) * 1998-04-03 1999-10-19 Toshiba Corp 液状エポキシ樹脂組成物および樹脂封止型半導体装置
JP3336253B2 (ja) * 1998-04-23 2002-10-21 松下電工株式会社 半導体装置とその製造方法、実装方法および用途
US6265776B1 (en) * 1998-04-27 2001-07-24 Fry's Metals, Inc. Flip chip with integrated flux and underfill
US6228678B1 (en) * 1998-04-27 2001-05-08 Fry's Metals, Inc. Flip chip with integrated mask and underfill
JP2000040711A (ja) * 1998-07-23 2000-02-08 Sony Corp 樹脂封止型半導体装置とその製造方法
JP3558576B2 (ja) * 1999-02-22 2004-08-25 三菱電機株式会社 半導体装置の製造方法および半導体装置
US6746896B1 (en) * 1999-08-28 2004-06-08 Georgia Tech Research Corp. Process and material for low-cost flip-chip solder interconnect structures
JP4195541B2 (ja) * 2000-05-12 2008-12-10 三井化学株式会社 半導体チップをプリント配線基板に装着する方法及びその方法の実施に用いる装着用シート
JP4441090B2 (ja) * 2000-10-11 2010-03-31 三井化学株式会社 プリント配線基板に半導体チップを装着する方法
US6518675B2 (en) * 2000-12-29 2003-02-11 Samsung Electronics Co., Ltd. Wafer level package and method for manufacturing the same
US6624216B2 (en) * 2002-01-31 2003-09-23 National Starch And Chemical Investment Holding Corporation No-flow underfill encapsulant
US6869832B2 (en) * 2003-02-07 2005-03-22 Lockheed Martin Corporation Method for planarizing bumped die
EP1557880A1 (en) * 2004-01-21 2005-07-27 Nitto Denko Corporation Resin composition for encapsulating semiconductor

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102695373A (zh) * 2011-03-25 2012-09-26 株式会社日立工业设备技术 印刷基板的制造装置以及制造方法
CN102695373B (zh) * 2011-03-25 2015-01-28 株式会社日立制作所 印刷基板的制造装置以及制造方法
CN102832327A (zh) * 2011-06-16 2012-12-19 日东电工株式会社 荧光粘接片、发光二极管元件及其装置、及它们的制法
TWI552994B (zh) * 2015-02-06 2016-10-11 Psk有限公司 裝置封裝方法
US9472531B2 (en) 2015-02-06 2016-10-18 Semigear, Inc. Device packaging facility and method, and device processing apparatus utilizing phthalate
US9741683B2 (en) 2015-02-06 2017-08-22 Semigear, Inc. Device packaging facility and method, and device processing apparatus utilizing phthalate
US9824998B2 (en) 2015-02-06 2017-11-21 Semigear, Inc. Device packaging facility and method, and device processing apparatus utilizing DEHT
US10283481B2 (en) 2015-02-06 2019-05-07 Semigear, Inc. Device packaging facility and method, and device processing apparatus utilizing DEHT
US10937757B2 (en) 2016-07-27 2021-03-02 Semigear, Inc. Device packaging facility and method, and device processing apparatus utilizing DEHT
CN108307591A (zh) * 2017-01-13 2018-07-20 奥特斯奥地利科技与系统技术有限公司 通过在安装于部件承载件材料之前用附着物覆盖部件制造的部件承载件
CN109047965A (zh) * 2018-09-20 2018-12-21 北京机械设备研究所 一种多管脚封装器件的焊接工装及其使用方法

Also Published As

Publication number Publication date
WO2006049853A2 (en) 2006-05-11
CN100550329C (zh) 2009-10-14
WO2006049853A3 (en) 2006-08-24
JP2006128567A (ja) 2006-05-18
TW200620513A (en) 2006-06-16
EP1810325A2 (en) 2007-07-25
US20090127692A1 (en) 2009-05-21
KR20070084607A (ko) 2007-08-24

Similar Documents

Publication Publication Date Title
CN100550329C (zh) 将半导体封装连接到印刷线路板上的方法
US6335571B1 (en) Semiconductor flip-chip package and method for the fabrication thereof
US7047633B2 (en) Method of using pre-applied underfill encapsulant
US6399426B1 (en) Semiconductor flip-chip package and method for the fabrication thereof
US7109061B2 (en) Wafer applied fluxing and underfill material, and layered electronic assemblies manufactured therewith
KR100467897B1 (ko) 반도체 장치 및 이의 제조방법
JP2004530740A (ja) フラックス処理用アンダーフィル組成物
JP5310252B2 (ja) 電子部品実装方法および電子部品実装構造
KR20070116661A (ko) 이방 도전성 구조체
CN101116383A (zh) 两块印刷电路板的连接方法及由此得到的印刷电路板
JP4206631B2 (ja) 熱硬化性液状封止樹脂組成物、半導体素子の組立方法及び半導体装置
JP2010171118A (ja) 実装部品の表面実装方法、その方法を用いて得られる実装部品構造体、及びその方法に用いられるアンダーフィル用液状エポキシ樹脂組成物
CN109075088A (zh) 半导体装置的制造方法
JP4816333B2 (ja) 半導体装置の製造方法
JPH10289969A (ja) 半導体装置およびそれに用いる封止用樹脂シート
US7004375B2 (en) Pre-applied fluxing underfill composition having pressure sensitive adhesive properties
AU695142B2 (en) Semiconductor unit package, semiconductor unit packaging method and encapsulant for use in semiconductor unit packaging
JP2007523967A (ja) 発泡性アンダーフィル封入剤
JP2008189760A (ja) アンダーフィル剤、それを用いた半導体装置および半導体装置の製造方法
JP3183272B2 (ja) 半導体装置およびその製造方法
JP7436240B2 (ja) アンダーフィル材、及びこれを用いた半導体装置の製造方法
JP2000174044A (ja) 半導体素子の組立方法
JP7238453B2 (ja) 半導体用接着剤
JP2004067930A (ja) 液状封止樹脂組成物及びこれを用いた半導体装置並びに半導体装置の製造方法
JP2008147510A (ja) フリップチップ実装方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20091014

Termination date: 20131014