CN101068010A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN101068010A
CN101068010A CNA2007100051535A CN200710005153A CN101068010A CN 101068010 A CN101068010 A CN 101068010A CN A2007100051535 A CNA2007100051535 A CN A2007100051535A CN 200710005153 A CN200710005153 A CN 200710005153A CN 101068010 A CN101068010 A CN 101068010A
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electrode pad
salient point
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semiconductor device
semiconductor chip
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松本健
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

本发明的目的在于提供一种半导体器件，该半导体器件在划线PCM的电极焊盘中，能够防止切割时产生残留的凸点，能够防止因该残留的凸点部分所产生的电气泄漏等，同时能够抑制因加宽划线部分而使半导体芯片的产出数下降。为解决上述问题，本发明用电离倾向大的金属、特别是Al，形成想要附加凸点或镀膜的电极焊盘的最上层部分；用电离倾向小的金属、特别是Cu，形成不想要附加凸点或镀膜的电极焊盘的最上层部分。

Description

半导体器件
技术领域
本发明涉及例如在晶片形状的基板上形成多个半导体芯片及划线的半导体器件的结构，特别涉及在半导体芯片上及划线上设置的电极焊盘部分的结构。
背景技术
从以往以来，作为半导体器件，是制造例如在晶片形状的基板上形成将半导体电路集成化的多个半导体芯片及划线的半导体器件，所谓划线的区域，是在从晶片切出半导体电路作为半导体芯片时的「切除材料」部分，为了判断是否没有问题地形成了切出的半导体芯片内的半导体电路，在该划线上形成多个称为工艺控制模块(PCM：Process Control Module)的元件(以下，称为划线PCM)。
关于以上那样的以往的半导体器件(例如，日本国专利公开公报的特开2001-332577号公报)，下面参照附图进行说明。
图4A～图4C所示为以往的半导体器件的晶片上的半导体芯片及划线PCM的形状举例的详细形状图。现在，半导体器件一般以图4A所示的晶片形状形成。通常，经过称为扩散工序的制造工序，在晶片1上形成多个将半导体电路集成化的半导体芯片2。然后，如图4B所示，从晶片1切出半导体芯片2，进行封装等，从而制造作为片状的半导体集成电路器件(LSI)。其中，如图4C所示，在划线3的区域，形成上述的划线PCM4。
对该划线PCM4设置与外部进行电连接用的多层结构的电极焊盘5，通过在划线3形成这样的划线PCM4，能够确认作为整个晶片1上的半导体器件质量好，特别是能够确认电性能质量好。另外，这里虽未图示，但在半导体芯片2上也设置多个与外部进行电连接用的多层结构的电极焊盘。
图5A～图5D所示是在以往的半导体器件中，对划线3上配置形成的划线PCM4的电极焊盘5、以及半导体芯片2的电极焊盘6，利用化学镀形成凸点时的工艺流程剖面状态的一个例子。本例作为一个例子，是表示用3层形成多层布线层的情况的半导体器件图。
如图5A所示，电极焊盘5、6是以从图面下侧向上方重叠第1层电极焊盘、第2层电极焊盘、第3层电极焊盘的3层电极焊盘的状态形成的。这里，最上层的第3层电极焊盘用Al形成。这里，图面左侧的第3层电极焊盘是划线PCM4的电极焊盘5，图面右侧的电极焊盘是半导体芯片2的电极焊盘6。
如图5B所示，首先，这里进行化学镀Zn。通过这样，在划线PCM4的电极焊盘5、以及半导体芯片2的电极焊盘6上，进行镀Zn层的形成。作为该机理，是利用Al与Zn的电离倾向(电离倾向是Al＞Zn)，从而使电极焊盘的材料即Al作为Al离子6a溶解在化学镀Zn液中，在两者的电极焊盘上，形成化学镀Zn液中的Zn离子7a作为镀Zn层7，即进行所谓的置换。
然后，如图5C所示，进行化学镀Ni。通过这样，在划线PCM4的电极焊盘5、以及半导体芯片2的电极焊盘6的镀Zn层7上，进行Ni凸点8的形成。作为该机理，是利用Zn与Ni的电离倾向(电离倾向是Zn＞Ni)，从而使镀Zn层7作为Zn离子7a溶解在化学镀Ni液中，在镀Zn层7上，形成化学镀Ni液中的Ni离子8a作为Ni凸点8，即进行所谓的置换。
然后，如图5D所示，进行化学镀Au。通过这样，在划线PCM4的电极焊盘5、以及半导体芯片2的电极焊盘6的Ni凸点8上，进行镀Au层9的形成。作为该机理，是利用Ni与Au的电离倾向(电离倾向是Ni＞Au)，从而使Ni凸点8作为Ni离子8a溶解在化学镀Au液中，在Ni凸点8上，形成化学镀Au液中的Au离子9a作为镀Au层9，是进行所谓的置换的机理。
图6所示为关于图5B～图5D所示的对以往的半导体器件进行化学镀的方法的详细图。如本图所示，作为该机理，是利用电离倾向(电离倾向是Al＞Zn＞Ni＞Au)，从而使划线PCM4的电极焊盘5、以及半导体芯片2的电极焊盘6的金属，作为电极焊盘侧的金属离子14(在本例中，是Al、Zn、Ni离子)溶解在各种镀液13(在本例中，是Zn、Ni、Au镀液)中，在划线PCM4的电极焊盘5、以及半导体芯片2的电极焊盘6上，形成作为各种镀层(在本例中，是Zn、Ni、Au镀层)。
图7A～图7B所示为对于图5D所示的在划线PCM4的电极焊盘5上形成了凸点的部分、为了从前述的晶片1切出半导体芯片2而实施切割时的流程图。
如图7A所示，用切片刀10切割划线3(同时切割划线PCM4及划线PCM4的电极焊盘5、Ni凸点8、镀Au层9)。通过这样，如图7B所示，能够从晶片1切出片状的半导体芯片2。
但是，对于上述那样的以往的半导体器件，在图5D所示的电极焊盘的结构中，具有以下所示的问题。
图8A～图8B与图7A～图7B相同，所示为对于在划线PCM4的电极焊盘5上形成了凸点8的部分、为了从前述的晶片1切出半导体芯片2而实施切割时的流程图。如图8A所示，用切片刀10切割划线3(同时切割划线PCM4及划线PCM4的电极焊盘5、Ni凸点8、镀Au层9)。
但是，在如图8A所示那样，切片刀10从适当位置偏离时，则如图8B所示，凸点8尽管切割了，但仍残留有边缘部分，产生这样的异常状态。若这样在切出半导体芯片2时，有导电性的凸点8仍残留有边缘部分，则在后面的组装工序中进行封装时，因该「残留的凸点」部分而恐怕会产生电气泄漏等。
图9与图8A～图8B相同，所示为对于在划线PCM4的电极焊盘5上形成了凸点8的部分、为了从前述的晶片1切出半导体芯片2而实施切割时的状态图。在这种情况下，虽用切片刀10切割划线3(同时切割划线PCM4及划线PCM4的电极焊盘5、Ni凸点8、镀Au层9)，但在本图的情况下，为了不使凸点8残留边缘部分，加宽切片刀10的宽度进行切割。
若使用这样的方法，虽能够防止凸点8残留边缘部分的情况，但由于增大切片刀10的宽度、即「切除材料」的宽度，所以因该加宽的部分而必须加宽切线3的宽度。如果那样，则晶片1上的切线3的宽度要比前述图7A(图9的下图)所示的宽度要宽。因此，反之晶片1上形成半导体芯片2的面积减小，有可能以晶片为单位的半导体芯片2的产出数减少。
发明内容
本发明正是为了解决上述以往的问题，其目的在于提供一种半导体器件，该半导体器件在划线PCM的电极焊盘中，能够防止切割时产生「残留的凸点」，能够防止因该「残留的凸点」部分所产生的电气泄漏等，同时能够抑制因加宽划线部分而使半导体芯片的产出数下降。
为了解决上述问题，第1发明的特征是，在基板上形成半导体芯片及划线、在前述半导体芯片上及前述划线上设置多个多层结构的电极焊盘的半导体器件中，在前述多个电极焊盘中，将形成凸点或镀膜的前述电极焊盘的最上层部分，用电离倾向大于凸点或镀膜材料的金属形成；将不形成凸点或镀膜的前述电极焊盘的最上层部分，用电离倾向小于前述凸点或镀膜材料的金属形成。
另外，第2发明的特征是，位于前述半导体芯片上的电极焊盘形成前述凸点或前述镀膜，位于前述划线上的电极焊盘不形成前述凸点或前述镀膜。
另外，第3发明的特征是，前述电离倾向大的金属采用Al，前述电离倾向小的金属采用Cu。
如上所述，根据本发明，能够在切割部分形成的划线PCM的电极焊盘不形成凸点，而仅在半导体芯片的电极焊盘形成凸点。
因此，在划线PCM的电极焊盘，能够防止切割时产生「残留的凸点」，能够防止因该「残留的凸点」部分所产生的电气泄漏等。
另外，能够抑制以往结构的问题、即因加宽划线部分而使半导体芯片的产出数下降。
再加上，在进行化学镀时，也能够对多个电极焊盘有选择地操作有无镀层。
附图说明
图1A为本发明实施形态1的半导体器件的凸点形成的工艺流程1图。
图1B为本发明实施形态1的半导体器件的凸点形成的工艺流程2图。
图1C为本发明实施形态1的半导体器件的凸点形成的工艺流程3图。
图1D为本发明实施形态1的半导体器件的凸点形成的工艺流程4图。
图2为对该实施形态1的半导体器件的切片刀的大小比较图。
图3为本发明实施形态2的半导体器件的半导体芯片的外形图。
图4A为以往的半导体器件的晶片的形状举例说明图。
图4B为从以往的半导体器件的晶片切出芯片的说明图。
图4C为以往的半导体器件的晶片上的划线PCM部分的形状举例说明图。
图5A为该以往例的半导体器件的凸点形成的工艺流程1图。
图5B为该以往例的半导体器件的凸点形成的工艺流程2图。
图5C为该以往例的半导体器件的凸点形成的工艺流程3图。
图5D为该以往例的半导体器件的凸点形成的工艺流程4图。
图6为对该以往例的半导体器件的化学镀方法的说明图。
图7A为对该以往例的半导体器件进行切割时的流程1图。
图7B为对该以往例的半导体器件进行切割时的流程2图。
图8A为对该以往例的半导体器件根据其它条件进行切割时的流程1图。
图8B为对该以往例的半导体器件根据其它条件进行切割时的流程2图。
图9为对该以往例的半导体器件根据另外的其它条件进行切割时的流程图。
具体实施方式
以下，参照附图具体说明表示本发明的实施形态的半导体器件。
(实施形态1)
下面，说明本发明实施形态1的半导体器件。
图1A～图1D所示是在本实施形态1的半导体器件中，对于形成在划线3上的划线PCM4的电极焊盘5不形成凸点、而对于半导体芯片2的电极焊盘6利用化学镀形成凸点时的工艺流程剖面状态的一个例子。在本例中，是表示用3层形成多层结构的布线焊盘的情况下的半导体器件图。
图1A所示为本实施形态1的半导体器件的形状。这里图面左侧的电极焊盘是划线PCM4的电极焊盘5，图面右侧的电极焊盘是半导体芯片2的电极焊盘6。
划线PCM4的电极焊盘5是以重叠第1层电极焊盘、第2层电极焊盘的2层电极焊盘的状态形成的。这里，划线PCM4的电极焊盘5(第2层电极焊盘)用Cu形成。
另外，半导体芯片2侧的电极焊盘6是以重叠第1层电极焊盘、第2层电极焊盘、第3层电极焊盘的3层电极焊盘的状态形成的。这里，半导体芯片2侧的电极焊盘6中，第3层(最上层)的电极焊盘用Al形成。
即形成下述结构，利用后述的化学镀方法用Al形成想要附加凸点或镀膜的部分的最上层电极焊盘(这里是半导体芯片2的电极焊盘6)，利用化学镀方法用Cu形成不想要附加凸点或镀膜的部分的最上层电极焊盘(这里是划线PCM4的电极焊盘5)。
如图1B所示，首先利用化学镀方法进行镀Zn。通过这样，在半导体芯片2的电极焊盘6上进行镀Zn层7的形成。作为该机理，是利用Al与Zn的电离倾向(电离倾向是Al＞Zn)，从而使半导体芯片2的电极焊盘6的Al作为Al离子6a溶解在镀Zn液中，在半导体芯片2的电极焊盘6上，形成镀Zn液中的Zn离子7a作为镀Zn层7，是进行所谓的置换的机理。
但是，划线PCM4侧的电极焊盘5用Cu形成，在利用该置换方式的化学镀中，由于Cu的电离倾向相对于Zn非常小，因此Cu本身不作为Cu离子溶解在镀Zn液中。所以，在划线PCM4侧的电极焊盘5上也没有形成镀Zn液中的Zn离子作为镀Zn层。即，在划线PCM4侧的电极焊盘5上没有形成镀Zn层7。
然后，如图1C所示，进行化学镀Ni。通过这样，在半导体芯片2侧的电极焊盘6上，进行Ni凸点8的形成。作为该机理，是利用Zn与Ni的电离倾向(电离倾向是Zn＞Ni)，从而使镀Zn层7作为Zn离子7a溶解在化学镀Ni液中，在半导体芯片2的电极焊盘6上，形成化学镀Ni液中的Ni离子8a作为Ni凸点8，是进行所谓的置换的机理。
但是，这里也同样，在划线PCM4侧的电极焊盘5上没有形成镀Zn层7。再有，由于Cu的电离倾向比Ni要小，因此在划线PCM4侧的电极焊盘5上没有形成Ni凸点8。
然后，如图1D所示，进行化学镀Au。通过这样，在半导体芯片2的电极焊盘6的Ni凸点8上，进行镀Au层9的形成。作为该机理，是利用Ni与Au的电离倾向(电离倾向是Ni＞Au)，从而使Ni作为Ni离子8a溶解在化学镀Au液中，在半导体芯片2的电极焊盘6的Ni凸点8上，形成化学镀Au液中的Au离子9a作为镀Au层9，是进行所谓的置换的机理。
但是，这里也同样，由于在划线PCM4侧的电极焊盘5上没有形成Ni凸点，因此即使具有化学镀Au液，在划线PCM4侧的电极焊盘5上也没有形成镀Au层。
采用以上的方法，在半导体芯片2的电极焊盘6上形成凸点、而仅在划线PCM4侧的电极焊盘5上不形成凸点的化学镀工艺。
图2为比较切割图1D中没有形成凸点的划线PCM4的电极焊盘5时的切片刀10的大小、与切割用图5D的工艺形成凸点的划线PCM4侧的电极焊盘5时的切片刀10的大小的比较图。
由本图可知，切割没有形成凸点的划线PCM4的电极焊盘5时的切片刀10较小。作为其理由是，以往如图2的下图所示，用切片刀10切割划线3部分(同时切割划线PCM4及划线PCM4的电极焊盘5、Ni凸点8、镀Au层9)，但在这种情况下，由于如前述的图8A～图8B所示，在边缘部分有可能残留凸点8等，因此要加宽切片刀10的宽度进行切割，由此加大切片刀10的宽度，即加大「切除材料」的宽度，所以产生的问题是，因该加宽的部分而必须加宽切线3的宽度。
但是，如图2的上图所示，在本实施形态1中，由于没有形成凸点，因此不可能在电极焊盘5的边缘部分残留凸点等，不需要加宽切片刀10的宽度进行切割，由此不需要加大切片刀10的宽度，即不需要加大「切除材料」的宽度，
因而，由于晶片1中的划线3部分的面积减小，因此反之形成设置有半导体集成电路的半导体芯片2的面积增多，能够抑制以晶片为单位的半导体芯片2的产出数的减少。
(实施形态2)
下面，说明本发明实施形态2的半导体器件。
图3为从本实施形态2的半导体器件切出的半导体芯片的外形图。如图3所示，在该半导体芯片2中，例如以化学镀用Al形成想要附加凸点的部分的电极焊盘11，以化学镀用Cu形成不想要附加凸点的部分的电极焊盘12。对于该半导体芯片2的电极焊盘，利用前面的图1A～图1D所示的化学镀方法进行凸点形成。
根据以上所述，如前面的图1A～图1D中说明的那样，在Cu上不形成凸点，而仅在Al上形成凸点。即，通过采用该半导体器件的结构，能够进行以往是不可能的化学镀中的选择性镀层。

Claims (4)

1.一种半导体器件，在基板上形成半导体芯片及划线、在所述半导体芯片上及所述划线上设置多个多层结构的电极焊盘，其特征在于，
在所述多个电极焊盘中，将形成凸点或镀膜的所述电极焊盘的最上层部分，用电离倾向大于凸点或镀膜材料的金属形成；将不形成凸点或镀膜的所述电极焊盘的最上层部分，用电离倾向小于所述凸点或镀膜材料的金属形成。
2.如权利要求1所述的半导体器件，其特征在于，
位于所述半导体芯片上的电极焊盘形成所述凸点或所述镀膜，位于所述划线上的电极焊盘不形成所述凸点或所述镀膜。
3.如权利要求1所述的半导体器件，其特征在于，
所述电离倾向大的金属采用Al，所述电离倾向小的金属采用Cu。
4.如权利要求2所述的半导体器件，其特征在于，
所述电离倾向大的金属采用Al，所述电离倾向小的金属采用Cu。
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