CN101030562A - 用于半导体封装的散热器 - Google Patents

用于半导体封装的散热器 Download PDF

Info

Publication number
CN101030562A
CN101030562A CNA2007100843939A CN200710084393A CN101030562A CN 101030562 A CN101030562 A CN 101030562A CN A2007100843939 A CNA2007100843939 A CN A2007100843939A CN 200710084393 A CN200710084393 A CN 200710084393A CN 101030562 A CN101030562 A CN 101030562A
Authority
CN
China
Prior art keywords
radiator
air vent
face
vent hole
mold compound
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2007100843939A
Other languages
English (en)
Inventor
R·易朴拉欣
K·B·蒂乌
K·V·C·穆尼安迪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN101030562A publication Critical patent/CN101030562A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明公开了一种用于半导体封装(38)的散热器(10),该散热器包括顶面(12),该顶面在其中心具有凹孔(16)。围绕散热器(10)的顶面(12)形成的侧壁(14)具有在侧壁(14)中形成的缺口(18)。在散热器(10)的角部处形成通气孔(22)。散热器(10)用于中心浇口成型。成型化合物(24)进入凹孔(16)、覆盖IC管芯(30)并经由缺口(18)排出。在成型注入期间,空气通过通气孔(22)排出。

Description

用于半导体封装的散热器
技术领域
本发明涉及集成电路(IC)的封装,并且尤其涉及用于半导体封装的散热器。
背景技术
借助引线接合技术的优点,半导体装配人员现在能制造具有更细微管脚间距和更复杂布线图的半导体封装。然而,在成型期间,细微的管脚间距应用和包括长导线的应用都易发生导线扫掠(wiresweep)。导线扫掠是不期望的,因为它会影响封装的电性能,并会导致封装故障。
测试已表明,通过使用中心或顶浇口成型工艺,而不是传统的边缘浇口成型工艺,可减少成型期间的导线扫掠。然而,由于传统的散热器通常设计用于边缘浇口成型工艺,并且由此不适于用在中心浇口成型工艺中,所以中心浇口成型封装的热管理可能引起问题。例如,由于在中心浇口成型工艺中成型化合物(mold compound)的径向流动模式,空气易于在传统散热器的侧面被捕集。捕集的空气在所得到的半导体封装中成为孔隙。孔隙的存在降低了封装的可靠性,并会造成封装缺陷,由此降低这种封装的成品率。因而,需要用于中心浇口成型式半导体封装的散热器。
附图说明
当结合附图阅读时,将较好地理解本发明的优选实施例的以下详细说明。本发明借助示例进行说明并且不受附图限制,在附图中类似的附图标记表示类似的元件。应理解,附图不是按比例的,并且为了易于理解本发明而已被简化。
图1是根据本发明实施例的散热器的放大立体图;
图2是图1的散热器的放大的俯视图;
图3是图1的散热器的放大的横截面图;
图4是根据本发明实施例置于模腔中的半导体组件的放大横截面图;
图5是半导体组件沿图4中的线X-X的放大的横截面图;
图6是被成型化合物封装的图4的半导体组件的放大的俯视图;
图7是由图6的已封装半导体组件形成的半导体封装的放大的俯视图;
图8是图7的半导体封装的放大的横截面图。
具体实施方式
以下结合附图作出的详细说明意在作为本发明的当前优选实施例的说明,而不意在代表可实施本发明的仅有形式。应理解,可通过意在包含在本发明的精神和范围内的不同实施例实现相同或等效的功能。在所有附图中,使用类似的附图标记指示类似的元件。
本发明提供一种用于半导体封装的散热器。该散热器包括顶面和至少一个通气孔,所述顶面具有接近其中心的凹孔,所述至少一个通气孔接近散热器的角部。
本发明还提供一种用于半导体封装的散热器,该散热器包括顶面,所述顶面具有接近其中心的凹孔。围绕散热器的顶面形成有侧壁。在侧壁中形成有多个缺口。该散热器包括接近其角部的至少一个通气孔。
本发明还提供一种半导体封装,该半导体封装包括基板和附装且电连接到基板的集成电路(IC)管芯。在IC管芯上方放置有散热器,该散热器附装到基板上。该散热器包括顶面和至少一个通气孔,所述顶面具有接近其中心的凹孔,所述至少一个通气孔接近散热器的角部。
图1至图3示出根据本发明实施例的散热器10。
现在参照图1,示出散热器10的放大立体图。散热器10具有顶面12和形成在顶面12周围的侧壁14。散热器10的尺寸和形状设计成总体上配合安装在半导体集成电路(IC)上方。例如,对于边长5mm的正方形IC,散热器10也成形为正方形,并且在一个实施例中边长约为20mm。使散热器10的尺寸大于IC可以留有用于导线接合部和封装的空间。而且,散热器10的尺寸可以用于良好的定位公差。散热器10可由铜或本领域中已知的其它导热材料制成。
顶面12包括接近其中心的凹孔16。孔16便于中心浇口成型,同时孔16中的凹陷减少了在封装期间成型化合物渗出或溢出。下文参照图8说明实现减少渗出或溢出的机理。在一个实施例中,孔16具有约4.0~5.0mm的外周直径Douter和约1.5~2.0mm的内周直径Dinner。然而,本领域的技术人员应理解,本发明不受孔16的尺寸或形状的限制。凹孔16可通过切割或冲孔形成。
在侧壁14中形成有多个缺口18,并且在侧壁14的远端形成有基部20。如所见到的,缺口18沿散热器10的各侧面形成。缺口18使成型化合物在封装期间可从散热器10下方流出。在所示实施例中,缺口18为矩形形状,例如具有约6.0mm至约7.0mm的宽度Wgap和约0.5mm的高度Hgap。但是应理解,本发明不受缺口18的形状或尺寸的限制。缺口18可通过切割或冲孔形成。
散热器10包括接近其角部的至少一个通气孔22。通气孔22便于空气在成型封装工艺期间从散热器10的顶面12的下方释出,并且通气孔的尺寸设计成限制成型化合物在封装期间通过通气孔流动。例如,通气孔22可具有约0.5mm至约0.8mm的高度Hvent和约1.0mm至约1.5mm的宽度Wvent。在所示实施例中,通气孔22为矩形,并且从散热器10的顶面12延伸到基部20。但是应理解,本发明不受通气孔22的尺寸或形状的限制。
现在参照图2,示出散热器10的放大俯视图。如所见到的,在散热器10的各角部中形成有多个通气孔22。由于通气孔22便于空气从散热器10的顶面12下方释出,在散热器10中优选形成多于一个通气孔22。因此,通过设置较多通气孔22减小了空气被捕集在散热器10的顶面12下方的可能性。这继而减少了在所得到半导体封装中形成的孔隙的数量。然而,应理解,本发明不受散热器10中的通气孔22的数量的限制。通气孔22可通过切割或冲孔形成。刻蚀也是可以的,但不经济。
现在参照图3,使出散热器10的放大的横截面图。在该具体实施例中,凹孔16具有约40至50微米的深度Hhole。然而,应理解,本发明不受凹孔16的深度Hhole的限制。如上所述,孔16中的凹陷减少了封装期间成型化合物的渗出或溢出。图3所示的散热器10的侧壁14不垂直于散热器10的顶面12,虽然可以是垂直的。在所示实施例中,侧壁14从散热器10的顶面12以在约120°到约135°之间的角度θ延伸。基部20可包括在其下侧上的一个或多个凸块23或凹座。当附装材料(例如环氧树脂)在与凸块23一致的位置处分配在基板上时,凸块23增强散热器到基板的附装。凸块23也有助于维持散热器的平面度。凸块23可通过座陷(downsetting)/冲压工艺形成。
图4至图7示出在封装半导体组件26的中心浇口成型工艺期间成型化合物24的流动,该半导体组件26包括图1至图3的散热器10。
现在参照图4,如图所示,半导体组件26置于模腔28中。该半导体组件26包括附装并电连接到基板32的集成电路(IC)管芯30。IC管芯30是本领域普通技术人员熟知的类型,诸如处理器芯片、专用集成电路(ASIC)等,并且对这些部件的进一步说明对于完全理解本发明是不需要的。IC管芯30以已知方式(例如用粘合材料层或粘合带)附装到基板32,并且经由多根导线34电连接到基板32上。导线34可由金(Au)、铜(Cu)、铝(Al)或本领域已知并且可买到的其它导电材料制成。
散热器10放置在IC管芯30上方并且附装到基板32上。更具体地,散热器10的基部20附装到基板32。散热器10使用现有设备和工艺用粘合剂或以任何其它已知的方式附装到基板32。
成型化合物24经由中心或顶浇口36分配,并流过散热器10的顶面12中的孔16,以填充模腔28。成型化合物24因而进入孔16,并且在IC管芯30的顶部上向外展开。
现在参照图5,示出半导体组件26沿图4中的线X-X的放大的横截面图。成型化合物24在进入散热器10的顶面12下方的空间时从其进入点(即,孔16)径向向外向散热器10的周边流动。散热器10的顶面12下方的空气通过成型化合物24移动,并且通过沿散热器10侧面的缺口18和散热器10角部处的通气孔22排出。因此,在散热器10的各角部设置通气孔22避免了空气的捕集,由此减小了在所得到半导体封装中形成的孔隙的数量。成型化合物24还通过缺口18、侧壁14和基部20的外侧上方流到模腔28的边缘。
现在参照图6,示出由成型化合物24封装的图4的半导体组件26的放大的俯视图。大量成型化合物24从散热器10下方经由沿散热器10的侧面的缺口18流出。一旦流出散热器10,成型化合物24就围绕散热器10流向位于模腔28的角部处的成型通气孔(未示出)。缺口18沿散热器10的侧面的布置将成型化合物24的流动导向到模腔28的所有部分,同时通气孔22使空气可以从顶面12下方排出,由此避免空气的捕集,这减小了在所得到半导体封装中形成的孔隙的数量。如上所述,通气孔22的尺寸设计成限制成型化合物24在封装期间通过通气孔的流动。通气孔22以这种方式设计尺寸以便避免过早密封,如果大量成型化合物24可以通过通气孔则会发生过早密封。在示例性实施例中,通气孔22具有约1.0到约1.5mm的宽度Wvent
如从图6可见到的,散热器10的顶面12基本为正方形。但是,本领域的技术人员应理解,本发明不受散热器10的顶面12的形状限制。在可替换实施例中,散热器10的顶面12可以是矩形或圆形。然而,基本为正方形或矩形的顶面12比圆形顶面是优选的,因为与后者相比,前者形状提供例如用于较长字符串的较大标记表面和用于散热的较大暴露表面。除了提供较大的标记表面和用于散热的较大暴露表面之外,矩形的散热器10还有助于维持成型化合物24围绕散热器10的一致流速。
现在参照图7,示出形成在图6的已封装半导体组件26外形成的半导体封装38的一个实施例的放大的俯视图。如所见到的,散热器10的顶面12在封装后露出。然而,因为凹孔16填充有成型化合物24,所以在激光标记期间保留有除外区域40(由虚线限定),以避免对半导体封装38的损坏。
现在参照图8,示出半导体封装38的放大的横截面图。如所见到的,IC管芯30、基板32的一部分和散热器10的一部分由成型化合物24覆盖。至少散热器10的顶面12被露出。在封装期间,来自成型化合物24的背压在顶面12的凹陷部分上施加向上的力,这导致孔16的尺寸减小,从而阻止了成型化合物24通过孔16流回。由于孔16的尺寸减小用于将成型化合物24保持在模腔28内,因而减少了成型化合物24的渗出或溢出。
从以上讨论显而易见,本发明提供了一种用于中心浇口成型半导体封装的散热器。在本发明中,接近散热器的顶面的中心形成有孔,以便于中心浇口成型。该孔凹陷以减少成型化合物在封装期间的渗出或溢出。沿散热器的侧面设置的缺口和接近散热器的角部设置的至少一个通气孔用于将成型化合物的流动导向到模腔的所有部分,由此防止空气的捕集。这减小了在所得到半导体封装中形成的孔隙的数量,由此提高这种封装的可靠性和成品率。另外,散热器的顶面成形为提供较大的标记表面和用于散热的较大暴露表面。
为了说明和描述的目的给出了本发明的优选实施例的说明,而不是穷举或将本发明限制到公开的形式。本领域技术人员应理解,可对上述实施例做出修改而不背离其宽泛的发明概念。例如,本发明可应用在通过中心浇口成型工艺封装的上方成型封装上,包括但不局限于OMPAC PBGA、Die Up TBGA和TBGA封装。另外,可改变管芯大小和台阶的尺寸以适应所需的封装设计。因此,应理解,本发明不局限于公开的具体实施例,而是覆盖在由所附权利要求书限定的本发明的精神和范围内的变型。

Claims (10)

1.一种用于半导体封装的散热器,包括:
顶面,所述顶面包括接近所述顶面中心的凹孔;以及
至少一个通气孔,所述至少一个通气孔接近所述散热器的角部。
2.根据权利要求1所述的散热器,其特征在于,所述孔便于中心浇口成型。
3.根据权利要求2所述的散热器,其特征在于,所述凹孔减少了成型化合物在封装期间的渗出。
4.根据权利要求1所述的散热器,其特征在于,所述通气孔便于所述散热器的顶面下方的空气的释出。
5.根据权利要求4所述的散热器,其特征在于,所述通气孔的尺寸设计成限制成型化合物在封装期间通过所述通气孔的流动。
6.根据权利要求1所述的散热器,其特征在于,所述散热器还包括围绕所述散热器的顶面形成的侧壁。
7.根据权利要求6所述的散热器,其特征在于,所述散热器还包括形成在所述侧壁中的多个缺口。
8.根据权利要求7所述的散热器,其特征在于,所述缺口沿所述散热器的各个侧面形成。
9.根据权利要求8所述的散热器,其特征在于,所述至少一个通气孔包括在所述散热器的各个角部中形成的多个通气孔。
10.根据权利要求9所述的散热器,其特征在于,所述散热器还包括在所述侧壁的远端形成的基部。
CNA2007100843939A 2006-02-28 2007-02-28 用于半导体封装的散热器 Pending CN101030562A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/364,048 US20070200225A1 (en) 2006-02-28 2006-02-28 Heat sink for semiconductor package
US11/364,048 2006-02-28

Publications (1)

Publication Number Publication Date
CN101030562A true CN101030562A (zh) 2007-09-05

Family

ID=38443185

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2007100843939A Pending CN101030562A (zh) 2006-02-28 2007-02-28 用于半导体封装的散热器

Country Status (4)

Country Link
US (1) US20070200225A1 (zh)
CN (1) CN101030562A (zh)
SG (1) SG135134A1 (zh)
TW (1) TW200739845A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103594429A (zh) * 2012-08-17 2014-02-19 矽品精密工业股份有限公司 半导体封装结构及其散热件
CN104022087A (zh) * 2013-02-28 2014-09-03 阿尔特拉公司 模制半导体封装中的热传播

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4821537B2 (ja) * 2006-09-26 2011-11-24 株式会社デンソー 電子制御装置
JP2008135688A (ja) * 2006-10-30 2008-06-12 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
US7989947B2 (en) * 2007-03-06 2011-08-02 Panasonic Corporation Semiconductor device and method of manufacturing the same
US8643172B2 (en) * 2007-06-08 2014-02-04 Freescale Semiconductor, Inc. Heat spreader for center gate molding
CN101944492A (zh) * 2008-10-20 2011-01-12 联合科技公司 板上收缩封装
US7875970B2 (en) * 2009-06-10 2011-01-25 Green Arrow Asia Limited Integrated circuit package having a castellated heatspreader
US20110012257A1 (en) * 2009-07-14 2011-01-20 Freescale Semiconductor, Inc Heat spreader for semiconductor package
US8569869B2 (en) * 2010-03-23 2013-10-29 Stats Chippac Ltd. Integrated circuit packaging system with encapsulation and method of manufacture thereof
US8710640B2 (en) 2011-12-14 2014-04-29 Stats Chippac Ltd. Integrated circuit packaging system with heat slug and method of manufacture thereof
US9159643B2 (en) 2012-09-14 2015-10-13 Freescale Semiconductor, Inc. Matrix lid heatspreader for flip chip package
US8921994B2 (en) 2012-09-14 2014-12-30 Freescale Semiconductor, Inc. Thermally enhanced package with lid heat spreader
US9368375B2 (en) * 2013-10-11 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for self-aligning chip placement and leveling
US9093449B2 (en) 2013-10-23 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for chip placement and molding
US9769361B2 (en) * 2015-08-31 2017-09-19 Adlink Technology Inc. Assembly structure for industrial cameras
DE102015120396A1 (de) 2015-11-25 2017-06-01 Infineon Technologies Austria Ag Halbleiterchip-Package umfassend Seitenwandkennzeichnung
TWM542853U (zh) 2016-11-14 2017-06-01 日月光半導體製造股份有限公司 散熱片結構及具有散熱片結構之半導體封裝結構
KR102667427B1 (ko) * 2018-09-18 2024-05-21 삼성전자주식회사 반도체 패키지 시스템
US11244885B2 (en) * 2018-09-18 2022-02-08 Samsung Electronics Co., Ltd. Semiconductor package system

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5166772A (en) * 1991-02-22 1992-11-24 Motorola, Inc. Transfer molded semiconductor device package with integral shield
JPH06120374A (ja) * 1992-03-31 1994-04-28 Amkor Electron Inc 半導体パッケージ構造、半導体パッケージ方法及び半導体パッケージ用放熱板
US5387554A (en) * 1992-09-10 1995-02-07 Vlsi Technology, Inc. Apparatus and method for thermally coupling a heat sink to a lead frame
JP3509274B2 (ja) * 1994-07-13 2004-03-22 セイコーエプソン株式会社 樹脂封止型半導体装置およびその製造方法
KR0159986B1 (ko) * 1995-09-04 1998-12-01 아남산업주식회사 히트싱크 내장형 반도체 패키지의 제조방법 및 그 구조
TW388976B (en) * 1998-10-21 2000-05-01 Siliconware Precision Industries Co Ltd Semiconductor package with fully exposed heat sink
US6198163B1 (en) * 1999-10-18 2001-03-06 Amkor Technology, Inc. Thin leadframe-type semiconductor package having heat sink with recess and exposed surface
US6614123B2 (en) * 2001-07-31 2003-09-02 Chippac, Inc. Plastic ball grid array package with integral heatsink
US6784525B2 (en) * 2002-10-29 2004-08-31 Micron Technology, Inc. Semiconductor component having multi layered leadframe
US6969640B1 (en) * 2004-09-02 2005-11-29 Stats Chippac Ltd. Air pocket resistant semiconductor package system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103594429A (zh) * 2012-08-17 2014-02-19 矽品精密工业股份有限公司 半导体封装结构及其散热件
CN104022087A (zh) * 2013-02-28 2014-09-03 阿尔特拉公司 模制半导体封装中的热传播

Also Published As

Publication number Publication date
TW200739845A (en) 2007-10-16
SG135134A1 (en) 2007-09-28
US20070200225A1 (en) 2007-08-30

Similar Documents

Publication Publication Date Title
CN101030562A (zh) 用于半导体封装的散热器
EP2605276B1 (en) Packaged leadless semiconductor device
US7989947B2 (en) Semiconductor device and method of manufacturing the same
US8361843B2 (en) Method for fabricating heat dissipation package structure
US8564108B2 (en) Semiconductor device with heat spreader
US7659531B2 (en) Optical coupler package
US20080099891A1 (en) Semiconductor device and method of manufacturing the same
US20060105501A1 (en) Electronic device with high lead density
CN1264174A (zh) 树脂密封的半导体器件
US7109586B2 (en) System for reducing or eliminating semiconductor device wire sweep
CN104854695A (zh) 具有印刷形成的端子焊盘的引线载体
JP2009513029A (ja) 封止の改善された半導体装置
KR100652405B1 (ko) 수지누설을 억제할 수 있는 반도체 패키지 몰드 금형 및이를 이용한 반도체 패키지 제조방법
JP2008252054A (ja) 半導体装置および半導体装置の製造方法
CN100576522C (zh) 半导体封装结构及其制造方法
CN117096166A (zh) 图像传感器封装结构及相关方法
JP3434752B2 (ja) 樹脂封止型半導体装置およびその製造方法
US20150076680A1 (en) Heat spreader for integrated circuit device
US6696750B1 (en) Semiconductor package with heat dissipating structure
US9230874B1 (en) Integrated circuit package with a heat conductor
US8039941B2 (en) Circuit board, lead frame, semiconductor device, and method for fabricating the same
CN101924041B (zh) 用于装配可堆叠半导体封装的方法
US11239130B2 (en) Selective molding for integrated circuit
CN108074889B (zh) 热耗散装置和包含其的半导体封装装置
US20240112989A1 (en) Semiconductor device with resin bleed control structure and method therefor

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication