CN100596263C - 多层印刷电路板及其制造方法 - Google Patents
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 110
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 90
- 239000004020 conductor Substances 0.000 claims abstract description 60
- 239000011889 copper foil Substances 0.000 claims abstract description 54
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 24
- 238000007747 plating Methods 0.000 claims abstract description 12
- 238000005253 cladding Methods 0.000 claims description 40
- 238000000576 coating method Methods 0.000 claims description 33
- 239000011248 coating agent Substances 0.000 claims description 32
- 229910052802 copper Inorganic materials 0.000 claims description 23
- 239000010949 copper Substances 0.000 claims description 23
- 239000011347 resin Substances 0.000 claims description 20
- 229920005989 resin Polymers 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 18
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
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- 238000007906 compression Methods 0.000 claims description 8
- 230000004913 activation Effects 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 5
- 238000003825 pressing Methods 0.000 claims description 5
- 238000000992 sputter etching Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
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- 238000000059 patterning Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 229910000906 Bronze Inorganic materials 0.000 description 6
- 239000010974 bronze Substances 0.000 description 6
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
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- 208000034189 Sclerosis Diseases 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
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Abstract
提供一种制造多层印刷电路板和低成本包层板的方法。将用于形成导体层(10、17、18)的铜箔层(19、24、33)和用于形成蚀刻停止层(11、12)的镍镀层(20、21)交替层叠并压紧,形成用于印刷电路板的包层板(34)。有选择性地蚀刻用于印刷电路板的包层板(34)以制造基板。在该基板表面上形成外导体层(15、16)并制作图形。导体层(10、15、16)通过由蚀刻铜箔层(19、24、33)和镍镀层(20、21)而形成的柱状导体(17、18)实现电连接,制成多层印刷电路板。
Description
本申请是第99809113.8号,发明名称为“用于印刷电路板的包层板、使用该包层板的多层印刷电路板及其制造方法”的中国专利申请的分案申请。
技术领域
本发明涉及用于大规模半导体集成电路的多层印刷电路板及其制造方法。
背景技术
这些年,已经要求高度集成的布线板以满足对半导体器件集成度更高、管脚更多和重量更轻的需求。为了满足这些需求,已经对增加电路板的层数和提高电路集成度作了大量的研究和开发。
作为一种增加层数的方法,所谓的内部构建(build-up)法已经开发并得广泛应用。该方法包括层叠绝缘层和电路层,通过光刻绝缘层、形成通路孔并在其表面上形成电镀层来完成这些层之间的连接。在一些情况下,用激光形成通路孔。
日本专利特开平8-264971公开了使用内部构建法制造多层印刷电路板的方法。以下参照图9来简单解释该申请的制造方法。
首先,第一树脂层53在区域52内形成,该区域52在具有内导体图形50的内部板51上没有形成任何图形。第一树脂层53形成得使内导体图形50侧面和第一树脂层53之间存在规定的间隙54。其次,通过涂敷形成包含绝缘层的第二树脂层55,随后除去硬化的树脂。第二树脂层55填充间隙54并覆盖内导体图形50和第一树脂层53。接着,在第二树脂层55上形成粘附层56,再粗糙化。之后,通过无电镀在粘附层56上形成外导体图形57。
然而,上述由内部构建法形成的多层印刷电路板有以下问题需要解决。
即,在上述方法中,当通过在具有内导体图形50的内部板两侧层叠外导体图形57来制造多层印刷电路板时,要求复杂的工艺,例如形成第一树脂层53、通过涂敷形成第二树脂层55并随后除去硬化树脂、以及形成粘附层56。因此,使用内部构建方法不能使多层印刷电路板成本降低。
还有另一种制造多层印刷电路板的方法,其中金属薄膜通过蒸发形成。然而,该方法有这样的问题:当膜较薄时(几μm),容易产生孔,而当膜较厚时(10μm或更大),生产率下降,成本增加。
本发明旨在解决这些问题。本发明目的是生产制造成本低且有优良特性的用于印刷电路板的包层板、以及使用该包层板的多层印刷电路板及其制造方法。
发明内容
根据本发明第1方面的用于印刷电路板的包层板特征在于:它是通过以0.1-3%压缩率压力接合铜箔和镍箔来制造的,其中所述包层板是包含铜/镍/铜/镍/铜层的五层板。
根据本发明第2方面的用于印刷电路板的包层板特征在于:它是通过以0.1-3%压缩率压力接合其一侧或两侧具有镍镀层的铜箔与另一铜箔或与其一侧具有镍镀层的铜箔的,其中所述包层板是包含铜/镍/铜/镍/铜层的五层板。
根据本发明第3方面的用于印刷电路板的包层板特征在于:它是包含铜/镍/铜/镍/铜层的五层板。
根据本发明第4方面的多层印刷电路板,其特征在于它包括:
通过有选择性蚀刻根据本发明第1或2方面的用于印刷电路板的包层板而形成的具有内导体层的基板;
在所述基板表面上形成的绝缘层和外导体层;
所述外导体层被构图;且
通过插入经蚀刻而在所述基板中形成的柱状导体而实现内导体层和外导体层的电连接。
根据本发明第5方面的多层印刷电路板的制造方法,其特征在于包括以下工序:
通过层叠用作导体层的铜箔和用作蚀刻停止层的镍箔或镍镀层,并同时以0.1-3%压缩率压力接合两者而形成用于印刷电路板的包层板;
通过选择性蚀刻所述多层包层板来制作基板;
在所述基板表面上形成绝缘层和外导体层;
对所述外导体层制作图形;以及
通过插入经蚀刻而在所述基板中形成的柱状导体实现内导体层和外导体层的电连接。
根据本发明第6方面的制造方法,其特征在于:
所述用于印刷电路板的包层板是在所述铜箔和所述镍箔或镍镀层的接触表面在真空室预先活化处理之后,通过层叠所述铜箔和所述镍箔或镍镀层,并以0.1-3%压缩率冷压接合两者而形成的,并且在该情况下,
所述活化处理按如下执行:
①在1×10-1-1×10-4乇的超低压不活泼气体气氛中;
②电极A和其它绝缘固定的电极B之间的辉光-放电充电交流为1-50MHz,电极A包括分别电接地的具有接触表面的所述铜箔和所述镍镀层;
③溅射蚀刻;
④暴露在由所述辉光放电产生的等离子体中的电极面积不大于电极B面积的1/3。
根据本发明,提供了一种多层印刷电路板的制造方法,包括:
a.利用其中设置有镍层的铜层形成多层包层板,该板包括第一铜层/第一镍层/第二铜层/第二镍层/第三铜层;
b.在第一铜层上形成光刻胶膜,将所述光刻胶膜曝光,并显影所述光刻胶膜;
c.选择性地蚀刻第一铜层以形成柱状导体作为外铜层;
d.形成在第一镍层上形成光刻胶膜,曝光并显影所述光刻胶膜,并用树脂涂覆第一镍层以形成第一绝缘层;
e.通过蚀刻第一镍层、第二铜层和第二镍层来形成内导体层;
f.利用树脂涂覆所述内导体层的表面,以形成第二绝缘层,并抛光第二绝缘层,使得所述柱状导体的顶部被露出;
g.利用铜来涂覆树脂的表面以形成外导体层;
h.对所述外导体层制作图形。
附图说明
图1示出本发明的多层印刷电路板制造方法的实施例的说明图。
图2示出本发明的多层印刷电路板制造方法的实施例的说明图。
图3示出本发明的多层印刷电路板制造方法的实施例的说明图。
图4示出本发明的多层印刷电路板制造方法的实施例的说明图。
图5示出本发明的多层印刷电路板制造方法的实施例的说明图。
图6示出本发明的多层印刷电路板制造方法的实施例的说明图。
图7示出本发明的多层印刷电路板制造方法的实施例的说明图。
图8示出包层金属板的制造设备的前剖视图。
图9示出常规多层印刷电路板的前剖视图。
具体实施方式
以下参照附图表示的实施例具体地解释本发明。
首先,参照图7解释作为本发明实施例的多层印刷电路板的结构。
如图7所示,基板芯通过把包含镍镀层的蚀刻停止层11、12(厚度0.5-3μm)键合到包含铜箔的内导体层10(厚度10-100μm)的两侧而形成。在内导体层10两侧形成包含铜镀层的外导体层15、16(厚度10-100μm),内导体层10介于包含树脂的绝缘层13、14中间。基板通过用包含铜的柱状导体17、18(厚度10-100μm)把内导体层10和外导体层15、16电连接起来。并且,多层印刷电路板通过在外导体层15、16的表面制作图形而形成。
其次,解释上述多层印刷电路板的制造方法。
首先,通过在铜箔19(厚度10-100μm)两侧上形成将成为蚀刻停止层11、12的镍镀层20、21来制备镀镍铜箔22,当多层印刷电路板完成时铜箔19为内导体层(见图1)。
如图8所示,镀镍铜箔22绕在包层板制造设备的反绕轮(rewinding reel)23上,同时把将成为柱状导体17的铜箔24绕在反绕轮25上。
镀镍铜箔22和铜箔24同时从反绕轮23、25上解开,它们部分绕在凸出地安装在蚀刻室26中的电极轮27、28上,然后它们在蚀刻室26中用溅射-蚀刻处理活化。
在此情形中,活化处理按如下执行:
①在1×10-1-1×10-4乇的超低压不活泼(inert)气体气氛中;
②电极A和其它绝缘固定的电极B之间的辉光-放电充电交流电流为1-50MHz,电极A包括分别电接地的具有接触表面的镀镍铜箔22和铜箔24;
③溅射蚀刻;
④暴露在由所述辉光放电产生的等离子体中的电极面积不大于电极B面积的1/3。
此后,它们通过安装在真空室29中的滚动单元30进行冷压接合,随后具有3个分层结构的用于印刷电路板的包层板31绕反绕轮32拉紧。
然后,具有3个分层结构的用于印刷电路板的包层板31再次绕在反绕轮23上,同时把将成为柱状导体18(见图1)的铜箔33绕在反绕轮25上。包层板31和铜箔33分别从反绕轮23、25上同时解开,它们部分绕在凸出地安装在蚀刻室26中的电极轮27、28上,然后它们在蚀刻室26中用溅射-蚀刻处理活化。
在此情形中,活化处理也按如下执行:
①在1×10-1-1×10-4乇的超低压不活泼气体气氛中;
②电极A和其它绝缘固定的电极B之间的辉光-放电充电交流电流为1-50MHz,电极A包括分别电接地的具有接触表面的用于印刷电路板的包层板31和铜箔33;
③溅射蚀刻;
④暴露在由所述辉光放电产生的等离子体中的电极面积不大于电极B面积的1/3,由此用于印刷电路板的包层板34具有5层结构。
进一步地,以铜/镍/铜/镍/铜的次序、由铜层作为顶层和底层并且中间插有镍层作为中间层而形成的多层包层板可以使用上述设备通过重复压力接合来制造。
而且,多层包层板可通过单次压力接合形成:安装3个或更多上述反绕轮、在这些轮上制备铜箔和镍箔并同时从3个或更多的这些反绕轮提供箔。
然后,在用于印刷电路板的包层板34切成需要的尺寸之后,根据参照图2-7进行解释的下述工艺制造多层印刷电路板。
首先,光刻胶膜35、36在如图2所示的铜箔24、33上形成之后,把它们曝光和显影。
接着,如图3所示,有选择性地蚀刻铜箔24、33,以使除了柱状导体17、18之外的部分被除去。
随后,在镍镀层20上形成光刻胶膜37之后,把它们曝光和显影,进而把树脂38涂覆在镍镀层21表面上,以形成如图4所示的绝缘层14。
然后,如图5所示,通过使用加有过氧化氢的氯化铁或硫酸来蚀刻镍镀层20、铜箔19、镍镀层21,从而形成基板芯。
此后,如图6所示,在基板芯的表面上涂覆树脂39以形成绝缘层13,把树脂表面抛光以获得均匀的表面。在此情况下,柱状导体17的顶部应被露出。
然后,在把树脂表面38、39(见图6)粗糙化之后,在粗糙表面上通过无电镀铜或电解镀铜而形成外导体层16、15。接着,对外导体层15、16制作图形。由此形成电路。
如上所述,在根据本发明第1-3任一方面的用于印刷电路板的包层板中,用于印刷电路板的包层板是通过压力接合铜箔和镍箔、或压力接合层叠状态的在其一侧或两侧上有镍镀层的铜箔和其它铜箔或在其一侧上有镍镀层的铜箔来制造,因此,在蒸发制造中由于可避免产生孔而提高了用于印刷电路板的包层板的质量,并且因依靠压力接合层叠的箔而能降低制造成本。进一步地,可通过把接合面应力控制到低水平来保证接合面的平面度,因为压力接合有较低的压缩率0.1-3%,并且因不需要恢复可成形性的热处理,在界面上不会生成任何合金,所以,使用这些用于印刷电路板的包层板可以制造具有优良的选择性蚀刻能力的多层印刷电路板。
在根据本发明第4方面的多层印刷电路板的制造方法中,通过选择性地蚀刻上述用于印刷电路板的包层板以形成基板时,在其表面上制作图形,并且导体层之间的电连接通过插入经蚀刻而在所述导体层中形成的柱状导体来完成,这样,具有高度集成电路的多层印刷电路板就可有效和经济地制造。
在根据本发明第5方面的多层印刷电路板的制造方法中,通过层叠用作导体层的铜箔和用作蚀刻停止层的镍镀层,并同时压力接合两者来形成用于印刷电路板的包层板,接着通过有选择性地蚀刻多层包层板来制造基板,然后,通过树脂涂覆、电镀并制作图形来制造该基板,而且所述导体层之间的电连接通过插入经蚀刻而在导体层中形成的柱状导体来完成,由此制成多层印刷电路板,这样,具有高度集成电路的多层印刷电路板就可有效和经济地制造。
在根据本发明第6方面的多层印刷电路板的制造方法中,当通过在真空室预先活化处理铜箔和镍镀层的接触表面,随后层叠铜箔和所述镍镀层,然后以0.1-3%压缩率冷压接合两者而形成多层包层板时,可通过把接合面应力控制到低水平来保证接合面的平面度,并且因不需要恢复可成形性的热处理,故在界面上不会生成任何合金,所以,可以用这些多层包层板制造具有优良的有选择性蚀刻能力的多层印刷电路板。
Claims (3)
1.一种多层印刷电路板,其中包括一个基板,
所述基板的基板芯包括一个由铜箔(19)构成的内导体层(10),还包括在内导体层(10)的两侧上形成的作为蚀刻停止层的镍镀层(11,12),
在所述基板芯的表面上形成包含树脂的绝缘层(13,14),以及
在所述绝缘层(13,14)的两侧上形成包括铜镀层的外导体层(15,16),并且
内导体层(10)通过包含铜的柱状导体(17,18)电连接到外导体层(15,16),从而共同构成所述基板,
其中,所述外导体层(15,16)被构图。
2.一种多层印刷电路板的制造方法,包括:
a.在包层板的上层和下层铜箔(24,33)上形成、曝光并显影光刻胶膜(35,36),该包层板包括一层中间层铜箔(19)、在该中间层铜箔(19)的两侧上形成的上层和下层镍镀层(20,21)、以及在该上层和下层镍镀层(20,21)上形成的上层和下层铜箔(24,33);
b.在上层和下层铜箔(24,33)上选择性地蚀刻除柱状导体(17,18)的区域以外的部分;
c.在上层镍镀层(20)上形成、曝光并显影一个光刻胶膜(37),并在下层镍镀层(21)的表面上涂覆树脂(38)以形成一个绝缘层(14);
d.通过选择性地蚀刻上层镍镀层(20)、中间层铜箔(19)和下层镍镀层(21)形成一个内导体层(10);
e.利用树脂(39)涂覆所述内导体层(10)的表面,以形成覆盖了柱状导体的绝缘层(13),并抛光该绝缘层(13),使得所述柱状导体(17)的顶部被露出;
f.利用铜来涂覆下方的绝缘层(13)的表面以形成外导体层(15,16);并且
g.对所述外导体层(15,16)进行构图。
3.一种如权利要求2所述的多层印刷电路板的制造方法,其特征在于包括以下步骤:
①.通过在所述中间层铜箔(19)的两侧镀上所述上层和下层镍镀层(20,21),形成一个镀镍铜箔(22);
②.在真空室中,在1×10-1-1×10-4乇的超低压不活泼气体气氛中对上层铜箔(24)和镀镍铜箔(22)的接触表面进行预先活化处理,其中所述上层铜箔(24)和镀镍铜箔(22)形成了第一个电极A,并且所述上层铜箔(24)和镀镍铜箔(22)的接触表面分别接地,在所述的第一个电极A和绝缘固定的第一个电极B之间对1-50MHz的充电交流电流进行辉光-放电,并且以暴露在由辉光放电产生的等离子体中的电极面积不大于第一个电极B面积的1/3的方式进行溅射蚀刻;
③.然后以0.1-3%的压缩率对所述上层铜箔(24)和镀镍铜箔(22)进行冷压接合,从而形成一个未完成的包层板(31);
④.在真空室中,在1×10-1-1×10-4乇的超低压不活泼气体气氛中对所述未完成的包层板(31)和下层铜箔(33)的接触表面进行预先活化处理,其中所述未完成的包层板(31)和下层铜箔(33)形成了第二个电极A,并且所述未完成的包层板(31)和下层铜箔(33)的接触表面分别接地,在所述的第二个电极A和绝缘固定的第二个电极B之间对1-50MHz的充电交流电流进行辉光-放电,并且以暴露在由辉光放电产生的等离子体中的电极面积不大于第二个电极B面积的1/3的方式进行溅射蚀刻;
⑤.然后以0.1-3%的压缩率对所述未完成的包层板(31)和下层铜箔(33)进行冷压接合,从而得到了完成后的包层板(31)。
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US5426850A (en) * | 1991-11-29 | 1995-06-27 | Hitachi Chemical Company, Ltd. | Fabrication process of wiring board |
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EP1111975B1 (en) | 2008-04-02 |
EP1111975A4 (en) | 2005-10-26 |
CN1234262C (zh) | 2005-12-28 |
US20020166840A1 (en) | 2002-11-14 |
CN1612678A (zh) | 2005-05-04 |
WO2000005934A1 (fr) | 2000-02-03 |
KR20010071675A (ko) | 2001-07-31 |
MY124084A (en) | 2006-06-30 |
EP1111975A1 (en) | 2001-06-27 |
DE69938456T2 (de) | 2009-04-09 |
AU4798599A (en) | 2000-02-14 |
US6579565B2 (en) | 2003-06-17 |
CN1311977A (zh) | 2001-09-05 |
DE69938456D1 (de) | 2008-05-15 |
US6730391B1 (en) | 2004-05-04 |
KR100615382B1 (ko) | 2006-08-25 |
TW585813B (en) | 2004-05-01 |
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