CN100578536C - 半导体存储卡 - Google Patents

半导体存储卡 Download PDF

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CN100578536C
CN100578536C CN200710004368A CN200710004368A CN100578536C CN 100578536 C CN100578536 C CN 100578536C CN 200710004368 A CN200710004368 A CN 200710004368A CN 200710004368 A CN200710004368 A CN 200710004368A CN 100578536 C CN100578536 C CN 100578536C
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terminal
card terminal
base
ground connection
semiconductor memory
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CN101008990A (zh
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太田洋一
小泽熏
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Toshiba Corp
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Abstract

本发明提供一种连接外部装置并输入输出信号的半导体存储卡，其具备：电路基板，其上表面形成有连接基板布线的基板端子，下表面设有用于向所述外部装置输入输出信号的输入输出卡端子、提供电源的电源卡端子、和通过连接所述外部装置而连接接地电位的接地卡端子；非易失性存储器芯片，放置在所述电路基板的上表面上，接近其第1边形成有多个第1接合焊盘，该第1接合焊盘与沿着所述第1边形成于所述电路基板上的多个第1基板端子引线接合；和控制器芯片，放置在所述非易失性存储器芯片上，形成有多个第2接合焊盘，该多个第2接合焊盘与沿着和所述第1边相邻的所述非易失性存储器芯片的第2边形成于所述电路基板上的多个第2基板端子引线接合，并且该控制器芯片控制所述非易失性存储器芯片。所述电源卡端子或所述接地卡端子具有：通过所述电路基板沿着所述第1基板端子和所述第2基板端子连接所述外部装置的连接部；和从该连接部延伸的延伸部。

Description

半导体存储卡
对相关申请的交叉引用
本发明以在2006年1月24日提出申请的第2006-014616号日本专利申请为基础并对其主张优先权，并且该原专利申请的全部内容通过引用被包含于此。
技术领域
本发明涉及一种具有用于提供电源的电源卡端子和连接接地电位的接地卡端子的半导体存储卡。
背景技术
近年来，安装了非易失性存储器芯片的手机、电脑等正在推进小型轻量化，进而对存储器的大容量化、具有各种功能的产品等的要求在提高。
以xD-Picture(TM)卡为代表的半导体存储卡，主要被用作数字照相机的存储介质。该半导体存储卡的半导体芯片结构需要被用作存储装置的非易失性存储器即闪存、和具备互换性功能以与各种设备进行互换的控制器芯片。
并且，近年来，伴随数字照相机的像素的高分辨率化、长时间的动态图像的获取，在推进半导体存储卡的大容量化。被用作存储介质的半导体存储器芯片通过减小存储器单元的尺寸实现大容量化，但随着存储器单元的进一步细微化变得困难，进一步减小芯片尺寸也变得困难。
另一方面，半导体存储卡的封装体的外形尺寸的规格已确定。在安装与半导体存储卡的外形尺寸相比充分小的芯片时，卡基板具有充足的空间，基板布线的自由度提高，容易进行布线设计。但是，在安装了大容量芯片时，布线空间减小，基板布线设计的自由度受到限制。
并且，为了做到存储器的大容量化、具备各种功能等，需要安装许多半导体芯片。但是，随着产品小型化的推进，安装半导体芯片的电路基板的大小也小型化，层叠安装多个半导体芯片变得困难。
以往的半导体存储卡例如包括以下部分：上部形成有开口部的基础卡；半导体封装体，其包括存储所期望的数据的半导体存储器，在上表面形成有与该半导体存储器电连接并且连接外部装置以输入输出信号的输入输出卡端子、电源卡端子和接地卡端子，该输入输出卡端子、电源卡端子和接地卡端子以通过开口部露出的方式被放置在基础卡内；和封条状的标签，粘接在基础卡的上部，以使输入输出卡端子的至少一部分露出的方式覆盖半导体封装体(例如参照日本专利特开2003-346109号公报)。
在这里，在上述现有技术中，板状的输入输出卡端子、电源卡端子和接地卡端子与半导体封装体的电路基板的基板布线的长度、基板端子的位置等无关，例如仅仅根据xD-Picture(TM)卡所要求的规格简单地并列配置。
因此，例如在基板端子和电源卡端子或接地卡端子分离配置时，从基板端子到电源卡端子或接地卡端子的通孔布线为止的布线长度变长，可能产生不能提高半导体存储卡的响应性、实现低功耗等的问题。另外，由于基板布线结构的复杂化等，存在可能产生基板布线间的交调失真(串扰)的问题。
发明内容
根据本发明的一个方式，提供一种连接外部装置并输入输出信号的半导体存储卡，其具备：电路基板，其上表面形成有连接基板布线的基板端子，下表面设有用于向所述外部装置输入输出信号的输入输出卡端子、提供电源的电源卡端子、和通过连接所述外部装置而连接接地电位的接地卡端子；非易失性存储器芯片，放置在所述电路基板的上表面上，接近其第1边形成有多个第1接合焊盘，该第1接合焊盘与沿着所述第1边形成于所述电路基板上的多个第1基板端子引线接合；和控制器芯片，放置在所述非易失性存储器芯片上，形成有多个第2接合焊盘，该多个第2接合焊盘与沿着和所述第1边相邻的所述非易失性存储器芯片的第2边形成于所述电路基板上的多个第2基板端子引线接合，并且该控制器芯片控制所述非易失性存储器芯片。所述电源卡端子或所述接地卡端子具有：通过所述电路基板沿着所述第1基板端子和所述第2基板端子连接所述外部装置的连接部；和从该连接部延伸的延伸部。
附图说明
图1是表示本发明的实施例1涉及的半导体存储卡的主要部分的结构的俯视图。
图2是表示本发明的实施例1涉及的半导体存储卡的电路基板的布线的主要部分的结构的俯视图。
图3是表示本发明的实施例1涉及的半导体存储卡的电路基板的端子结构的俯视图。
图4是表示本发明的实施例1涉及的半导体存储卡的外观的图。
具体实施方式
以下参照附图说明适用了本发明的各个实施例。另外，为了简化起见，以层叠了一个非易失性存储器芯片和一个控制器芯片的情况为例进行说明。
(实施例1)
图1是表示本发明的实施例1涉及的半导体存储卡的主要部分的结构的俯视图。另外，在图1中为了便于说明，省略了在电路基板上密封非易失性存储器芯片、控制器芯片等的密封树脂。
如图1所示，连接外部装置(未图示)并输入输出信号的半导体存储卡100具备：大致矩形的电路基板3，其上表面形成有连接基板布线的第1、第2基板端子1、2；大致矩形的非易失性存储器芯片6，其被放置在该电路基板3的上表面上，接近其第1边6a形成有多个第1接合焊盘4，该第1接合焊盘4与沿着第1边6a形成于电路基板3上的多个第1基板端子1通过接合线5引线接合；和大致矩形的控制器芯片9，其被放置在该非易失性存储器芯片6上，形成有多个第2接合焊盘7，该多个第2接合焊盘7与沿着和第1边6a相邻的非易失性存储器芯片6的第2边6b形成于电路基板3上的多个第2基板端子2通过接合线8引线接合，并且该控制器芯片9控制非易失性存储器芯片6。
第1基板端子1包括：非易失性存储器输入输出基板端子1a，用于向非易失性存储器芯片6输入输出包括地址、命令和输入输出数据的数据输入输出信号；非易失性存储器控制基板端子1b，用于从控制器芯片9向非易失性存储器芯片6输入控制非易失性存储器芯片6的控制信号；和电源基板端子1c，用于从外部向非易失性存储器芯片6提供电力。
例如，在非易失性存储器芯片6为NAND型闪存时，控制非易失性存储器芯片6的控制信号包括：用于强制禁止写入和擦除的WP(WriteProtect)信号；用于写入数据的WE(Write Enable)信号；用于控制地址、数据的取入的ALE(Address Latch Enable)信号；用于控制命令的取入的CLE(Command Latch Enable)信号；使处于动作状态的CE(ChipEnable)信号；用于输出数据的RE(Read Enable)信号；和用于将动作状态通知外部的RB(Ready Busy)信号。
并且，第2接合焊盘7沿着控制器芯片9的长边9a的一边形成。另外，在能够设置第2接合焊盘7的情况下，也可以进一步沿着与长边9a相对的边形成，以便可以布线于非易失性存储器芯片6的两侧。
第2基板端子2包括：用于从外部向控制器芯片9提供电力的电源基板端子2a；通过连接外部装置而连接接地电位的接地基板端子2b；在电路基板3上向非易失性存储器控制基板端子1b进行了布线的第1存储器侧接口基板端子2c；与外部端子连接，进行数据输入输出信号和控制信号的输入输出的主机侧接口基板端子2d；在电路基板1上向非易失性存储器输入输出基板端子1a进行了布线的第2存储器侧接口基板端子2e。
并且，第2基板端子2在电路基板3上沿着第2边6b并列配置成大致扇形状。由此，能够使从各个第2基板端子2到第2接合焊盘7的布线距离更加均等。
并且，第2基板端子2在电路基板3上沿着第2边6b交替地并列着交错配置成两列，以便不使所连接的各个接合线8接触。由此，与配置成一列时相比，能够确保第2基板端子2具有所需要的面积，并配置在接近控制器芯片9的长边9a的区域。
在这里，例如在进行读出动作时，从控制器芯片9输出的数据输入输出信号如前面所述包括地址、命令，根据该数据输入输出信号指定非易失性存储器芯片6的物理地址块，并设定为能够读出该地址块的状态。并且，根据从控制器芯片9输出的控制信号，非易失性存储器芯片6从所指定的该地址块，从非易失性存储器输入输出基板端子1a输出规定的数据。
在控制这种一系列的读出动作时，需要在控制信号之前向非易失性存储器芯片6输入数据输入输出信号。并且，在控制其他的写入等动作时也存在相同要求。
因此，第2存储器侧接口基板端子2e相比第1存储器侧接口基板端子2c被配置得更靠近非易失性存储器芯片6的第1边6a。由此，能够缩短非易失性存储器输入输出基板端子1a和第2存储器侧接口基板端子2e之间的布线长度，能够降低数据输入输出信号的信号延迟。
在电路基板3的上表面，在接合、布线了第1基板端子1、第2基板端子2等的区域之外，成膜有抗焊剂10，形成于电路基板3的基板布线等被绝缘。
接合线5、8例如选择金线。在进行这些接合线5、8的引线接合时，向各个第1、第2接合焊盘4、7施加超声波振动。
下面，说明上述电路基板3的布线结构。
图2是表示本发明的实施例1涉及的半导体存储卡的电路基板的基板布线的主要部分结构的俯视图。此处，说明基板布线为1层时的情况。另外，在图2中，为了便于说明，省略了抗焊剂、与本发明的结构无关的基板布线、通孔布线等。
如图2所示，电源基板端子1c和通孔布线11通过基板布线12相连接。电源基板端子2a和通孔布线13通过基板布线14相连接。并且，接地基板端子2b和通孔布线15、16通过基板布线17相连接。
并且，第1存储器侧接口基板端子2c和非易失性存储器控制基板端子1b通过基板布线18相连接，第2存储器侧接口基板端子2e和非易失性存储器输入输出基板端子1a通过基板布线19相连接。并且，主机侧接口基板端子2d和通孔布线20通过基板布线21相连接。
如上所述，第2存储器侧接口基板端子2e相比第1存储器侧接口基板端子2c被配置得更靠近非易失性存储器芯片6的第1边6a，所以能够使基板布线19的布线长度短于基板布线18的布线长度。
另外，虽然第2存储器侧接口基板端子2e尽量接近第1边6a配置比较好，但此处由于半导体存储卡的规格关系，通孔20的配置受到限定，考虑到布线情况，将主机侧接口基板端子2d配置在第2存储器侧接口基板端子2e之间。通过该主机侧接口基板端子2d输入输出的信号，通过通孔20输入输出到电路基板1的背面侧。
下面，说明从主机侧接口基板端子配置在电路基板的背面侧的卡端子的结构和向该卡端子输入输出的信号等。
图3是表示在本发明的实施例1涉及的半导体存储卡的电路基板的背面侧形成的卡端子的概况的俯视图。此处，说明非易失性存储器为NAND型闪存的情况。
如图3所示，在电路基板3的背面(下表面)侧设有：向外部装置输入输出信号的输入输出卡端子22；用于提供电源的电源卡端子23；和通过连接外部装置而连接接地电位的接地卡端子24。
电源卡端子23形成为大致L字型，具有：通过图2中的电路基板3沿着第1基板端子1的连接外部装置的连接部23a；和通过电路基板3沿着第2基板端子2的从连接部23a延伸的延伸部23b。另外，电源卡端子23根据半导体存储卡的规格、电路基板的布线结构等，也可以形成为其连接部23a通过电路基板3沿着第2基板端子2、其延伸部23b通过电路基板3沿着第1基板端子的大致L字型。
接地卡端子24也形成为大致L字型，具有：连接外部装置的连接部24a；和以通过电路基板3沿着第2基板端子2的方式从该连接部24a延伸的延伸部24b。
并且，接地卡端子24形成为使延伸部24b的宽度Y比连接外部装置的连接部24a的宽度X宽。
由此，能够获得相对于形成有基板布线的信号布线层即电路基板3仅单面配置接地布线层即接地卡端子22的微型带结构。该微型带结构中的接地卡端子22实现稳定的特性电阻值，并且具有实现低噪声(降低基板布线之间的交调失真)的重要作用。
接地卡端子24的延伸部24b形成有梳齿状的多个切槽24c。此处，例如形成有对应根据半导体存储卡的规格配置的各个输入输出端子22的间隔的切槽24c。这样，延伸部24b的相邻切槽24c之间的距离A与输入输出端子22的宽度B相同。
由此，在面积大于其他端子的接地卡端子24的延伸部24b中，例如能够降低由于引线接合时的加热而产生的应力。即，能够增大延伸部24b的宽度实现前面叙述的微型带结构，降低由于加热产生的应力，提高接合性、提高电路基板和非易失性存储器芯片的紧密接触性。
并且，由于接地卡端子24的延伸部24b的宽度比连接部24a的宽度宽，所以能够降低布线电阻。
并且，如前面所述，在电路基板3上形成有用于连接电源卡端子23、接地卡端子24和第1、第2基板端子1、2的通孔布线11、13、15、16。第1基板端子1的电源基板端子1c和电源卡端子23的连接部23a通过基板布线12、邻近的通孔布线11相连接。第2基板端子2的电源基板端子2a和电源卡端子23的延伸部23b通过基板布线14、邻近的通孔布线13相连接。
并且，第2基板端子2的接地基板端子2b和接地卡端子24的连接部24a通过基板布线17、邻近的通孔布线16相连接。第2基板端子2的接地基板端子2b和接地卡端子24的延伸部24b通过基板布线17、邻近的通孔布线15相连接。
这样，各个基板端子1、2和电源卡端子23、接地卡端子24以更短的距离相连接，能够降低基板布线12、14、16、17中的损耗。
另外，也可以根据半导体存储卡的规格、电路基板的布线结构等，以使接地卡端子沿着第1基板端子和第2基板端子的方式设置连接部和延伸部。
此处，如图3所示，各个卡端子例如被分配了VCC、VSS、I/O-0～I/O-7、RB(Ready/Busy)、RE(Read Enable)、CE(Chip Enable)、CLE(Command Latch Enable)、ALE(Address Latch Enable)、WE(Write Enable)、WP(Write Protect)。
被分配了VCC的电源卡端子23是用于提供电源电位(VCC)的VCC输入用卡端子。被分配了VSS的接地卡端子24即卡端子是用于提供接地电位(VSS)的VSS输入用卡端子。
并且，被分配了I/O-0～I/O-7的输入输出卡端子22是用于输入输出地址、命令、输入输出数据的卡端子。
并且，被分配了RB的输入输出卡端子22是用于将半导体存储卡内部的动作状态通知外部的输出用卡端子。被分配了RE的输入输出卡端子22是串行输出数据的输出用卡端子。被分配了CE的输入输出卡端子22是用于获取设备选择用信号的输入用卡端子。
并且，被分配了CLE的输入输出卡端子22是输入用于控制向半导体存储卡内部的命令寄存器(未图示)取入动作命令的信号的卡端子。被分配了ALE的输入输出卡端子22是输入用于控制向半导体存储卡内部的地址寄存器和数据寄存器(均未图示)取入地址数据和输入数据的信号的卡端子。
并且，被分配了WE的输入输出卡端子22是输入用于从I/O输入输出卡端子向半导体存储卡的内部取入各个数据的信号的卡端子。被分配了WP的输入输出卡端子22是输入用于强制禁止写入、擦除动作的信号的卡端子。
另外，被输入输出给I/O-0～I/O-7的输入输出卡端子22的信号相当于前面叙述的数据输入输出信号。并且，分别输入RB、RE、CE、CLE、ALE、WE和WP的卡端子的信号，通过控制器芯片进行处理，根据该处理结果生成前面叙述的控制信号。
下面，说明具有上述内部结构的半导体存储卡100的外观。图4是表示本发明的实施例1涉及的半导体存储卡的外观(下表面侧)的图。
如图4所示，半导体存储卡100将连接有输入输出卡端子22、电源卡端子23和接地卡端子24的电路基板收纳在罩体25中，通过将绝缘性封条26等粘贴在规定位置而完成。
如前面所述，输入输出卡端子22与外部装置的外部端子连接，输入输出所期望的信号。并且，从外部装置提供的电力，通过电源卡端子23、电路基板的基板布线等提供给非易失性存储器芯片、控制器芯片。并且，接地卡端子24通过与外部装置的外部端子连接而接地。
如上所述，根据本实施例涉及的半导体存储卡，能够提高响应性、实现低功耗，并且能够降低基板布线之间的交调失真。
另外，在本实施例中，说明了在电路基板上安装一个非易失性存储器芯片的情况，但在层叠了多个非易失性存储器芯片时，也能够发挥相同的作用效果。
并且，在本实施例中，说明了电源卡端子、接地卡端子具有大致L字型形状的情况，但根据卡端子的规格、布线等，例如也可以具有大致T字型等的形状。

Claims (12)

1.一种半导体存储卡，是连接外部装置并输入输出信号的半导体存储卡，其特征在于，具备：
电路基板，其上表面形成有连接基板布线的基板端子，下表面设有用于向所述外部装置输入输出信号的输入输出卡端子、用于提供电源的电源卡端子、和通过连接所述外部装置而连接接地电位的接地卡端子；
非易失性存储器芯片，其被放置在所述电路基板的上表面上，接近其第1边形成有多个第1接合焊盘，该第1接合焊盘与沿着所述第1边形成于所述电路基板上的多个第1基板端子引线接合；和
控制器芯片，其被放置在所述非易失性存储器芯片上，形成有多个第2接合焊盘，该多个第2接合焊盘与沿着和所述第1边相邻的所述非易失性存储器芯片的第2边形成于所述电路基板上的多个第2基板端子引线接合，并且该控制器芯片控制所述非易失性存储器芯片；
其中，所述电源卡端子或所述接地卡端子，以通过所述电路基板沿着所述第1基板端子和所述第2基板端子的方式，具有连接所述外部装置的连接部，和从该连接部延伸的延伸部，所述连接部和所述延伸部在所述电路基板的下表面形成，并通过基板布线和通孔布线与所述第1基板端子或所述第二基板端子连接。
2.根据权利要求1所述的半导体存储卡，其特征在于，
所述电源卡端子具有：通过所述电路基板沿着所述第1基板端子的连接所述外部装置的所述连接部；和通过所述电路基板沿着所述第2基板端子的从所述连接部延伸的所述延伸部，
所述接地卡端子具有：连接所述外部装置的所述连接部；和通过所述电路基板沿着所述第2基板端子的所述延伸部，该延伸部的宽度形成为比所述接地卡端子的所述连接部的宽度宽。
3.根据权利要求2所述的半导体存储卡，其特征在于，在所述接地卡端子的所述延伸部形成有梳齿状的多个切槽。
4.根据权利要求3所述的半导体存储卡，其特征在于，所述延伸部的相邻的所述切槽间的宽度与所述输入输出卡端子的宽度相同。
5.根据权利要求2所述的半导体存储卡，其特征在于，在所述电路基板上形成有：第1通孔布线，其用于连接所述电源卡端子或所述接地卡端子的所述连接部与所述第1基板端子；和第2通孔布线，其用于连接所述电源卡端子或所述接地卡端子的所述延伸部与所述第2基板端子。
6.根据权利要求3所述的半导体存储卡，其特征在于，在所述电路基板上形成有：第1通孔布线，其用于连接所述电源卡端子或所述接地卡端子的所述连接部与所述第1基板端子；和第2通孔布线，其用于连接所述电源卡端子或所述接地卡端子的所述延伸部与所述第2基板端子。
7.根据权利要求4所述的半导体存储卡，其特征在于，在所述电路基板上形成有：第1通孔布线，其用于连接所述电源卡端子或所述接地卡端子的所述连接部与所述第1基板端子；和第2通孔布线，其用于连接所述电源卡端子或所述接地卡端子的所述延伸部与所述第2基板端子。
8.根据权利要求1所述的半导体存储卡，其特征在于，所述电源卡端子或所述接地卡端子具有大致为L字型的形状。
9.根据权利要求2所述的半导体存储卡，其特征在于，所述电源卡端子或所述接地卡端子具有大致为L字型的形状。
10.根据权利要求3所述的半导体存储卡，其特征在于，所述电源卡端子或所述接地卡端子具有大致为L字型的形状。
11.根据权利要求4所述的半导体存储卡，其特征在于，所述电源卡端子或所述接地卡端子具有大致为L字型的形状。
12.根据权利要求5所述的半导体存储卡，其特征在于，所述电源卡端子或所述接地卡端子具有大致为L字型的形状。
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