CN100570881C - 影像感测器 - Google Patents
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- CN100570881C CN100570881C CNB2007100895153A CN200710089515A CN100570881C CN 100570881 C CN100570881 C CN 100570881C CN B2007100895153 A CNB2007100895153 A CN B2007100895153A CN 200710089515 A CN200710089515 A CN 200710089515A CN 100570881 C CN100570881 C CN 100570881C
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Abstract
本发明提供一种影像感测器,包括:一感测元件,形成于一半导体基底中;一层间介电层,形成于该半导体基底中;一导电元件,位于该层间介电层中;以及一掺杂铝的接面,形成于该层间介电层中,且在水平方向位于该感测元件的周围。本发明所述的影像感测器,由于掺杂铝的深隔离壁宽度窄且深度深,故其占据半导体基底较小的面积却又能有效的隔离元件。
Description
技术领域
本发明是有关于一种感测器的构造及其制造方法,且特别有关于一种具有掺杂铝的接面的感测器的构造及其制造方法。
背景技术
在半导体技术中,影像感测器(image sensor)包括形成于半导体基底中的多个感测元件或像素,感测元件是用于感测投射至半导体基底的光线。感测元件可形成于基底的前表面,而光可投射至基底的前表面或后表面以传达至感测元件,通过光投射至感测元件即可产生电信号,然而电信号可能分散至其他感测元件而产生干扰(crosstalk)。因此,目前亟需一种改善影像感测器及/或其基底的结构及制造方法。
发明内容
本发明的目的在于提供一种影像感测器的结构及半导体装置的制造方法,其具有掺杂铝的接面,借此可有效的消除电干扰。
本发明提供一种影像感测器,包括:一基底,其具有一前表面及一后表面,其中该基底包括晶体方向为<100>或<111>的晶体硅;多个感测元件,形成于该基底的该前表面上,所述感测元件是用以接受入射至该后表面的光;以及一铝掺杂区,形成于该基底中,在水平方向位于相邻的感测元件之间,在垂直方向位于该后表面及所述感测元件之间。
本发明所述的影像感测器,其中该铝掺杂区的铝掺杂浓度约介于1013atoms/cm3至1020atoms/cm3。
本发明所述的影像感测器,其中所述感测元件是选自互补式金属氧化物半导体影像感测器、电荷耦合元件、主动感测器、被动感测器及其组合所组成的群组。
本发明又提供一种影像感测器,包括:一感测元件,形成于一半导体基底中;一层间介电层,形成于该半导体基底中;一导电元件,位于该层间介电层中;以及一掺杂铝的接面,形成于该层间介电层中,且在水平方向位于该感测元件的周围。
本发明所述的影像感测器,其中该掺杂铝的接面的铝掺杂浓度约介于1013atoms/cm3至1020atoms/cm3。
本发明另提供一种半导体元件的形成方法,包括:提供一半导体基底;提供一掩膜层于该半导体基底上;形成一开口于该掩膜层中,该开口暴露该半导体基底;形成一含铝层于该掩膜层上以及该开口中的该半导体基底上;以及经由该掩膜层的该开口扩散该含铝层中的铝至该半导体基底,以在该感测元件的周围形成一掺杂铝的接面。
本发明所述的半导体元件的形成方法,更包括在扩散该含铝层中的铝至该半导体基底之后,移除该含铝层。
本发明所述的半导体元件的形成方法,其中扩散该含铝层中的铝至该半导体基底包括实施一退火制程。
本发明所述的半导体元件的形成方法,其中该退火制程的退火温度约介于400℃至1200℃。
本发明所述的半导体元件的形成方法,其中该退火制程是选自热退火、快速退火、激光退火及其组合所组成的群组。
本发明所述的半导体元件的形成方法,其中形成该含铝层的步骤是选自化学气相沉积法、物理气相沉积法、电镀法及其组合所组成的群组。
本发明所述的影像感测器及半导体元件的形成方法,由于掺杂铝的深隔离壁宽度窄且深度深,故其占据半导体基底较小的面积却又能有效的隔离元件。
附图说明
图1-图7是绘示本发明实施例的具有掺杂铝的深接面(deep junction)的背部受光型(backside illuminated)影像感测器及其制造方法;
图8是绘示本发明另一实施例的具有掺杂铝的深接面(deep junction)的正面受光型(front illnminated)影像感测器的剖面图。
具体实施方式
以下将揭露多个不同的实施例以实施各种实施例的不同特征,以下说明特定实施例中的元件及排列方法以简化说明,其仅用以作为示例而非用以限定本发明。并且相同或类似的元件在不同的实施例中将以相同或类似的标号标示,并且当叙述一第一元件形成于一第二元件上,包含该第一元件直接接触形成于该第二元件上,或者该第一元件与该第二元件之间还有额外的元件。
以下将配合图1-图7说明本发明实施例的具有掺杂铝的深接面(deep junction)的背部受光型(backside illuminated)影像感测器及其制造方法。请参照图1,其是绘示本发明实施例的剖面图,首先提供半导体元件100,其具有多个背部受光型感测元件。
半导体元件100包括半导体基底110,半导体基底110包括结晶硅,较佳者半导体基底110为具有<100>或<110>晶体方向的硅,其在垂直于半导体基底110平面的方向相较于其他方向具有较高的铝扩散速度。半导体基底110亦可包括其他元素半导体,例如锗,或包括化合物半导体,例如碳化硅、砷化镓、砷化铟及磷化铟。在本实施例中,半导体基底110在某方向上相较于其他方向具有最高的铝扩散速度。半导体基底110可包括各种p型掺杂区及/或n型掺杂区用以形成各种功能的元件及装置。上述的掺杂步骤可通过如离子注入或扩散等方法。半导体基底110亦可包括其他元件,如外延层、硅覆盖绝缘层(SOI)基底或其组合。
半导体元件100包括感测元件(或像素)120,其形成于半导体基底110的前表面上及/或半导体基底110内。在一实施例中,感测元件120设置于半导体基底110的前表面上并延伸至半导体基底110内。感测元件120包括感光区(或影像感测区),感光区是通过如扩散或离子注入等掺杂方法,以于半导体基底110中形成n型或p型掺杂区。感光区的掺杂浓度约介于1014atoms/cm3至1021atoms/cm3,而感光区的表面积约为其对应的感测元件面积的10%至80%,感光区的表面积范围可依据需求调整以接受光(或来自欲成像物体的辐射线)。感测元件120例如为光二极管(photodiodes)、互补式金属氧化物半导体(CMOS)影像感测器、电荷耦合元件(CCD)、主动感测器、被动感测器及/或其他形成于或扩散至半导体基底110的元件。感测元件120可包括已知或未来发展的影像感测元件。
半导体元件100可包括多个以阵列形式或其他形式排列的感测元件,这些感测元件可为各种感测形式,举例而言,一些感测元件可为CMOS影像感测器,而另一些感测元件可为被动感测器。并且,感测元件120可包括彩色影像感测器或单色影像感测器。半导体元件100在运作时可接受入射至半导体基底110的后表面的光(或辐射线)125,借此可消除由如栅极元件或金属元件等物体对光路径造成的阻碍,并且可使感光区对于照射光的暴露面积增加至最大。半导体基底110是相对薄以便于使来自其后表面的光有效率的到达感测元件120。
半导体元件100更包括耦合至感测元件120的多层内连线结构(MLI)130,感测元件120可借此响应照射光。多层内连线结构130可形成于半导体基底110上并置于其前表面以及感测元件120上。多层内连线结构130可包括导电材料,例如铝、铝/硅/铜合金、钛、氮化钛、钨、多晶硅、金属硅化物(metal silicide)或其组合。多层内连线结构130较佳为铝内连线,铝内连线的形成方法可通过物理气相沉积法(如溅镀法)、化学气相沉积法或其组合,其他形成铝内连线的制程包括光刻及蚀刻制程以图案化导电材料,借以形成垂直(如介层窗或接触窗)或平行的连线(如导线)。而具有金属硅化物的多层内连线结构130可通过热退火制程形成,或者多层内连线结构130可为铜多层内连线结构,其包括铜、铜合金、钛、氮化钛、钨、多晶硅、金属硅化物(metal silicide)或其组合,铜多层内连线结构可通过化学气相沉积法、溅镀法或其他适合的方法形成。多层内连线结构的金属硅化物可包括硅化镍、硅化钴、硅化钨、硅化钽、硅化钛、硅化铂、硅化铒、硅化钯或其组合。
半导体元件100包括层间介电层(ILD)140,用以绝缘形成于其中的多层内连线结构130。层间介电层140可为低介电常数材料,例如介电常数小于约3.5的介电材料。层间介电层140可包括二氧化硅、氮化硅、氮氧化硅、聚亚醯胺(polyimide)、旋涂式玻璃(SOG)、氟硅玻璃(FSG)、掺杂碳的氧化硅、Black(加州Santa Clara应用化学公司制造)、干凝胶(Xerogel)、气凝胶(Aerogel)、掺氟的非晶系碳(amorphousfluorinated carbon)、聚对二甲基苯(parylene)、苯并环丁烯树脂(BCB,bis-benzocyclobutenes)、SiLK(美国DowChemical公司制造)及/或其他适合的材料。层间介电层140可通过旋涂式(spin-on)沉积法、化学气相沉积法、溅镀法或其他适合的方法形成。多层内连线结构130及层间介电层140可通过整合制程形成,例如镶嵌(damascene)制程或光刻/等离子蚀刻制程。
请参照图2,于半导体基底110的后表面上形成掩膜层150,以作为后续铝扩散制程中的扩散阻挡层,掩膜层150可包括氧化硅、氮化硅、氮氧化硅、其他适合的介电材料及其组合。掩膜层150可更包括阻障材料,如钛、氮化钛、钽或氮化钽。掩膜层150可为多层结构以作为有效的掩膜层,举例而言,掩膜层150为钛、氮化钛及氧化硅薄膜的叠层。掩膜层150需具有足够的厚度以阻挡铝的扩散,其可通过热处理形成,例如热氧化法或热氮化法,或者可通过旋转涂布法(spin-on coating)、化学气相沉积法、物理气相沉积法或其组合形成。在一实施例中,可先以溅镀法形成钛/氮化钛薄膜,再以化学气相沉积法于钛/氮化钛叠层上形成氧化硅。
请参照图3-图4,图案化掩膜层150以形成多个开口160,并暴露出开口160中的半导体基底110,开口160形成的位置是对应于后续欲形成于半导体基底110中的掺杂铝的深隔离壁(wall)的区域。如图4所示,由俯视图可知开口160是形成于邻近的感测元件120之间,并且开口160大致包围感测元件120。开口160可为各种的尺寸及形状,举例而言,包围感测元件120的开口160可为圆形或方形,其宽度W的范围约介于0.1微米至5微米。开口160可通过光刻制程以及如干蚀刻(等离子蚀刻)或湿蚀刻的蚀刻制程形成。在一实施例中,于掩膜层150上形成光致抗蚀剂层,接着以光刻制程图案化光致抗蚀剂层以于光致抗蚀剂层中形成开口,之后实施等离子蚀刻以蚀刻在光致抗蚀剂层开口中暴露的掩膜层,并以如湿剥除(wet stripping)或等离子灰化法移除光致抗蚀剂层。
请参照图5,在图案化的掩膜层150上以及开口160中的半导体基底110上形成含铝层170。含铝层170可另包含其他材料,例如含有少许比例的硅以形成可改善性质的硅/铝合金。含铝层170的厚度以大于约1000埃为佳,其可通过化学气相沉积法、物理气相沉积法、电镀法或其组合形成,在一实施例中,含铝层170是通过溅镀法形成。可选择性的利用如化学机械研磨法(CMP)的制程移除图案化掩膜层150上的含铝层170,如此含铝层170仅留在掩膜层150的开口160中的半导体基底110上。
请参照图6,实施热处理以扩散含铝层170中的铝至掩膜层150的开口160中的半导体基底110中,借此在半导体基底110中以及在邻近的感测元件120之间形成掺杂铝的深隔离壁180。掺杂铝的深隔离壁180大致上形成在半导体基底110的后表面与感测元件120之间,在一实施例中,其可延伸至邻近层间介电层140的区域。掺杂铝的深隔离壁180的铝浓度约介于1013atoms/cm3至1020atoms/cm3。扩散铝的热处理方法可包括如利用快速高温退火(RTP)机台进行快速高温退火或利用快速退火(flash anne aling)机台进行快速退火的热退火制程,退火温度约介于400℃至600℃。在多层内连线结构130可承受更高温的情况下,退火温度可约介于400℃至1200℃。在其他实施例中,可利用激光退火作为扩散铝的热处理,激光光束聚焦于含铝层170以及开口160中的半导体基底110,如此仅这些部分加热至高温,而不会导致其他部分的半导体元件过热,例如多层内连线结构130。退火时间可持续几分钟至数十个小时,取决于所欲形成的掺杂铝的深隔离壁180的高度D。如前所述,由于在本实施例中的半导体基底110是晶体方向为<100>或<110>的硅基底,因此铝的扩散速度在垂直于基底的方向较其他侧向方向快,借此掺杂铝的深隔离壁180就不会过于向侧边形成。掺杂铝的深隔离壁180的高度D则由半导体基底110的厚度决定,较佳者掺杂铝的深隔离壁180的高度D是大于半导体基底110的厚度的四分之一,举例而言,半导体基底110的厚度约为4微米,掺杂铝的深隔离壁180的高度则约大于1微米。掺杂铝的深隔离壁180的深/宽比约大于3左右。
掺杂铝的深隔离壁180是接触深阱的掺杂的半导体基底,其形成深接面并作为隔离元件,借此在影像感测器运作时由成像辐射线所产生的电信号因被隔离,而只存在一个感测元件中且不会分散至其他感测元件,掺杂铝的深隔离壁180的形成可消除影像感测器在操作时的电干扰(electrical crosstalk)。在其他实施例中,掺杂铝的深隔离壁180可延伸至多层内连线结构130的导电元件,以于深隔离壁施加偏压借此增加隔离效果。
请参照图7,在形成掺杂铝的深隔离壁180之后,可通过适合的铝蚀刻制程移除含铝层170,举例而言,铝的蚀刻液可包括磷酸、醋酸、硝酸、氢过氧化物、水或其组合,并且蚀刻液可加热至室温以上,例如约25℃至100℃。掩膜层150亦可移除以避免影像感测器在操作时掩膜层150会散射及/或吸收光。在其他实施例中,含铝层170及掩膜层150可通过相同的化学机械研磨步骤移除。
掺杂铝的深隔离壁180及借此形成的深接面亦可形成于正面受光型(front illuminated)感测器,如图8所示。半导体元件200包括半导体基底110、多个感测元件120、多层内连线结构130以及层间介电层140,其形成方法、组成与结构与半导体元件100中的元件相似,然而半导体元件200是正面受光型感测器,其接受入射至半导体基底的前表面的光。掺杂铝的深隔离壁180形成于半导体基底110中,并且水平的形成于于邻近的影像感测元件之间,类似于图7中半导体元件100,在垂直方向上,掺杂铝的深隔离壁180大致上在半导体基底110的后表面与感测元件120之间。除了在半导体元件200中掺杂铝的深隔离壁180是形成在半导体基底的前表面中之外,半导体元件200的掺杂铝的深隔离壁180的形成方法大致上类似于在半导体元件100中的形成方法。举例而言,于半导体基底110的前表面上形成掩膜层150,并图案化掩膜层150以在对应邻近的感测元件之间的区域上形成多个开口。含铝层(图中未绘示)形成于层间介电层140上,并且在掩膜层150的开口中的层间介电层140上。接着实施热处理以使含铝层中的铝扩散至半导体基底110中,而形成掺杂铝的深隔离壁180。
在不脱离本发明的精神的情况下,本发明可通过不同的实施例来完成本发明,举例而言,半导体元件100具有多个背部受光型感测元件,其掺杂铝的深隔离壁180可在多层内连线结构130及层间介电层140形成之前先形成,由于在制作掺杂铝的深隔离壁180时,多层内连线结构130还未形成,借此可消除如热预算的问题。或者,感测元件不限定于影像感测器,然其亦可为如热感测器等其他感测元件。掺杂铝的深隔离壁180可以任何形式排列,其目的是为了消除邻近的感测元件之间的电干扰,举例而言,掺杂铝的深隔离壁180可为栅栏(fence)结构,该结构是在邻近的感测元件之间以及每个感测元件周围设置柱(post)。用以扩散铝至半导体基底的热处理制程亦可包括额外的场(field),如电场,以使铝具方向性的扩散至半导体基底。
在上述的结构及方法中,半导体元件100或200所接受的照射光并不限定于可见光,其亦可为任何如红外光(IR)或紫外光(UV)的辐射光束。掺杂铝的深隔离壁180可加以设计或排列,以有效的吸收及/或反射光束。
半导体元件100或200更可包括于多层内连线结构上形成保护(passivation)层,半导体元件100更可包括透明层,其贴附于半导体基底110的后表面,以作为机械性的支撑并使来自后表面的光通过半导体基底110。半导体元件100更可包括在感测元件120及半导体基底110的后表面之间形成彩色滤光器,以作为彩色成像的目的。半导体元件100更可包括在感测元件120及半导体基底110的后表面之间形成多个微透镜(micro-lens),或者若有彩色滤光器形成,微透镜可形成于彩色滤光器及半导体基底110的后表面之间,如此背部照明光可聚焦于感光区。由于掺杂铝的深隔离壁180宽度窄且深度深,故其占据半导体基底较小的面积却又能有效的隔离元件。
本发明的实施例提供一种半导体影像感测器,其包括感测元件,形成于半导体基底中;以及掺杂铝的深接面,形成于半导体基底中,由半导体基底的俯视图来看其水平的设置于感测元件的周围。
在上述半导体影像感测器中,半导体基底可包括结晶硅,较佳者其结晶方向为<100>或<111>。该掺杂铝的深接面的深度约大于1微米,其深/宽比约大于3左右。该半导体影像感测器更包括微透镜,形成于半导体基底中,用以投射成像辐射线至感测元件。掺杂铝的深接面形成在感测元件及微透镜之间。
本发明的实施例提供一种半导体影像感测器,其包括具有前表面及后表面的基底;多个感测元件,形成于基底的前表面上,各感测元件是用以接受入射至基底的后表面的光;以及铝掺杂区,形成于基底中,并设置于相邻的感测元件之间以及基底的后表面与感测元件之间。
在该半导体影像感测器中,铝掺杂区的深/宽比约大于3左右。基底可包括结晶方向为<100>或<111>结晶硅。铝掺杂区的高度约为大于1微米,且铝掺杂浓度约介于1013atoms/cm3至1020atoms/cm3。感测元件是选自互补式金属氧化物半导体(CMOS)影像感测器、电荷耦合元件(CCD)、主动感测器、被动感测器及其组合所组成的群组。
本发明的实施例提供一种半导体影像感测器,其包括感测元件,形成于半导体基底中;层间介电层,形成于半导体基底中;导电元件,形成于层间介电层中;以及掺杂铝的接面,形成于层间介电层中,且由半导体基底的俯视图来看其水平的设置于感测元件的周围。
在该半导体影像感测器中,掺杂铝的接面的深度约大于1微米,其深/宽比约大于3左右,而铝掺杂浓度约介于1013atoms/cm3至1020atoms/cm3。
本发明实施例另提供一种半导体装置的制造方法,其包括提供半导体基底,该半导体基底在某方向具有最高的铝扩散速率;在半导体基底上形成掩膜层;在掩膜层中形成开口,以暴露在开口中的半导体基底;在掩膜层上及开口中的半导体基底上形成含铝层;以及经由掩膜层中的开口扩散于含铝层中的铝至半导体基底,借此掺杂铝的深接面形成于感测元件的周围(由半导体基底的俯视图来看)。
该半导体装置的制造方法更包括在扩散铝之后,移除含铝层。扩散含铝层中的铝至半导体基底的步骤包括退火处理,退火温度可介于400℃至1200℃,退火制程可选自热退火、激光退火及其组合所组成的群组。掩膜层可选自氧化硅、氮化硅、氮氧化硅、钛、氮化钛、钽或氮化钽及其组合所组成的群组。形成掩膜层的方法可选自热氧化法、热氮化法、旋转涂布法(spin-on coating)、化学气相沉积法、物理气相沉积法及其组合所组成的群组。于掩膜层中形成开口的方法可选自等离子蚀刻、湿蚀刻及其组合所组成的群组。形成含铝层的方法可选自化学气相沉积法、物理气相沉积法、电镀法及其组合所组成的群组。半导体基底可包括晶体方向为<100>或<111>的晶体硅。
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
附图中符号的简单说明如下:
100:半导体元件
110:半导体基底
120:感测元件
125:光
130:多层内连线结构
140:层间介电层
150:掩膜层
160:开口
170:含铝层
180:掺杂铝的深隔离壁
200:半导体元件
W:宽度
D:深度。
Claims (2)
1.一种影像感测器,其特征在于,该影像感测器包括:
一感测元件,形成于一半导体基底中;
一层间介电层,形成于该半导体基底中;
一导电元件,位于该层间介电层中;以及
一掺杂铝的接面,形成于该层间介电层中,且在水平方向位于该感测元件的周围。
2.根据权利要求1所述的影像感测器,其特征在于,该掺杂铝的接面的铝掺杂浓度介于1013atoms/cm3至1020atoms/cm3。
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US11/456,291 US7791170B2 (en) | 2006-07-10 | 2006-07-10 | Method of making a deep junction for electrical crosstalk reduction of an image sensor |
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TW200805640A (en) | 2008-01-16 |
US20100289102A1 (en) | 2010-11-18 |
TWI337405B (en) | 2011-02-11 |
CN101699619B (zh) | 2011-11-16 |
CN101106144A (zh) | 2008-01-16 |
US20080014673A1 (en) | 2008-01-17 |
US7791170B2 (en) | 2010-09-07 |
KR20080005841A (ko) | 2008-01-15 |
KR100840990B1 (ko) | 2008-06-24 |
US7994032B2 (en) | 2011-08-09 |
CN101699619A (zh) | 2010-04-28 |
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