CN100505257C - 集成电路和该电路的操作参数的评价方法 - Google Patents

集成电路和该电路的操作参数的评价方法 Download PDF

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CN100505257C
CN100505257C CNB2005100820355A CN200510082035A CN100505257C CN 100505257 C CN100505257 C CN 100505257C CN B2005100820355 A CNB2005100820355 A CN B2005100820355A CN 200510082035 A CN200510082035 A CN 200510082035A CN 100505257 C CN100505257 C CN 100505257C
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effect transistor
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carbon nanotube
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马克·C.·哈克
马克·E.·马斯特斯
利亚·M.·P.·帕斯特尔
戴维·P.·瓦尔莱特
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Abstract

一种集成电路的形成方法和结构,它包括第一晶体管和靠近第一晶体管的嵌入式碳纳米管场效应晶体管(CNT FET),其中CNT FET的形成尺寸小于第一晶体管。该CNT FET适于检测来自第一晶体管的信号,其中该信号包括温度、电压、电流、电场和磁场信号的任一种。而且,该CNT FET适于检测集成电路中的应力和应变,其中该应力和应变包括机械应力和应变与热应力和应变中的任一种。另外,该CNT FET适于检测集成电路中的有缺陷电路。

Description

集成电路和该电路的操作参数的评价方法
技术领域
本发明的实施例一般通常涉及集成电路技术,尤其涉及评价集成电路芯片操作参数的器件和技术。
背景技术
在集成电路工业,监控用于控制、检测和/或诊断目的监控集成电路的操作是必需的。传统地,或者使用电子读出器内部(如诊断电路、锁存器、扫描链和相关的结构)或者使用物理传感器(如电荷耦合器件(CCD)探测器、热成像仪和磁场传感器)远程采集信号。不幸地是,电子读出器电路通常占据宝贵的芯片面积,引起性能下降或芯片上关键电路的负担,不能明确地查明问题的所在位置。
而且,使用物理传感器从芯片前侧远程监测通常受到金属线路和表面互连或输入/输出(I/O)器件的阻碍。从芯片后侧监测,信号全被硅衬底严重衰减并同样与前侧监测一样被金属线路阻碍。而且,对于空间分辨率,远程传感器通常也缺乏,其中显示的最好分辨率大约在一微米的量级,该量级已经较最小的集成电路特征尺寸大了十倍。
因此,需要一种在工作过程中用于监控集成电路操作的新颖的结构和方法,其进一步提供提高的分辨率质量,在圆片量级或在封装部件上是可操作的,不占据大量的芯片面积,不负面影响电路和/或器件性能。
发明内容
考虑到上述原因,本发明的一个实施例提供一种包括被监控器件和靠近被监控器件的碳纳米管场效应晶体管(CNT FET)的集成电路。CNT FET适于检测来自第一晶体管的信号,该信号包括温度、电压、电流、电场或磁场信号中的任一种信号。而且,CNT FET适用于测量集成电路中的应力和应变,该应力和应变包括机械应力和应变以及热应力和应变中的任一种。另外,CNT FET适于探测集成电路中的有缺陷的电路。根据本发明的一个实施例,被监控器件包括配制在金属氧化物半导体结构中的晶体管。而且,根据本发明的一个实施例,被监控器件包括一个栅极、源极区、漏极区、和分隔栅极和各个源极区与漏极区的栅极绝缘层。而且,CNT FET包括一个CNT FET栅极、CNTFET源极区、CNT FET漏极区和分隔CNT FET源极区和CNT FET漏极区的碳纳米管。根据一个替代的实施例,被监控器件的栅极和CNT FET栅极具有共同的结构。根据另一个实施例,被监控器件的源极区和CNT FET源极区具有共同的结构。还有,被监控器件包括场效应晶体管、二极管、导线、通孔、电阻器、电感器和电容器中的任一个。
本发明的另一方面提供了一种包括主晶体管和与主晶体管分隔的嵌入式CNT FET的集成电路,其中CNT FET适于检测来自主晶体管的信号,该信号包括任一种温度、电压、电流、电场或磁场信号。另外,CNT FET适于检测集成电路中的应力和应变,该应力和应变包括机械应力和应变以及热应力和应变中的任一种。而且,CNT FET适于检测集成电路中的有缺陷电路。根据本发明的一个实施例,主晶体管包括一个金属氧化物半导体结构。在本发明的一个实施例中,主晶体管包括一个栅极、源极区、漏极区、和分隔栅极与各源极区和漏极区的栅极绝缘层。而且,CNT FET包括一个CNT FET栅极、CNTFET源极区、CNT FET漏极区和分隔CNT FET源极区和CNT FET漏极区的碳纳米管。根据一个替代的实施例,主晶体管的栅极和CNTFET栅极具有共同的结构。根据另一个实施例,主晶体管的源极区和CNT FET源极区具有共同的结构。还有,主晶体管包括场效应晶体管、二极管、导线、通孔、电阻器、电感器或电容器中的任一个。
本发明的又一个方面提供了一种评价集成电路的操作参数的方法,该方法包括在集成电路中形成主晶体管、将CNT FET嵌入集成电路中、操作主晶体管和使用CNT FET检测主晶体管的信号,其中该信号包括任一种温度、电压、电流、电场或磁场信号。该方法进一步包括使用CNT FET测量集成电路中的应力和应变,该应力和应变包括机械应力和应变以及热应力和应变任一种。另外,该方法包括使用CNT FET检测集成电路中的有缺陷电路。而且,形成主晶体管的步骤包括以场效应晶体管、二极管、导线、通孔、电阻器、电感器或电容器配置中的任一个配置主晶体管。
根据本发明的一个实施例,CNT FET具有增强的分辨率性质,具有在圆片级或封装部件量级可操作的能力,足够小的构造以致于它不会占据大量的芯片面积,和它的构造不会负面影响电路和/或器件性能。本发明的实施例可以用于微处理器、特殊用途的集成电路、SRAM配制、存储器单元的阵列、宏(macro)、芯和用于检测电路元件的特定缺陷或特定特征的具有已知物理设计的数字或模拟电路元件。例如,本发明的实施例可以用于功率用途分析、热特性、IDD、临界通路分析和其它的影响器件性能的芯片内的检测和诊断参数。
结合下面的描述和附图将会更好地理解本发明的实施例的这些和其它的方面。然而,应该理解,下面的描述在指示本发明的优选实施例和它们的诸多特定细节的同时,仅起到解释的作用而不是限制作用。可以在本发明实施例的范围内进行各种变更和修改而没有脱离其精神,和本发明的实施例包括各种这样的改变。
附图说明
从下面的详述并参照附图将更好地理解本发明的实施例,附图中:
图1是根据本发明第一实施例的具有集成的碳纳米管传感器器件的集成电路一部分的横截面图;
图2是图1所示器件的电路图;
图3是与本发明的实施例结合使用的碳纳米管晶体管器件的电路图;
图4是根据本发明的第二实施例的集成碳纳米管传感器器件的横截面图;
图5是图4所示器件的电路图;
图6是根据本发明的第三实施例的集成碳纳米管传感器器件的横截面图;
图7是图6所示器件的电路图;和
图8是本发明的一个实施例的优选方法的流程图。
具体实施方式
参照附图所显示和下面所描述的非限定的实施例详细地解释本发明的实施例和其各种特性和优越的细节。应当说明,附图所示的特征不一定按比例绘制。为了避免本发明的实施例晦涩模糊省略了已知组件和工艺技术的描述。这里所用的示例仅仅想要帮助对本发明实施方法的理解,即本发明实施例可以被实现和进一步使熟悉本发明的人员能实现该实施例的方法。因此,这些示例不应当被解释为限制本发明实施例的保护范围。
如上所述,仍然需要一种在工作过程中监控集成电路的工作参数的新结构和方法。本发明的实施例通过提供作为诊断传感器能被嵌入到互补金属氧化物半导体(CMOS)集成电路的碳纳米管场效应晶体管(CNT FET)实现了这种需要。现在参照附图,尤其参照图1到图8,介绍本发明的优选实施例。图1到图7和对它们的描述涉及单一的CMOS或CNT器件。然而,为了便于理解图1到图7的每幅图仅示出了一个晶体管。而且,熟悉本发明的人员容易理解图1到图7所示的器件如何扩展到更完整的集成电路结构中。
图1示出了本发明的第一实施例,其中CNT FET作为传感器被集成到CMOS器件中。集成电路5a部分包括其中植入源极24扩散区和漏极22扩散区的硅圆片10。然后在位于源极24区和漏极22区之间部分的硅圆片10上面生长栅极绝缘层25,如氮氧化物。然后,在栅极绝缘层25上面构造栅极30。然后接触和通孔/金属互连结构45被连接到栅极30。另外,接触和通孔/金属互连结构46被连接到漏极22区。在栅极30上面和靠近栅极绝缘层25以及凸起的源极24区和漏极22区的侧面形成第一层间(interlevel)电介质层35。而且,围绕栅极30形成垫片15。
接下来,采用任何传统的技术,如美国专利的公开文本US2003/0218224A1和US2001/0023986A1描述的技术,形成CNT FET传感器器件,这两篇专利所公开的全部内容在这里作为参考文献引用,其中CNT FET传感器器件包括纳米管55置于其间的源极区54和漏极区52和靠近CNT FET的源极54/漏极52/纳米管55部分的栅极50。这样,对应的垂直CNT FET栅极50布置在靠近生长的CNT沟道处。栅极50可以由现存的金属充填物形式(metal fill shapes)构成。对CNT FET施以固定的偏压,这样其沟道电流的改变仅仅是由本地温度、电压、电流、电场和磁场梯度引起。
第二层间电介质层40形成在第一层间电介质层35上面,并围绕CNT FET源极54、漏极52、栅极50和纳米管55。尽管附图显示了CNT FET的通常的垂直源极54/漏极52/栅极50/纳米管55部分,熟悉本领域的人员容易理解其包括了任何的构造,包括水平构造。
图2进一步显示了集成电路5a,其中CMOS FET器件(被监控器件)75包括栅极30、源极24和漏极22。同样,CNT FET器件70包括栅极50、源极54和漏极52和位于源极54和漏极52之间的纳米管55。如图1和图2所示,CNT FET器件70作为寄生器件被构造到CMOS器件75,它们之间没有电路连接。图3更详细地显示了图2的CNT FET器件70。
图4和图5显示了本发明的第二实施例,它的实现类似于第一实施例,这样在图1-2和图4-5中同样的标号对应同样的构件。第一实施例和第二实施例的不同在于第二实施例的集成电路5b包括用于CMOS器件75和CNT FET器件70的共用的栅极60。
图6和图7显示了本发明的第三实施例,它的实现类似于第一和第二实施例,这样在图1-2,图4-5和图6-7中同样的标号对应同样的构件。第三实施例的不同在于第三实施例的集成电路5c包括用于CMOS器件75和CNT FET器件70的共用的栅极60、源极65。这样,这样的CNT FET器件70可以被放置在已存的CMOS信号通路或栅极叠层的最近处,共用相同的栅极电场源,从而用作“追随器件”(follower device),其中驱动预先存在的CMOS器件75的信号能被跟随的CNT FET器件70监控。而且,已存的CMOS信号和栅极电压被CNT FET器件70监控,其中CNT FET器件与CMOS器件的源极65分享源极65和与CMOS器件栅极60分享栅极60。于是,CMOS器件栅极60的电压同时影响CMOS器件75和CNT FET器件70的电场,这样CNT FET器件70的电场与出现在CNT FET器件70的漏极52上的信号成正比关系。
根据本发明的实施例,CNT FET器件70用作CMOS器件75的温度、电压、电流、电场或磁场传感器,其中CMOS器件75中本地的各个梯度被CNT FET器件70检测。同样,CNT FET器件70用作CMOS器件75的应力和应变传感器,其中存在CMOS器件75中的应力和应变被CNT FET器件70检测。进一步,尽管显示了两个层间电介质层35和40,熟悉本领域的人员容易理解可以使用更少或更多数目的层间电介质和相应的金属配线层,带有形成在任一个层间电介质和相应的金属配线层中的CNT FET器件。
通过在集成电路5a、5b和5c中嵌入CNT FET器件70,集成电路5a、5b和5c上的临界尺寸比CNT FET器件70的尺寸大许多倍,从而允许以最小芯片面积需求并且没有电路退化或负载地本地测量关键的工作参数,如温度、电压、电流、电场和磁场信号。由于它们的相对小的尺寸、高灵敏度和与硅CMOS集成电路膜和工艺的材料相容性,CNT FET器件70优选地用作传感器。如上所述,可以使用已知的方法将CNT FET器件70嵌入CMOS工艺中以检测在集成电路工作期间电场、温度、磁场和相关重要性能的本地变化,这种检测有利于提供关于正常运行与有缺陷的电路和集成电路5a、5b、5c区域的信息。而且,CNT FET器件70采用现存已知的方法和电路被导线连通并作为连接芯片内和/或芯片外电路的界面。
根据本发明的该实施例,CNT FET器件70是场调制器件,其中碳纳米管55的导电性能受到存在的电场的控制并且进一步依赖于温度、磁场、应力和应变。所以,CNT FET器件70被放置在靠近被监控器件75处,这样穿过CNT FET器件70的信号会受到邻近的被监控器件75施加的任何显著的电场、磁场、温度/应力/应变的变化的影响。进一步,在替代实施例中,CNT FET器件70距离被监控器件75足够远以致于CNT FET器件70不会影响被监控器件75的工作。CNTFET器件70相对于被监控器件75的确切位置将根据不同的设计变化,也会依赖邻近的被监控器件75需要被监控的距离变化,这样CNTFET器件70距离被监控器件75越近,被监控器件施加的场、应力等越可能影响穿过CNT FET器件70的信号。电场、温度、磁场、应力和应变不仅受到最近的CMOS器件75的正常工作的影响,而且也受到附近电路中的各种缺陷影响。因此将CNT FET器件70连接到适合的测量和放大电路会提供指示这些条件存在的信号。
图8(连同图1-7所示的实施例和组件)显示了评价集成电路5a、5b、5c的工作参数的方法,其中该方法包括在集成电路5a、5b、5c中形成主晶体管(被监控器件)75(102);在集成电路5a、5b、5c中嵌入CNT FET器件70(104);操作主晶体管75(106);和使用CNT FET器件70检测主晶体管75的信号(107),其中信号包括温度、电压、电流、电场和磁场信号中的任一个。该方法进一步包括使用CNT FET器件70测量集成电路5a、5b、5c中的应力和应变(109),其中应力和应变包括机械应力和应变和热应力和应变中的任一种。另外,该方法包括使用CNT FET器件70检测集成电路5a、5b、5c中的有缺陷电路(111)。而且,形成主晶体管75(102)的步骤包括在任一个场效应晶体管、二极管、导线、通孔、电阻器、电感器和电容器结构中构造主晶体管75。
CNT FET器件70可以被用作功率管理系统部件的传感器。特别地,CNT FET器件70可以被用来判断集成电路5a、5b、5c的区何时需要与该区的额外的功率通路/连接。而且,CNT FET器件70可以被用来判断集成电路5a、5b、5c的区是否需要减少通到该区的功率通路/连接。还有,CNT FET器件70可以被用来测量在集成电路5a、5b、5c中的功率分布的电流/电压和决定何时需要刷新备用/休眠电路。
在应力/应变可能允许器件性能的情况下,连同导致会影响器件功能性的错位,CNT FET器件70结合主FET75提供检测集成电路5a、5b、5c的面积,该面积要经受会导致器件退化和/或故障的升高的应力/应变水平。
通常,本发明提供一种包括第一(或主)晶体管75和一靠近(或替代地分开的)第一(或主)晶体管75的嵌入式碳纳米管场效应晶体管70的集成电路5a、5b、5c,其中CNT FET器件70的尺寸小于第一(或主)晶体管75。CNT FET器件70适于检测来自第一(或主)晶体管75的信号,其中该信号包括任一温度、电压、电流、电场和磁场信号。而且,CNT FET器件70适于测量集成电路5a、5b、5c的应力和应变,其中该应力和应变包括机械应力和应变以及热应力和应变中的任一种。
另外,CNT FET器件70适于检测集成电路5a、5b、5c中的有缺陷电路。根据一个实施例,第一(或主)晶体管75包括一金属氧化物半导体结构。而且,该第一(或主)晶体管75包括栅极30、源极24区、漏极22区和使栅极30与各个源极24区和漏极22区分开的栅极氧化物层25。而且,CNT FET器件70包括CNT FET栅极50、CNTFET源极区54、CNT FET漏极区52和分开CNT FET源极区54和CNT FET漏极区52的碳纳米管55。根据一个实施例,第一(或主)晶体管30的栅极和CNT FET栅极50包括共同的(相同的)结构60。根据又一个实施例,第一(或主)晶体管24的源极区和CNT FET源极区54包括一共同的(相同的)结构65。
本发明的实施例可以用于微处理器、特殊用途的集成电路、SRAM结构、存储器单元的排列、宏、磁芯和具有已知的物理设计用于检测电路元件的特定缺陷或特定特征的数字或模拟电路元件。例如,本发明的实施例可以用于功率应用分析、热特征、IDD、临界通路分析、连同其它的芯片内检测和影响器件性能的诊断参数。
根据本发明的实施例,CNT FET器件70具有提高的分辨率性能,这是因为CNT FET器件70的尺寸远远小于嵌入其中的CMOS器件75的尺寸,这就允许问题被定位在CNT FET器件70的特定位置并具有CNT FET器件70尺寸量级的空间分辨率。另外,由于CNT FET器件70被嵌入集成电路5a、5b、5c中和使用原始的CMOS集成电路5a、5b、5c固有的电路,CNT FET器件70具有在圆片量级或封装部件量级的可操作性。而且,CNT FET器件70被构造的足够小,这样由于碳纳米管技术可得到的足够小的FET直径(与CMOS器件75的晶体管和互连导体相比),它不会占据相当大的芯片面积。而且,CNTFET器件70被这样构造,它不会负面影响电路和/或器件性能,这是由于CNT FET器件70仅仅通过温度、电场、磁场、应力或应变被动地连接到它监控的器件和电路。
特定实施例的以上描述充分地揭示了本发明的一般规则,通过应用现有的知识,其他人容易更改和/或适应性修改诸如特定应用的各种用途而没有脱离共用的概念,因此,这种适应性修改和更改应当和意欲包括在揭示的实施例的等同范围内。例如,尽管附图和文字描述显示了场效应晶体管中的第一(或主)晶体管,本发明的实施例同样适用于其它的晶体管和电路结构,包括并不限于二极管、导线、通孔、电阻器、电感器和电容器结构。可以理解,这里所用的措词或技术是为了描述而不是限制的目的。因此,尽管已经根据优选的实施例描述了本发明的实施例,熟悉本领域的人员会认识到本发明的实施例可以经修改而落在附带的权利要求书的精神和保护范围内。

Claims (19)

1、一种集成电路,包括:
被监控的器件,和
靠近所述被监控器件的碳纳米管场效应晶体管,
其中,所述被监控器件包括:
栅极;
源极区;
漏极区;和
使所述栅极与所述源极区和漏极区中的每一个都分开的栅极绝缘层,
所述碳纳米管场效应晶体管包括:
碳纳米管场效应晶体管栅极;
碳纳米管场效应晶体管源极区;
碳纳米管场效应晶体管漏极区;和
分开所述碳纳米管场效应晶体管源极区和所述碳纳米管场效应晶体管漏极区的碳纳米管,
所述被监控器件的所述栅极和所述碳纳米管场效应晶体管栅极具有共用的结构。
2、如权利要求1所述的集成电路,其特征在于,所述碳纳米管场效应晶体管适于检测来自所述被监控器件的信号,其中所述信号包括温度、电压、电流、电场和磁场信号中的任一个。
3、如权利要求1所述的集成电路,其特征在于,所述碳纳米管场效应晶体管适于测量所述集成电路中的应力和应变,其中所述应力和应变包括机械应力和应变以及热应力和应变中的任一种。
4、如权利要求1所述的集成电路,其特征在于,所述碳纳米管场效应晶体管适于检测所述集成电路中的有缺陷电路。
5、如权利要求1所述的集成电路,其特征在于,所述被监控器件包括一构造在金属氧化物半导体结构中的晶体管。
6、如权利要求1所述的集成电路,其特征在于,所述被监控器件的所述源极区和所述碳纳米管场效应晶体管源极区具有共用的结构。
7、如权利要求1所述的集成电路,其特征在于,所述被监控器件包括场效应晶体管。
8、一种集成电路,包括:
主晶体管;和
与所述主晶体管分开的嵌入式碳纳米管场效应晶体管。
其中,所述碳纳米管场效应晶体管适于检测来自所述主晶体管的信号,
所述主晶体管包括:
栅极;
源极区;
漏极区;和
使所述栅极与所述源极区和漏极区中的每一个都分开的栅极绝缘层,
所述碳纳米管场效应晶体管包括:
碳纳米管场效应晶体管栅极;
碳纳米管场效应晶体管源极区;
碳纳米管场效应晶体管漏极区;和
分开所述碳纳米管场效应晶体管源极区和碳纳米管场效应晶体管漏极区的碳纳米管,
所述主晶体管的所述栅极与所述碳纳米管场效应晶体管栅极具有共用的结构。
9、如权利要求8所述的集成电路,其特征在于,所述信号包括温度、电压、电流、电场和磁场信号中的任一种。
10、如权利要求8所述的集成电路,其特征在于,所述碳纳米管场效应晶体管适于检测所述集成电路中的应力和应变,其中所述应力和应变包括机械应力和应变以及热应力和应变中的任一种。
11、如权利要求8所述的集成电路,其特征在于,所述碳纳米管场效应晶体管适于检测所述集成电路中的有缺陷电路。
12、如权利要求8所述的集成电路,其特征在于,所述主晶体管包括金属氧化物半导体结构。
13、如权利要求8所述的集成电路,其特征在于,所述主晶体管的所述源极区和所述碳纳米管场效应晶体管源极区具有共用的结构。
14、如权利要求8所述的集成电路,其特征在于,所述主晶体管包括场效应晶体管。
15、一种评估集成电路的工作参数的方法,所述的方法包括:
在所述集成电路中形成主晶体管;
在所述集成电路中嵌入碳纳米管场效应晶体管,其中所述主晶体管的栅极与所述碳纳米管场效应晶体管的栅极具有共用的结构;
使所述主晶体管工作;和
使用所述碳纳米管场效应晶体管检测来自所述主晶体管的信号。
16、如权利要求15所述的方法,其特征在于,在所述检测来自所述主晶体管的信号的步骤中,所述信号包括温度、电压、电流、电场和磁场信号中的任一种。
17、如权利要求15所述的方法,进一步包括使用所述碳纳米管场效应晶体管检测所述集成电路中的应力和应变,其中所述应力和应变包括机械应力和应变以及热应力和应变的任一种。
18、如权利要求15所述的方法,进一步包括使用所述碳纳米管场效应晶体管检测所述集成电路中的有缺陷电路。
19、如权利要求15所述的方法,其特征在于,所述形成主晶体管的步骤包括将所述主晶体管构造为场效应晶体管。
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US7247877B2 (en) 2007-07-24
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