CN100495687C - 双应力soi衬底 - Google Patents
双应力soi衬底 Download PDFInfo
- Publication number
- CN100495687C CN100495687C CN200580042739.8A CN200580042739A CN100495687C CN 100495687 C CN100495687 C CN 100495687C CN 200580042739 A CN200580042739 A CN 200580042739A CN 100495687 C CN100495687 C CN 100495687C
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- substrate
- layer
- compressive
- tensile
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/938—Lattice strain control or utilization
Landscapes
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Optical Integrated Circuits (AREA)
- Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/905,062 | 2004-12-14 | ||
| US10/905,062 US7262087B2 (en) | 2004-12-14 | 2004-12-14 | Dual stressed SOI substrates |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101076889A CN101076889A (zh) | 2007-11-21 |
| CN100495687C true CN100495687C (zh) | 2009-06-03 |
Family
ID=36582810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200580042739.8A Expired - Fee Related CN100495687C (zh) | 2004-12-14 | 2005-12-13 | 双应力soi衬底 |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US7262087B2 (enExample) |
| EP (1) | EP1825509B1 (enExample) |
| JP (1) | JP5039902B2 (enExample) |
| CN (1) | CN100495687C (enExample) |
| AT (1) | ATE487234T1 (enExample) |
| DE (1) | DE602005024611D1 (enExample) |
| TW (1) | TWI366264B (enExample) |
| WO (1) | WO2006065759A2 (enExample) |
Families Citing this family (40)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4157496B2 (ja) * | 2004-06-08 | 2008-10-01 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US7202513B1 (en) * | 2005-09-29 | 2007-04-10 | International Business Machines Corporation | Stress engineering using dual pad nitride with selective SOI device architecture |
| US8319285B2 (en) * | 2005-12-22 | 2012-11-27 | Infineon Technologies Ag | Silicon-on-insulator chip having multiple crystal orientations |
| JP2007335573A (ja) * | 2006-06-14 | 2007-12-27 | Hitachi Ltd | 半導体装置およびその製造方法 |
| US7803690B2 (en) * | 2006-06-23 | 2010-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxy silicon on insulator (ESOI) |
| JP5532527B2 (ja) * | 2006-08-03 | 2014-06-25 | 株式会社デンソー | Soi基板およびその製造方法 |
| US7829407B2 (en) * | 2006-11-20 | 2010-11-09 | International Business Machines Corporation | Method of fabricating a stressed MOSFET by bending SOI region |
| US7888197B2 (en) * | 2007-01-11 | 2011-02-15 | International Business Machines Corporation | Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer |
| US20080185655A1 (en) * | 2007-02-02 | 2008-08-07 | United Microelectronics Corp. | Smiconductor device, method for fabricating thereof and method for increasing film stress |
| US20080203485A1 (en) * | 2007-02-28 | 2008-08-28 | International Business Machines Corporation | Strained metal gate structure for cmos devices with improved channel mobility and methods of forming the same |
| US20080237733A1 (en) * | 2007-03-27 | 2008-10-02 | International Business Machines Corporation | Structure and method to enhance channel stress by using optimized sti stress and nitride capping layer stress |
| US7615435B2 (en) * | 2007-07-31 | 2009-11-10 | International Business Machines Corporation | Semiconductor device and method of manufacture |
| US20090095991A1 (en) * | 2007-10-11 | 2009-04-16 | International Business Machines Corporation | Method of forming strained mosfet devices using phase transformable materials |
| US20090140351A1 (en) * | 2007-11-30 | 2009-06-04 | Hong-Nien Lin | MOS Devices Having Elevated Source/Drain Regions |
| US7883956B2 (en) * | 2008-02-15 | 2011-02-08 | International Business Machines Corporation | Method of forming coplanar active and isolation regions and structures thereof |
| US8232186B2 (en) * | 2008-05-29 | 2012-07-31 | International Business Machines Corporation | Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure |
| WO2009150558A1 (en) * | 2008-06-13 | 2009-12-17 | Nxp B.V. | Intrusion protection using stress changes |
| FR2934085B1 (fr) * | 2008-07-21 | 2010-09-03 | Commissariat Energie Atomique | Procede pour containdre simultanement en tension et en compression les canaux de transistors nmos et pmos respectivement |
| US8138523B2 (en) * | 2009-10-08 | 2012-03-20 | International Business Machines Corporation | Semiconductor device having silicon on stressed liner (SOL) |
| JP5946771B2 (ja) * | 2009-12-16 | 2016-07-06 | ナショナル セミコンダクター コーポレーションNational Semiconductor Corporation | 半導体基板上のラージエリアガリウム窒化物又は他の窒化物ベース構造のための応力補償 |
| WO2011096265A1 (ja) * | 2010-02-04 | 2011-08-11 | シャープ株式会社 | 転写方法および半導体装置の製造方法並びに半導体装置 |
| US8216905B2 (en) * | 2010-04-27 | 2012-07-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress engineering to reduce dark current of CMOS image sensors |
| US8318563B2 (en) | 2010-05-19 | 2012-11-27 | National Semiconductor Corporation | Growth of group III nitride-based structures and integration with conventional CMOS processing tools |
| US8377759B2 (en) * | 2010-08-17 | 2013-02-19 | International Business Machines Corporation | Controlled fin-merging for fin type FET devices |
| US8592292B2 (en) | 2010-09-02 | 2013-11-26 | National Semiconductor Corporation | Growth of multi-layer group III-nitride buffers on large-area silicon substrates and other substrates |
| US9064974B2 (en) * | 2011-05-16 | 2015-06-23 | International Business Machines Corporation | Barrier trench structure and methods of manufacture |
| US8921209B2 (en) | 2012-09-12 | 2014-12-30 | International Business Machines Corporation | Defect free strained silicon on insulator (SSOI) substrates |
| CN103296013B (zh) * | 2013-05-28 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | 射频器件的形成方法 |
| US9018057B1 (en) | 2013-10-08 | 2015-04-28 | Stmicroelectronics, Inc. | Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer |
| US9190467B2 (en) | 2014-01-08 | 2015-11-17 | Macronix International Co., Ltd. | Semiconductor structure and manufacturing method of the same |
| US20150372096A1 (en) * | 2014-06-20 | 2015-12-24 | Ishiang Shih | High Electron Mobility Transistors and Integrated Circuits with Improved Feature Uniformity and Reduced defects for Microwave and Millimetre Wave Applications |
| US20150371905A1 (en) * | 2014-06-20 | 2015-12-24 | Rf Micro Devices, Inc. | Soi with gold-doped handle wafer |
| US9716581B2 (en) * | 2014-07-31 | 2017-07-25 | Akoustis, Inc. | Mobile communication device configured with a single crystal piezo resonator structure |
| US9515181B2 (en) | 2014-08-06 | 2016-12-06 | Qualcomm Incorporated | Semiconductor device with self-aligned back side features |
| US9570360B2 (en) | 2014-08-27 | 2017-02-14 | International Business Machines Corporation | Dual channel material for finFET for high performance CMOS |
| US9543323B2 (en) | 2015-01-13 | 2017-01-10 | International Business Machines Corporation | Strain release in PFET regions |
| JP2018101740A (ja) * | 2016-12-21 | 2018-06-28 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置、半導体装置の製造方法、及び、電子機器 |
| TWI622169B (zh) * | 2017-02-17 | 2018-04-21 | Powerchip Technology Corporation | 半導體元件的製造方法 |
| CN110660773A (zh) * | 2018-06-28 | 2020-01-07 | 晟碟信息科技(上海)有限公司 | 包含应力消除层的半导体产品衬底 |
| US12431469B2 (en) | 2022-02-11 | 2025-09-30 | International Business Machines Corporation | Vertically stacked FET with strained channel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507071A (zh) * | 2002-12-12 | 2004-06-23 | �Ҵ���˾ | 具有受应力通道的场效应晶体管及其制造方法 |
| US20040132267A1 (en) * | 2003-01-02 | 2004-07-08 | International Business Machines Corporation | Patterned strained silicon for high performance circuits |
| US20040232513A1 (en) * | 2003-05-23 | 2004-11-25 | Taiwan Semiconductor Manufacturing Co. | Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials |
Family Cites Families (81)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3602841A (en) * | 1970-06-18 | 1971-08-31 | Ibm | High frequency bulk semiconductor amplifiers and oscillators |
| GB1601059A (en) * | 1978-05-31 | 1981-10-21 | Secr Defence | Fet devices and their fabrication |
| US4853076A (en) * | 1983-12-29 | 1989-08-01 | Massachusetts Institute Of Technology | Semiconductor thin films |
| US4655415A (en) * | 1985-01-24 | 1987-04-07 | The Garrett Corporation | Helicopter flotation |
| US4665415A (en) | 1985-04-24 | 1987-05-12 | International Business Machines Corporation | Semiconductor device with hole conduction via strained lattice |
| EP0219641B1 (de) * | 1985-09-13 | 1991-01-09 | Siemens Aktiengesellschaft | Integrierte Bipolar- und komplementäre MOS-Transistoren auf einem gemeinsamen Substrat enthaltende Schaltung und Verfahren zu ihrer Herstellung |
| US4958213A (en) * | 1987-12-07 | 1990-09-18 | Texas Instruments Incorporated | Method for forming a transistor base region under thick oxide |
| US5354695A (en) * | 1992-04-08 | 1994-10-11 | Leedy Glenn J | Membrane dielectric isolation IC fabrication |
| US5459346A (en) * | 1988-06-28 | 1995-10-17 | Ricoh Co., Ltd. | Semiconductor substrate with electrical contact in groove |
| US5006913A (en) * | 1988-11-05 | 1991-04-09 | Mitsubishi Denki Kabushiki Kaisha | Stacked type semiconductor device |
| US5108843A (en) * | 1988-11-30 | 1992-04-28 | Ricoh Company, Ltd. | Thin film semiconductor and process for producing the same |
| US4952524A (en) * | 1989-05-05 | 1990-08-28 | At&T Bell Laboratories | Semiconductor device manufacture including trench formation |
| US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
| US5310446A (en) * | 1990-01-10 | 1994-05-10 | Ricoh Company, Ltd. | Method for producing semiconductor film |
| US5060030A (en) * | 1990-07-18 | 1991-10-22 | Raytheon Company | Pseudomorphic HEMT having strained compensation layer |
| US5218213A (en) * | 1991-02-22 | 1993-06-08 | Harris Corporation | SOI wafer with sige |
| US5081513A (en) * | 1991-02-28 | 1992-01-14 | Xerox Corporation | Electronic device with recovery layer proximate to active layer |
| US5371399A (en) * | 1991-06-14 | 1994-12-06 | International Business Machines Corporation | Compound semiconductor having metallic inclusions and devices fabricated therefrom |
| US5134085A (en) * | 1991-11-21 | 1992-07-28 | Micron Technology, Inc. | Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories |
| US5391510A (en) * | 1992-02-28 | 1995-02-21 | International Business Machines Corporation | Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps |
| US6008126A (en) * | 1992-04-08 | 1999-12-28 | Elm Technology Corporation | Membrane dielectric isolation IC fabrication |
| US5268326A (en) * | 1992-09-28 | 1993-12-07 | Motorola, Inc. | Method of making dielectric and conductive isolated island |
| US5234535A (en) * | 1992-12-10 | 1993-08-10 | International Business Machines Corporation | Method of producing a thin silicon-on-insulator layer |
| US5561302A (en) * | 1994-09-26 | 1996-10-01 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
| US5405791A (en) * | 1994-10-04 | 1995-04-11 | Micron Semiconductor, Inc. | Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers |
| US5444014A (en) * | 1994-12-16 | 1995-08-22 | Electronics And Telecommunications Research Institute | Method for fabricating semiconductor device |
| US5670387A (en) * | 1995-01-03 | 1997-09-23 | Motorola, Inc. | Process for forming semiconductor-on-insulator device |
| US5670798A (en) * | 1995-03-29 | 1997-09-23 | North Carolina State University | Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same |
| US5679965A (en) * | 1995-03-29 | 1997-10-21 | North Carolina State University | Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same |
| US5557122A (en) * | 1995-05-12 | 1996-09-17 | Alliance Semiconductors Corporation | Semiconductor electrode having improved grain structure and oxide growth properties |
| US6403975B1 (en) * | 1996-04-09 | 2002-06-11 | Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev | Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates |
| US5880040A (en) * | 1996-04-15 | 1999-03-09 | Macronix International Co., Ltd. | Gate dielectric based on oxynitride grown in N2 O and annealed in NO |
| US5861651A (en) * | 1997-02-28 | 1999-01-19 | Lucent Technologies Inc. | Field effect devices and capacitors with improved thin film dielectrics and method for making same |
| US5940736A (en) * | 1997-03-11 | 1999-08-17 | Lucent Technologies Inc. | Method for forming a high quality ultrathin gate oxide layer |
| US6309975B1 (en) * | 1997-03-14 | 2001-10-30 | Micron Technology, Inc. | Methods of making implanted structures |
| US6025280A (en) * | 1997-04-28 | 2000-02-15 | Lucent Technologies Inc. | Use of SiD4 for deposition of ultra thin and controllable oxides |
| US5960297A (en) * | 1997-07-02 | 1999-09-28 | Kabushiki Kaisha Toshiba | Shallow trench isolation structure and method of forming the same |
| JP3139426B2 (ja) * | 1997-10-15 | 2001-02-26 | 日本電気株式会社 | 半導体装置 |
| US6066545A (en) * | 1997-12-09 | 2000-05-23 | Texas Instruments Incorporated | Birdsbeak encroachment using combination of wet and dry etch for isolation nitride |
| US6274421B1 (en) * | 1998-01-09 | 2001-08-14 | Sharp Laboratories Of America, Inc. | Method of making metal gate sub-micron MOS transistor |
| KR100275908B1 (ko) * | 1998-03-02 | 2000-12-15 | 윤종용 | 집적 회로에 트렌치 아이솔레이션을 형성하는방법 |
| US6361885B1 (en) * | 1998-04-10 | 2002-03-26 | Organic Display Technology | Organic electroluminescent materials and device made from such materials |
| US6165383A (en) * | 1998-04-10 | 2000-12-26 | Organic Display Technology | Useful precursors for organic electroluminescent materials and devices made from such materials |
| US5989978A (en) * | 1998-07-16 | 1999-11-23 | Chartered Semiconductor Manufacturing, Ltd. | Shallow trench isolation of MOSFETS with reduced corner parasitic currents |
| JP4592837B2 (ja) * | 1998-07-31 | 2010-12-08 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US6319794B1 (en) * | 1998-10-14 | 2001-11-20 | International Business Machines Corporation | Structure and method for producing low leakage isolation devices |
| US6235598B1 (en) * | 1998-11-13 | 2001-05-22 | Intel Corporation | Method of using thick first spacers to improve salicide resistance on polysilicon gates |
| US6117722A (en) * | 1999-02-18 | 2000-09-12 | Taiwan Semiconductor Manufacturing Company | SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof |
| US6255169B1 (en) * | 1999-02-22 | 2001-07-03 | Advanced Micro Devices, Inc. | Process for fabricating a high-endurance non-volatile memory device |
| US6284626B1 (en) * | 1999-04-06 | 2001-09-04 | Vantis Corporation | Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench |
| US6281532B1 (en) * | 1999-06-28 | 2001-08-28 | Intel Corporation | Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering |
| US6228694B1 (en) * | 1999-06-28 | 2001-05-08 | Intel Corporation | Method of increasing the mobility of MOS transistors by use of localized stress regions |
| US6362082B1 (en) * | 1999-06-28 | 2002-03-26 | Intel Corporation | Methodology for control of short channel effects in MOS transistors |
| US6656822B2 (en) * | 1999-06-28 | 2003-12-02 | Intel Corporation | Method for reduced capacitance interconnect system using gaseous implants into the ILD |
| KR100332108B1 (ko) * | 1999-06-29 | 2002-04-10 | 박종섭 | 반도체 소자의 트랜지스터 및 그 제조 방법 |
| TW426940B (en) * | 1999-07-30 | 2001-03-21 | United Microelectronics Corp | Manufacturing method of MOS field effect transistor |
| JP3275896B2 (ja) * | 1999-10-06 | 2002-04-22 | 日本電気株式会社 | 半導体装置の製造方法 |
| US6284623B1 (en) * | 1999-10-25 | 2001-09-04 | Peng-Fei Zhang | Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect |
| US6476462B2 (en) * | 1999-12-28 | 2002-11-05 | Texas Instruments Incorporated | MOS-type semiconductor device and method for making same |
| US6221735B1 (en) * | 2000-02-15 | 2001-04-24 | Philips Semiconductors, Inc. | Method for eliminating stress induced dislocations in CMOS devices |
| US6531369B1 (en) * | 2000-03-01 | 2003-03-11 | Applied Micro Circuits Corporation | Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe) |
| JP4963140B2 (ja) * | 2000-03-02 | 2012-06-27 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| US6368931B1 (en) * | 2000-03-27 | 2002-04-09 | Intel Corporation | Thin tensile layers in shallow trench isolation and method of making same |
| US6380021B1 (en) * | 2000-06-20 | 2002-04-30 | Taiwan Semiconductor Manufacturing Company | Ultra-shallow junction formation by novel process sequence for PMOSFET |
| US6493497B1 (en) * | 2000-09-26 | 2002-12-10 | Motorola, Inc. | Electro-optic structure and process for fabricating same |
| US6501121B1 (en) * | 2000-11-15 | 2002-12-31 | Motorola, Inc. | Semiconductor structure |
| KR100784603B1 (ko) * | 2000-11-22 | 2007-12-11 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 장치 및 그 제조 방법 |
| JP2003086708A (ja) * | 2000-12-08 | 2003-03-20 | Hitachi Ltd | 半導体装置及びその製造方法 |
| US6563152B2 (en) * | 2000-12-29 | 2003-05-13 | Intel Corporation | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel |
| US20020086497A1 (en) * | 2000-12-30 | 2002-07-04 | Kwok Siang Ping | Beaker shape trench with nitride pull-back for STI |
| US6265317B1 (en) * | 2001-01-09 | 2001-07-24 | Taiwan Semiconductor Manufacturing Company | Top corner rounding for shallow trench isolation |
| US6403486B1 (en) * | 2001-04-30 | 2002-06-11 | Taiwan Semiconductor Manufacturing Company | Method for forming a shallow trench isolation |
| US6531740B2 (en) * | 2001-07-17 | 2003-03-11 | Motorola, Inc. | Integrated impedance matching and stability network |
| US6498358B1 (en) * | 2001-07-20 | 2002-12-24 | Motorola, Inc. | Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating |
| US6908810B2 (en) * | 2001-08-08 | 2005-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation |
| JP2003060076A (ja) * | 2001-08-21 | 2003-02-28 | Nec Corp | 半導体装置及びその製造方法 |
| US20030057184A1 (en) * | 2001-09-22 | 2003-03-27 | Shiuh-Sheng Yu | Method for pull back SiN to increase rounding effect in a shallow trench isolation process |
| US6656798B2 (en) | 2001-09-28 | 2003-12-02 | Infineon Technologies, Ag | Gate processing method with reduced gate oxide corner and edge thinning |
| US6911379B2 (en) * | 2003-03-05 | 2005-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming strained silicon on insulator substrate |
| US7812340B2 (en) * | 2003-06-13 | 2010-10-12 | International Business Machines Corporation | Strained-silicon-on-insulator single-and double-gate MOSFET and method for forming the same |
| US7125759B2 (en) * | 2005-03-23 | 2006-10-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor-on-insulator (SOI) strained active areas |
-
2004
- 2004-12-14 US US10/905,062 patent/US7262087B2/en not_active Expired - Lifetime
-
2005
- 2005-12-02 TW TW094142702A patent/TWI366264B/zh not_active IP Right Cessation
- 2005-12-13 WO PCT/US2005/044957 patent/WO2006065759A2/en not_active Ceased
- 2005-12-13 JP JP2007545712A patent/JP5039902B2/ja not_active Expired - Fee Related
- 2005-12-13 DE DE602005024611T patent/DE602005024611D1/de not_active Expired - Lifetime
- 2005-12-13 EP EP05853786A patent/EP1825509B1/en not_active Expired - Lifetime
- 2005-12-13 AT AT05853786T patent/ATE487234T1/de not_active IP Right Cessation
- 2005-12-13 CN CN200580042739.8A patent/CN100495687C/zh not_active Expired - Fee Related
-
2007
- 2007-04-27 US US11/741,441 patent/US7312134B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507071A (zh) * | 2002-12-12 | 2004-06-23 | �Ҵ���˾ | 具有受应力通道的场效应晶体管及其制造方法 |
| US20040132267A1 (en) * | 2003-01-02 | 2004-07-08 | International Business Machines Corporation | Patterned strained silicon for high performance circuits |
| US20040232513A1 (en) * | 2003-05-23 | 2004-11-25 | Taiwan Semiconductor Manufacturing Co. | Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials |
Also Published As
| Publication number | Publication date |
|---|---|
| DE602005024611D1 (de) | 2010-12-16 |
| EP1825509A2 (en) | 2007-08-29 |
| TW200636979A (en) | 2006-10-16 |
| JP2008523631A (ja) | 2008-07-03 |
| WO2006065759A3 (en) | 2007-06-14 |
| US20070202639A1 (en) | 2007-08-30 |
| CN101076889A (zh) | 2007-11-21 |
| US7312134B2 (en) | 2007-12-25 |
| ATE487234T1 (de) | 2010-11-15 |
| EP1825509A4 (en) | 2009-04-15 |
| JP5039902B2 (ja) | 2012-10-03 |
| TWI366264B (en) | 2012-06-11 |
| US7262087B2 (en) | 2007-08-28 |
| WO2006065759A2 (en) | 2006-06-22 |
| US20060125008A1 (en) | 2006-06-15 |
| EP1825509B1 (en) | 2010-11-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100495687C (zh) | 双应力soi衬底 | |
| US7605429B2 (en) | Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement | |
| TWI364095B (en) | Finfet having improved carrier mobility and method of its formation | |
| TWI395295B (zh) | 積體電路及其製造方法 | |
| US7528056B2 (en) | Low-cost strained SOI substrate for high-performance CMOS technology | |
| US8587063B2 (en) | Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channels | |
| CN100461430C (zh) | 半导体结构及其形成方法 | |
| JP4521542B2 (ja) | 半導体装置および半導体基板 | |
| US7560328B2 (en) | Strained Si on multiple materials for bulk or SOI substrates | |
| US7767546B1 (en) | Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer | |
| JP3512701B2 (ja) | 半導体装置及びその製造方法 | |
| CN1956199B (zh) | 半导体结构及其制造方法 | |
| CN101388399A (zh) | 混合取向技术互补金属氧化物半导体结构及其制造方法 | |
| JP2005514771A (ja) | ボディ結合型絶縁膜上シリコン半導体デバイス及びその方法 | |
| US20070040235A1 (en) | Dual trench isolation for CMOS with hybrid orientations | |
| US8710549B2 (en) | MOS device for eliminating floating body effects and self-heating effects | |
| US8932921B2 (en) | N/P metal crystal orientation for high-k metal gate Vt modulation | |
| US6352872B1 (en) | SOI device with double gate and method for fabricating the same | |
| US8062952B2 (en) | Strain transformation in biaxially strained SOI substrates for performance enhancement of P-channel and N-channel transistors | |
| US7898003B2 (en) | Hybrid strained orientated substrates and devices | |
| US7385257B2 (en) | Hybrid orientation SOI substrates, and method for forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170106 Address after: Grand Cayman, Cayman Islands Patentee after: INTERNATIONAL BUSINESS MACHINES Corp. Address before: American New York Patentee before: Globalfoundries second U.S. Semiconductor Co.,Ltd. Effective date of registration: 20170106 Address after: American New York Patentee after: Globalfoundries second U.S. Semiconductor Co.,Ltd. Address before: American New York Patentee before: International Business Machines Corp. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090603 Termination date: 20181213 |