CN100495687C - 双应力soi衬底 - Google Patents

双应力soi衬底 Download PDF

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Publication number
CN100495687C
CN100495687C CN200580042739.8A CN200580042739A CN100495687C CN 100495687 C CN100495687 C CN 100495687C CN 200580042739 A CN200580042739 A CN 200580042739A CN 100495687 C CN100495687 C CN 100495687C
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China
Prior art keywords
dielectric layer
substrate
layer
compressive
tensile
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Expired - Fee Related
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CN200580042739.8A
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Chinese (zh)
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CN101076889A (zh
Inventor
D·奇丹巴尔拉奥
O·H·多库马茨
B·B·多里斯
O·格卢斯秦柯夫
朱慧珑
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Globalfoundries Second US Semiconductor Co ltd
International Business Machines Corp
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International Business Machines Corp
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/791Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/938Lattice strain control or utilization

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  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Optical Integrated Circuits (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
CN200580042739.8A 2004-12-14 2005-12-13 双应力soi衬底 Expired - Fee Related CN100495687C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/905,062 2004-12-14
US10/905,062 US7262087B2 (en) 2004-12-14 2004-12-14 Dual stressed SOI substrates

Publications (2)

Publication Number Publication Date
CN101076889A CN101076889A (zh) 2007-11-21
CN100495687C true CN100495687C (zh) 2009-06-03

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CN200580042739.8A Expired - Fee Related CN100495687C (zh) 2004-12-14 2005-12-13 双应力soi衬底

Country Status (8)

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US (2) US7262087B2 (enExample)
EP (1) EP1825509B1 (enExample)
JP (1) JP5039902B2 (enExample)
CN (1) CN100495687C (enExample)
AT (1) ATE487234T1 (enExample)
DE (1) DE602005024611D1 (enExample)
TW (1) TWI366264B (enExample)
WO (1) WO2006065759A2 (enExample)

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US8319285B2 (en) * 2005-12-22 2012-11-27 Infineon Technologies Ag Silicon-on-insulator chip having multiple crystal orientations
JP2007335573A (ja) * 2006-06-14 2007-12-27 Hitachi Ltd 半導体装置およびその製造方法
US7803690B2 (en) * 2006-06-23 2010-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxy silicon on insulator (ESOI)
JP5532527B2 (ja) * 2006-08-03 2014-06-25 株式会社デンソー Soi基板およびその製造方法
US7829407B2 (en) * 2006-11-20 2010-11-09 International Business Machines Corporation Method of fabricating a stressed MOSFET by bending SOI region
US7888197B2 (en) * 2007-01-11 2011-02-15 International Business Machines Corporation Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer
US20080185655A1 (en) * 2007-02-02 2008-08-07 United Microelectronics Corp. Smiconductor device, method for fabricating thereof and method for increasing film stress
US20080203485A1 (en) * 2007-02-28 2008-08-28 International Business Machines Corporation Strained metal gate structure for cmos devices with improved channel mobility and methods of forming the same
US20080237733A1 (en) * 2007-03-27 2008-10-02 International Business Machines Corporation Structure and method to enhance channel stress by using optimized sti stress and nitride capping layer stress
US7615435B2 (en) * 2007-07-31 2009-11-10 International Business Machines Corporation Semiconductor device and method of manufacture
US20090095991A1 (en) * 2007-10-11 2009-04-16 International Business Machines Corporation Method of forming strained mosfet devices using phase transformable materials
US20090140351A1 (en) * 2007-11-30 2009-06-04 Hong-Nien Lin MOS Devices Having Elevated Source/Drain Regions
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US8232186B2 (en) * 2008-05-29 2012-07-31 International Business Machines Corporation Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure
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JP5946771B2 (ja) * 2009-12-16 2016-07-06 ナショナル セミコンダクター コーポレーションNational Semiconductor Corporation 半導体基板上のラージエリアガリウム窒化物又は他の窒化物ベース構造のための応力補償
WO2011096265A1 (ja) * 2010-02-04 2011-08-11 シャープ株式会社 転写方法および半導体装置の製造方法並びに半導体装置
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CN103296013B (zh) * 2013-05-28 2017-08-08 上海华虹宏力半导体制造有限公司 射频器件的形成方法
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US20150372096A1 (en) * 2014-06-20 2015-12-24 Ishiang Shih High Electron Mobility Transistors and Integrated Circuits with Improved Feature Uniformity and Reduced defects for Microwave and Millimetre Wave Applications
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JP2018101740A (ja) * 2016-12-21 2018-06-28 ソニーセミコンダクタソリューションズ株式会社 半導体装置、半導体装置の製造方法、及び、電子機器
TWI622169B (zh) * 2017-02-17 2018-04-21 Powerchip Technology Corporation 半導體元件的製造方法
CN110660773A (zh) * 2018-06-28 2020-01-07 晟碟信息科技(上海)有限公司 包含应力消除层的半导体产品衬底
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Also Published As

Publication number Publication date
DE602005024611D1 (de) 2010-12-16
EP1825509A2 (en) 2007-08-29
TW200636979A (en) 2006-10-16
JP2008523631A (ja) 2008-07-03
WO2006065759A3 (en) 2007-06-14
US20070202639A1 (en) 2007-08-30
CN101076889A (zh) 2007-11-21
US7312134B2 (en) 2007-12-25
ATE487234T1 (de) 2010-11-15
EP1825509A4 (en) 2009-04-15
JP5039902B2 (ja) 2012-10-03
TWI366264B (en) 2012-06-11
US7262087B2 (en) 2007-08-28
WO2006065759A2 (en) 2006-06-22
US20060125008A1 (en) 2006-06-15
EP1825509B1 (en) 2010-11-03

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