DE602005024611D1 - Verfahren zur Herstellung dual verspannter SOI Substrate - Google Patents

Verfahren zur Herstellung dual verspannter SOI Substrate

Info

Publication number
DE602005024611D1
DE602005024611D1 DE602005024611T DE602005024611T DE602005024611D1 DE 602005024611 D1 DE602005024611 D1 DE 602005024611D1 DE 602005024611 T DE602005024611 T DE 602005024611T DE 602005024611 T DE602005024611 T DE 602005024611T DE 602005024611 D1 DE602005024611 D1 DE 602005024611D1
Authority
DE
Germany
Prior art keywords
dielectric layer
atop
substrate
tensile
compressive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005024611T
Other languages
English (en)
Inventor
Dureseti Chidambarrao
Omer H Dokumaci
Bruce B Doris
Oleg Gluschenkov
Huilong Zhu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE602005024611D1 publication Critical patent/DE602005024611D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization
DE602005024611T 2004-12-14 2005-12-13 Verfahren zur Herstellung dual verspannter SOI Substrate Active DE602005024611D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/905,062 US7262087B2 (en) 2004-12-14 2004-12-14 Dual stressed SOI substrates
PCT/US2005/044957 WO2006065759A2 (en) 2004-12-14 2005-12-13 Dual stressed soi substrates

Publications (1)

Publication Number Publication Date
DE602005024611D1 true DE602005024611D1 (de) 2010-12-16

Family

ID=36582810

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005024611T Active DE602005024611D1 (de) 2004-12-14 2005-12-13 Verfahren zur Herstellung dual verspannter SOI Substrate

Country Status (8)

Country Link
US (2) US7262087B2 (de)
EP (1) EP1825509B1 (de)
JP (1) JP5039902B2 (de)
CN (1) CN100495687C (de)
AT (1) ATE487234T1 (de)
DE (1) DE602005024611D1 (de)
TW (1) TWI366264B (de)
WO (1) WO2006065759A2 (de)

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Also Published As

Publication number Publication date
EP1825509B1 (de) 2010-11-03
CN100495687C (zh) 2009-06-03
EP1825509A4 (de) 2009-04-15
JP5039902B2 (ja) 2012-10-03
US20070202639A1 (en) 2007-08-30
TWI366264B (en) 2012-06-11
US7262087B2 (en) 2007-08-28
WO2006065759A2 (en) 2006-06-22
TW200636979A (en) 2006-10-16
JP2008523631A (ja) 2008-07-03
WO2006065759A3 (en) 2007-06-14
EP1825509A2 (de) 2007-08-29
ATE487234T1 (de) 2010-11-15
US20060125008A1 (en) 2006-06-15
CN101076889A (zh) 2007-11-21
US7312134B2 (en) 2007-12-25

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