CN110660773A - 包含应力消除层的半导体产品衬底 - Google Patents

包含应力消除层的半导体产品衬底 Download PDF

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Publication number
CN110660773A
CN110660773A CN201810690328.9A CN201810690328A CN110660773A CN 110660773 A CN110660773 A CN 110660773A CN 201810690328 A CN201810690328 A CN 201810690328A CN 110660773 A CN110660773 A CN 110660773A
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China
Prior art keywords
substrate
stress relief
relief layer
layer
dielectric core
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CN201810690328.9A
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English (en)
Inventor
郭睿
陆松涛
黄盛华
刘婷
邱进添
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shengdai Information Technology (shanghai) Co Ltd
SanDisk Information Technology Shanghai Co Ltd
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Shengdai Information Technology (shanghai) Co Ltd
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Application filed by Shengdai Information Technology (shanghai) Co Ltd filed Critical Shengdai Information Technology (shanghai) Co Ltd
Priority to CN201810690328.9A priority Critical patent/CN110660773A/zh
Priority to US16/277,244 priority patent/US20200006212A1/en
Publication of CN110660773A publication Critical patent/CN110660773A/zh
Pending legal-status Critical Current

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Abstract

公开了一种衬底，其具有应力消除层。应力消除层可以施加到衬底的电介质芯，在其中形成电迹线和接触垫的导电层下方。包含应力消除层的衬底可以整合到半导体产品中，半导体产品可以例如使用衬底的表面上的焊料球安装在主机印刷电路板上。应力消除层帮助耗散衬底内的应力并改善板级可靠性。

Description

包含应力消除层的半导体产品衬底
技术领域
本发明总体上涉及半导体装置，更具体地，涉及包含应力消除层的半导体产品衬底。
背景技术
对于便携式消费电子装置的需求的强劲增长正驱动对于大容量储存装置的需求。非易失性半导体存储器装置变得广泛应用，以满足对数字信息储存和交换的日益增长的需求。它们的便携性、多功能以及坚固设计连同它们的高可靠性和大容量，已经使得这样的存储器装置对于在多样的电子产品中使用是理想的，电子装置包含例如数码相机、数字音乐播放器、视频游戏控制台、计算机SSD、PDA以及蜂窝电话。
虽然已知许多不同封装配置，闪速存储器半导体装置可以总体上制造为系统级封装体(SIP)或多芯片模块(MCM)，其中多个半导体裸芯安装并互连到小足印衬底的上表面。衬底可以总体上包含刚性的、电介质的基部，基部具有在一侧或两侧上蚀刻的导电层。焊料球通常安装在形成在衬底的下表面上的接触垫上，以允许衬底被焊接到诸如印刷电路板的主机装置。一经安装，信号可以在半导体裸芯与主机装置之间经由衬底传输。
在常规板级半导体产品中，常常在衬底垫与PCB(印刷电路板)垫之间的焊料球结合点处产生机械应力。例如，这些应力可能由于例如在板级半导体产品的热循环测试期间的半导体封装体和PCB的不同热膨胀系数产生。这些应力还可能由于例如在半导体产品的掉落测试期间的对焊料球冲击振动而产生。这些应力可能导致焊料球裂开、焊料球从接触垫分离和/或迹线在与接触垫的连接点处的破裂，其全部都可能导致板级可靠性(BLR)失效。
发明内容
概括起来，在一个示例中，本技术涉及一种在半导体产品中使用的衬底，包括：具有第一主平坦表面和第二主平坦表面的电介质芯；施加到电介质芯的第一主平坦表面上的应力消除层，应力消除层的模量小于电介质芯的模量；施加到电介质芯的第二主平坦表面上的第一导电层，第一导电层形成为第一导电图案；以及施加到应力消除层上的第二导电层，第二导电层形成为第二导电图案。
在另一示例中，本技术涉及一种半导体产品，包括：衬底，包括：具有第一主平坦表面的电介质芯，施加到电介质芯的第一主平坦表面上的应力消除层，应力消除层的模量小于电介质芯的模量，以及施加到应力消除层上的第一导电层，第一导电层形成为第一导电图案；以及安装在衬底上并电互连到衬底的一个或多个半导体裸芯。
在其他示例中，本技术涉及一种制造半导体产品的衬底的方法，包括：(a)将电介质膜施加到电介质芯上，电介质膜具有比电介质芯更低的模量；(b)将第一导电层施加到电介质芯上；(c)将第一导电层形成为第一导电图案；(d)将第二导电层施加到应力消除层上；(e)将第二导电层形成为第二导电图案；以及(f)将焊料球固定到衬底，电介质膜耗散焊料球与衬底之间的应力。
在另一示例中，本技术涉及一种在半导体产品中使用的衬底，包括：具有第一平坦主表面和第二主平坦表面的电介质芯；应力消除构件，施加到电介质芯的第一主平坦表面上，用于降低衬底内的机械应力；施加到电介质芯的第二主平坦表面上的第一导电层，第一导电层形成为第一导电图案；以及施加到应力消除构件上的第二导电层，第二导电层形成为第二导电图案。
附图说明
图1是根据本技术的实施例的衬底和使用该衬底的半导体产品的总体制造工艺的流程图。
图2是根据本技术的实施例的在制造工艺中的第一步骤的半导体产品的衬底的侧视图。
图3是图2的衬底的仰视图。
图4是根据本技术的实施例的在制造工艺中的第二步骤的半导体产品的衬底的侧视图。
图5是图4的衬底的俯视图。
图6是根据本技术的实施例的在制造工艺中的第三步骤的半导体产品的衬底的侧视图。
图7是图6的衬底的俯视图。
图8是图6的衬底的仰视图。
图9是根据本技术的实施例的安装在衬底上的若干半导体裸芯的侧视图。
图10是根据本技术的实施例的安装在衬底上并引线键合到衬底的若干半导体裸芯的立体图。
图11是根据本技术的实施例的完成的半导体产品的侧视图。
图12是图11的半导体产品的仰视图。
图13和图14是根据本技术的替代实施例的包含应力消除层的衬底的仰视图。
具体实施方式
现将参考附图描述本技术，其在实施例中涉及一种具有应力消除层的衬底。应力消除层可以施加到衬底的电介质芯，在其中形成电迹线和接触垫的导电层下面。包含应力消除层的衬底可以整合到半导体产品中，半导体产品可以例如使用衬底的表面上的焊料球安装在主机印刷电路板上。应力消除层帮助耗散衬底内的应力并改善板级可靠性。
应理解的是，本技术可以以许多不同形式实施，且不应理解为限制为本文中提出的实施例。反之，提供这些实施例使得本公开将是彻底且完整的，并将向本领域技术人员完全地传达本技术。实际上，本技术意图覆盖这些实施例的替代、修改以及等同，其包含在由所附权利要求所限定的本技术的范围和精神内。另外，在本技术的以下详细描述中，提出了许多具体细节，以便提供本技术的彻底理解。然而，本领域普通技术人员将明白，本技术可以在没有这些具体细节的情况下实践。
如本文中可能使用的术语“顶”和“底”、“上”和“下”和“垂直”和“水平”仅是作为示例和出于说明目的，并且不旨在限制技术的描述，因为涉及的项目可以在位置和取向上交换。另外，如本文中所使用的，术语“实质上”、“近似”和/或“约”是指指定尺寸或参数可以在给定应用的可接受制造公差内变化。在一个实施例中，可接受制造公差是给定尺寸的±2.5％。
现将参考图1的流程图和图2至图12的俯视图、侧视图以及立体图解释本技术的实施例。虽然附图示出了单独的半导体装置150或其一部分，应理解的是，产品150可以在衬底面板上连同多个其他半导体产品批量制造，以实现规模经济效益。衬底面板上的装置150的行和列的数目可以变化。
用于制造半导体产品150的衬底面板开始于多个衬底100(再次地，图2-8中示出了一个这样的衬底)。衬底100可以是多种不同的芯片载体介质，包含印刷电路板(PCB)、引线框架或带式自动接合(TAB)带。在衬底100是PCB的情况下，衬底可以由如图2中所示的芯102形成。芯102可以由各种电介质材料形成，例如，聚酰亚胺层压体、包含FR4和FR5的环氧树脂、双马来酰亚胺三嗪(bismaleimide triazine，BT)等。芯可以具有40微米(μm)至200μm之间的厚度，虽然芯的厚度在替代实施例中可以在该范围之外变化。芯102在替代实施例中可以是陶瓷或有机的。
根据本技术的方面，应力消除层103可以在步骤200中形成在电介质芯102上，分别如图2和图3的边视图和仰视图所示。应力消除层可以是模量低于相对刚性的电介质芯102的模量的多种弹性膜中的任意弹性膜。在实施例中，应力消除层103的模量可以是例如100MPa至1000MPa，并且可能为约300MPa至500MPa。应力消除层103可以由各种电介质材料形成，包含例如聚酰亚胺(PI)、聚苯并恶唑(PBO)、苯并环丁烯(BCB)、各种硅胶化合物以及各种橡胶。应力消除层103在其他实施例中可以由其他材料形成。在实施例中，应力消除层103可以具有在10μm至50μm之间的厚度，例如20μm至25μm。应力消除层103在其他实施例中可以比之更薄或更厚。
应力消除层103的其他性质可以包含0.25至0.5的泊松比(Poisson’s ratio)，例如0.33至0.35。其可以具有范围在20PPM与60PPM之间的热膨胀系数，例如30PPM。应力消除层103可以通过多种工艺中的任意工艺施加到电介质芯102，包含例如薄膜沉积、气相沉积、印刷、旋涂、干膜层压或其他方法。在实施例中，应力消除层103可以施加到电介质芯102的单个主平坦表面。然而，在其他实施例中，应力消除层103可以施加到电介质芯102的两个主平坦表面。
在步骤204中，导电层104和105可以接下来形成在衬底100的暴露的平坦表面上，分别如图4和图5的边视图和俯视图所示。例如，在应力消除层103形成在电介质芯102的一个表面上的情况下，导电层104可以形成在电介质芯102的暴露的主平坦表面上。导电层105可以形成在应力消除层103的暴露的主平坦表面上。
导电层104、105可以由铜或铜合金、镀覆的铜或镀覆的铜合金、合金42(42Fe/58Ni)、铜镀覆的钢或适于在衬底面板上使用的其他金属和材料形成。导电层104、105可以具有约8μm至40μm的厚度，虽然层的厚度在替代实施例中可以在该范围之外变化。
在步骤210中，通孔、引线和/或垫的导电图案形成在衬底100中且穿过衬底100。可以将衬底100钻孔，以限定穿孔通孔(throug-hole via)106，其随后被镀覆和/或填充有导电金属。然后电迹线108和接触垫110的导电图案可以形成在衬底100的顶和/或底主平坦表面上。图5示出了导电图案的示例，其包含衬底100的第一主平坦表面112上形成的迹线108和接触垫110。图8示出了导电图案的示例，其包含衬底100的第二主平坦表面114上形成的迹线108和接触垫110。
附图中在表面112和表面114上所示的通孔106、迹线108以及接触垫110的图案是作为示例，并且衬底100在其他实施例中可以包含更多或更少的通孔、迹线和/或接触垫，并且它们在其他实施例中可以在不同的位置中。衬底100的顶和/或底表面上的导电图案可以通过各种已知工艺形成，包含例如各种光刻法工艺。
再次参考图1，衬底100可以接下来在步骤214中被检查。此步骤可以包含自动化光学检查(AOI)。一经检查，可以在步骤216中将阻焊掩模118施加到衬底的上表面和/或下表面，分别如图6、7和8的边视图、俯视图以及仰视图所示。在施加阻焊掩模之后，可以在步骤218中以已知的电镀或薄膜沉积工艺将接触垫110以及要被焊接在导电图案上的任何其他区域例如用Ni/Au、合金42等镀覆。衬底100可以接下来在步骤220中经受操作测试，以确保衬底100正确工作。在步骤222中，衬底可以被视觉检查，包含例如自动化视觉检查(AVI)和最终视觉检查(FVI)，以检查污染、划痕以及变色(discoloration)。在其他实施例中，这些步骤中的一个或多个可以省略或以其他顺序进行。
假设衬底100通过检查，无源部件122(图6和图7)可以接下来在步骤224中固定到衬底100。一个或多个无源部件可以包含例如一个或多个电容器、电阻器和/或电感器，虽然可以预期其他部件。示出的无源部件122b仅作为示例，并且在其他实施例中数目、类型以及位置可以变化。
在实施例中，本技术可以涉及上面所描述并例如在图6-8中示出的衬底100。如后文所解释的，焊料球可以固定到接触垫110，例如在第二(底部)主平坦表面114上，如图8中所示。如下面所讨论的，在衬底100内提供应力消除层103起到降低焊料球与接触垫110之间的机械应力的作用，机械应力否则可能由于衬底100上的热失配、冲击振动或其他产生应力的力而发展。
上述的衬底100可以具有在0.05mm与0.3mm范围之间的厚度，并且更特别地0.08mm或0.21mm。应理解的是，衬底100在其他实施例中可以具有其他厚度。在上述实施例中，衬底100是双层衬底(夹在电介质层上的两个导电层)。在其他实施例中，衬底100可以包含更多层，例如四层衬底(分散在三个电介质层周围的四个导电层)。
在其他实施例中，本技术可以涉及使用上述的衬底100形成的半导体产品150。特别地，在步骤230中，一个或多个半导体裸芯124可以安装在衬底100上，如图9的边视图中所示。半导体裸芯124可以例如为存储器裸芯，诸如2D NAND闪速存储器或3D BiCS(位成本可规模化)、V-NAND或其他3D闪速存储器，但可以使用其他类型的裸芯124。这些其他类型的半导体裸芯包含但不限于诸如ASIC的控制器裸芯，或诸如SDRAM、DDR SDRAM、LPDDR以及GDDR的RAM。
在包含多个半导体裸芯124的情况下，半导体裸芯124可以以偏移阶梯式配置堆叠上下叠置，以形成如例如图9中所示的裸芯堆叠体。通过使用例如每个裸芯之间的间隔体来为电互连(下面解释的)留下空间，裸芯可以替代地直接上下叠置。堆叠体中所示的裸芯124的数目仅作为示例，且实施例可以包含不同数目的半导体裸芯，包含例如1、2、4、8、16、32或64个裸芯。在其他实施例中可以存在其他数目的裸芯。裸芯可以使用裸芯贴附膜固定到衬底和/或彼此固定。作为一个示例，裸芯贴附膜可以固化到B阶段以在堆叠体中初步固定裸芯124，并且随后固化到最终的C阶段，以将裸芯124永久固定到衬底100。
在步骤234中，半导体裸芯124可以彼此电互连并电互连到衬底100。图10示出了引线键合体128的立体图，引线键合体128在相应的裸芯124上的对应的裸芯接合垫之间顺堆叠体向下形成，并且然后被接合到衬底100的表面112上的接触垫110。引线键合体可以通过球接合技术形成，但其他引线键合技术是可能的。半导体裸芯124在其他实施例中可以通过其他方法彼此电互连并电互连到衬底100，包含通过硅通孔(TSV)。
在将裸芯124电连接到衬底100之后，半导体产品150可以在步骤238中被封裹在模塑料130中，如图11中所示。模塑料130可以包含例如固体环氧树脂树脂、酚醛树脂、熔融石英、晶体石英、碳黑和/或金属氢氧化物。可预期来自其他制造商的其他模塑料。模塑料可以通过各种已知工艺施加，包含通过压缩模塑、FFT(自由流薄)模塑、传递模塑或注射模塑技术。
在步骤240中，焊料球132可以固定到衬底100的下表面114上的接触垫110，如图11和图12中所示。焊料球132可以用来将半导体产品焊接到主机装置，诸如印刷电路板。图12中在衬底100的底表面114上所示的接触垫110和焊料球132的图案仅作为示例，并且在其他实施例中可以变化。在实施例中，焊料球132的数目可以在50与1000之间的范围内，并且更特别地为70至500。
如上面提到的，半导体产品150可以形成在衬底的面板上。在形成和封裹衬底100之后，衬底100可以在步骤242中被彼此单体化，以形成完成的半导体产品150，如图11中所示。可以通过多种切割方法中的任意方法来单体化半导体产品150，方法包含锯割、水射流切割、激光切割、水引导激光切割、干介质切割以及金刚石涂层线切割。尽管直的线切割将限定总体上矩形或正方形形状的半导体产品150，应理解的是，半导体产品150在本技术的其他实施例中可以具有除了矩形和正方形之外的形状。
根据本技术的应力消除层103在上面描述为连续施加在电介质芯102之上的固体层。然而，在其他实施例中无需如此。图13和图14图示了根据其他实施例的图案化的应力消除层103的两个可能性。在其他实施例中，应力消除层的图案可以匹配衬底100的表面114上的接触垫110的图案。其他图案是可能的。
在衬底100内包含应力消除层103起到改善板级可靠性(BLR)的作用，否则板级可靠性在没有层103的情况下可能由于衬底100上和半导体产品150内的热失配、冲击振动或其他产生应力的力而降级。层103能够吸收和耗散接触垫110与焊料球132之间的结合点处以及衬底100中的其它地方的应力。
应变能密度(SED)是在衬底的机械测试中评估BLR性能的良好指标。下面的表1指示了衬底的两个不同组上的热循环测试期间的焊料球的SED的比较。衬底的第一组是不具有应力消除层103(SRL)的常规衬底。衬底的第二组是包含SRL的衬底100的示例。对于两个组中的每个衬底，基于焊料球的粘塑性行为计算SED。每个衬底上的第一焊料球称为锚球(在图12中的焊料球132A的位置中)，并且它是设置为承受相对大量的应力的角部焊料球。每个衬底上的第二焊料球称为功能球(在图12中的焊料球132F的位置中)，因为它在信号传输中使用，并向内、朝向衬底的中心设置。
表1
Figure BDA0001712302040000081
通过在-40℃与85℃之间以15℃/min的斜坡时间并以15min的驻留时间循环第一组和第二组中的每个衬底来进行测试。
在测试1中，两个衬底都是双层衬底，130μm厚，具有60％铜布线覆盖率且没有通孔。如所示出的，具有应力消除层的衬底的锚球和功能球两者都具有比没有应力消除层的衬底更低的测得的SED。
在测试2中，两个衬底都是四层衬底，170μm厚，具有60％铜布线覆盖率且没有通孔。如所示出的，具有应力消除层的衬底的锚球和功能球两者都具有比没有应力消除层的衬底更低的测得的SED。
在测试3中，两个衬底都是双层衬底，130μm厚，本次具有40％铜布线覆盖率且没有通孔。如所示出的，具有应力消除层的衬底的锚球和功能球两者都具有比没有应力消除层的衬底更低的测得的SED。
在测试4中，两个衬底都是双层衬底，130μm厚，具有40％铜布线覆盖率且两者在此测试中都包含通孔。如所示出的，具有应力消除层的衬底的锚球和功能球两者都具有比没有应力消除层的衬底更低的测得的SED。
如从以上测试所见，在衬底内包含应力释放层103对降低应变能密度和改善板级可靠性是有效的。衬底上的机械应力还可能导致衬底和/或半导体产品翘曲。包含应力消除层103的衬底的测试显示了与相同但不包含应力消除层的常规衬底相比翘曲上的1-2μm的降低。
已经出于说明和描述目的提出了本技术的前述详细描述。其不旨在穷举或将本技术限制为所公开的精确形式。鉴于以上教导，许多修改和变化是可能的。选择所描述的实施例以最好地解释本技术的原理及其实际应用，从而是本领域技术人员能够在各种实施例中并以适于预期的特定应用的各种修改来利用本技术。本技术的范围意图由所附权利要求限定。

Claims (20)

1.一种在半导体产品中使用的衬底，包括：
电介质芯，具有第一主平坦表面和第二主平坦表面；
应力消除层，施加到所述电介质芯的第一主平坦表面上，所述应力消除层的模量小于所述电介质芯的模量；
第一导电层，施加到所述电介质芯的第二主平坦表面上，所述第一导电层形成为第一导电图案；以及
第二导电层，施加到所述应力消除层上，所述第二导电层形成为第二导电图案。
2.根据权利要求1所述的衬底，其中所述应力消除层由电介质膜形成。
3.根据权利要求1所述的衬底，其中所述应力消除层由聚酰亚胺、聚苯并恶唑、苯并环丁烯、硅胶和橡胶的化合物中的一种形成。
4.根据权利要求1所述的衬底，其中所述应力消除层具有100MPa至1000MPa的模量。
5.根据权利要求1所述的衬底，其中所述应力消除层具有300MPa至500MPa的模量。
6.根据权利要求1所述的衬底，其中所述应力消除层是连续施加在所述电介质芯之上的固体层。
7.根据权利要求1所述的衬底，其中所述应力消除层降低所述衬底的翘曲。
8.根据权利要求1所述的衬底，其中所述应力消除层耗散所述衬底内的机械应力。
9.根据权利要求1所述的衬底，其中所述第二导电层中的第二导电图案包括多个接触垫，所述衬底还包括所述多个接触垫上的多个焊料球，并且其中所述应力消除层配置为耗散所述多个接触垫与多个焊料球之间的机械应力。
10.根据权利要求1所述的衬底，其中所述应力消除层的厚度在5μm与50μm之间。
11.一种半导体产品，包括：
衬底，包括：
电介质芯，具有第一主平坦表面，
应力消除层，施加到所述电介质芯的第一主平坦表面上，所述应力消除层的模量小于所述电介质芯的模量，以及
第一导电层，施加到所述应力消除层上，所述第一导电层形成为第一导电图案；以及
一个或多个半导体裸芯，安装在所述衬底上并电互连到所述衬底。
12.根据权利要求11所述的半导体产品，还包括固定到所述第一导电图案的接触垫的多个焊料球，所述应力消除层配置为降低所述多个焊料球与所述接触垫之间的应力。
13.根据权利要求11所述的半导体产品，其中所述应力消除层由电介质膜形成。
14.根据权利要求11所述的半导体产品，其中所述应力消除层具有300MPa至400MPa的模量。
15.根据权利要求11所述的半导体产品，其中所述应力消除层配置为降低所述衬底的翘曲。
16.根据权利要求11所述的半导体产品，其中所述应力消除层配置为耗散所述半导体产品内的机械应力。
17.一种制造半导体产品的衬底的方法，包括：
(a)将电介质膜施加到电介质芯上，所述电介质膜具有比所述电介质芯更低的模量；
(b)将第一导电层施加到所述电介质芯上；
(c)将所述第一导电层形成为第一导电图案；
(d)将第二导电层施加到所述应力消除层上；
(e)将所述第二导电层形成为第二导电图案；以及
(f)将焊料球固定到所述衬底，所述电介质膜耗散所述焊料球与所述衬底之间的应力。
18.根据权利要求17所述的方法，其中所述将电介质膜施加到电介质芯上的步骤(a)包括通过薄膜沉积、气相沉积、印刷、旋涂以及干法膜层压中的一种来施加所述电介质膜的步骤。
19.根据权利要求17所述的方法，其中所述将所述第二导电层形成为第二导电图案的步骤(e)包括在所述第二导电图案中形成多个接触垫的步骤，所述焊料球固定到所述多个接触垫，所述电介质膜耗散所述焊料球与所述接触垫之间的应力。
20.一种在半导体产品中使用的衬底，包括：
电介质芯，具有第一主平坦表面和第二主平坦表面；
应力消除构件，施加到所述电介质芯的第一主平坦表面上，以降低所述衬底内的机械应力；
第一导电层，施加到所述电介质芯的第二主平坦表面上，所述第一导电层形成为第一导电图案；以及
第二导电层，施加到所述应力消除构件上，所述第二导电层形成为第二导电图案。
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US20120155055A1 (en) * 2010-12-21 2012-06-21 Tessera, Inc. Semiconductor chip assembly and method for making same

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