CN100477235C - 形成半导体装置的方法 - Google Patents

形成半导体装置的方法 Download PDF

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Publication number
CN100477235C
CN100477235C CNB2005800358985A CN200580035898A CN100477235C CN 100477235 C CN100477235 C CN 100477235C CN B2005800358985 A CNB2005800358985 A CN B2005800358985A CN 200580035898 A CN200580035898 A CN 200580035898A CN 100477235 C CN100477235 C CN 100477235C
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China
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silicon
area
semiconductor device
substrate
layer
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Expired - Lifetime
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CNB2005800358985A
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English (en)
Chinese (zh)
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CN101044621A (zh
Inventor
A·M·韦特
J·奇克
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

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  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
CNB2005800358985A 2004-11-01 2005-10-12 形成半导体装置的方法 Expired - Lifetime CN100477235C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/976,780 2004-11-01
US10/976,780 US7235433B2 (en) 2004-11-01 2004-11-01 Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device

Publications (2)

Publication Number Publication Date
CN101044621A CN101044621A (zh) 2007-09-26
CN100477235C true CN100477235C (zh) 2009-04-08

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Family Applications (1)

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CNB2005800358985A Expired - Lifetime CN100477235C (zh) 2004-11-01 2005-10-12 形成半导体装置的方法

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US (1) US7235433B2 (enExample)
EP (1) EP1815520B1 (enExample)
JP (1) JP5039557B2 (enExample)
KR (1) KR101124657B1 (enExample)
CN (1) CN100477235C (enExample)
TW (1) TWI382492B (enExample)
WO (1) WO2006049833A1 (enExample)

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US7851916B2 (en) * 2005-03-17 2010-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. Strain silicon wafer with a crystal orientation (100) in flip chip BGA package
US7432149B2 (en) * 2005-06-23 2008-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS on SOI substrates with hybrid crystal orientations
US7611937B2 (en) * 2005-06-24 2009-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. High performance transistors with hybrid crystal orientations
US7737532B2 (en) * 2005-09-06 2010-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid Schottky source-drain CMOS for high mobility and low barrier
US7396407B2 (en) * 2006-04-18 2008-07-08 International Business Machines Corporation Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates
US7452784B2 (en) * 2006-05-25 2008-11-18 International Business Machines Corporation Formation of improved SOI substrates using bulk semiconductor wafers
EP2442363A3 (en) * 2006-07-13 2012-07-11 National University Corporation Tohoku Unversity Semiconductor device
FR2905519B1 (fr) * 2006-08-31 2008-12-19 St Microelectronics Sa Procede de fabrication de circuit integre a transistors completement depletes et partiellement depletes
FR2915318B1 (fr) * 2007-04-20 2009-07-17 St Microelectronics Crolles 2 Procede de realisation d'un circuit electronique integre a deux portions de couches actives ayant des orientations cristallines differentes
KR101461206B1 (ko) * 2007-05-17 2014-11-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치 및 그의 제조방법
JP2009072845A (ja) * 2007-09-19 2009-04-09 Oki Semiconductor Co Ltd 半導体デバイスの製造方法
JP5394043B2 (ja) * 2007-11-19 2014-01-22 株式会社半導体エネルギー研究所 半導体基板及びそれを用いた半導体装置、並びにそれらの作製方法
US8039401B2 (en) * 2007-12-14 2011-10-18 Fairchild Semiconductor Corporation Structure and method for forming hybrid substrate
US7956415B2 (en) * 2008-06-05 2011-06-07 International Business Machines Corporation SOI transistor having a carrier recombination structure in a body
US8193616B2 (en) * 2009-06-29 2012-06-05 Kabushiki Kaisha Toshiba Semiconductor device on direct silicon bonded substrate with different layer thickness
CN102790004B (zh) * 2011-05-16 2014-06-11 中国科学院上海微系统与信息技术研究所 一种全隔离混合晶向soi的制备方法
JP6997501B2 (ja) * 2017-03-24 2022-01-17 旭化成エレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
US10748934B2 (en) * 2018-08-28 2020-08-18 Qualcomm Incorporated Silicon on insulator with multiple semiconductor thicknesses using layer transfer
CN111009530A (zh) * 2018-10-08 2020-04-14 世界先进积体电路股份有限公司 半导体结构以及制造方法
US11348944B2 (en) * 2020-04-17 2022-05-31 Taiwan Semiconductor Manufacturing Company Limited Semiconductor wafer with devices having different top layer thicknesses
US12074024B2 (en) * 2021-12-29 2024-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing thereof

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JPH01162376A (ja) 1987-12-18 1989-06-26 Fujitsu Ltd 半導体装置の製造方法
US6063677A (en) * 1996-10-28 2000-05-16 Texas Instruments Incorporated Method of forming a MOSFET using a disposable gate and raised source and drain
US5894152A (en) * 1997-06-18 1999-04-13 International Business Machines Corporation SOI/bulk hybrid substrate and method of forming the same
JP3265569B2 (ja) 1998-04-15 2002-03-11 日本電気株式会社 半導体装置及びその製造方法
KR100282523B1 (ko) * 1998-11-04 2001-02-15 김영환 정전방전 보호 특성을 개선한 에스오아이 반도체 소자 및 그 제조방법
US6214694B1 (en) * 1998-11-17 2001-04-10 International Business Machines Corporation Process of making densely patterned silicon-on-insulator (SOI) region on a wafer
US6476445B1 (en) * 1999-04-30 2002-11-05 International Business Machines Corporation Method and structures for dual depth oxygen layers in silicon-on-insulator processes
US6326247B1 (en) 2000-06-09 2001-12-04 Advanced Micro Devices, Inc. Method of creating selectively thin silicon/oxide for making fully and partially depleted SOI on same waffer
US6492209B1 (en) 2000-06-30 2002-12-10 Advanced Micro Devices, Inc. Selectively thin silicon film for creating fully and partially depleted SOI on same wafer
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JP4322453B2 (ja) * 2001-09-27 2009-09-02 株式会社東芝 半導体装置およびその製造方法
JP3825688B2 (ja) * 2001-12-25 2006-09-27 株式会社東芝 半導体装置の製造方法
JP3943932B2 (ja) * 2001-12-27 2007-07-11 株式会社東芝 半導体装置の製造方法
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US6830962B1 (en) * 2003-08-05 2004-12-14 International Business Machines Corporation Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes
US20050116290A1 (en) 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
US6949420B1 (en) * 2004-03-12 2005-09-27 Sony Corporation Silicon-on-insulator (SOI) substrate having dual surface crystallographic orientations and method of forming same
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JP2006040911A (ja) * 2004-07-22 2006-02-09 Renesas Technology Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
KR101124657B1 (ko) 2012-04-19
TWI382492B (en) 2013-01-11
US7235433B2 (en) 2007-06-26
EP1815520B1 (en) 2012-05-02
JP2008518475A (ja) 2008-05-29
CN101044621A (zh) 2007-09-26
KR20070065902A (ko) 2007-06-25
JP5039557B2 (ja) 2012-10-03
TW200620537A (en) 2006-06-16
EP1815520A1 (en) 2007-08-08
WO2006049833A1 (en) 2006-05-11
US20060091427A1 (en) 2006-05-04

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