CN100472783C - 一种接触方法和利用该方法产生的器件 - Google Patents

一种接触方法和利用该方法产生的器件 Download PDF

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CN100472783C
CN100472783C CNB2005800393086A CN200580039308A CN100472783C CN 100472783 C CN100472783 C CN 100472783C CN B2005800393086 A CNB2005800393086 A CN B2005800393086A CN 200580039308 A CN200580039308 A CN 200580039308A CN 100472783 C CN100472783 C CN 100472783C
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dielectric film
metal
coat
substrate
electric interface
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CN101061582A (zh
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卡尔·韦德纳
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Siemens AG
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Abstract

本发明涉及一种接触至少一个位于一基板(2)和/或至少一个布置在所述基板(2)上的组件(3)的一表面上的电接触面(1)的方法，所述组件特别为半导体芯片。所述方法包括下列步骤：在真空条件下将至少一个由电绝缘塑料材料制成的绝缘膜(4)层压在所述基板(2)和所述组件的具有所述接触面(1)的表面上；通过在所述绝缘膜(4)上开一窗口(6)来露出所述表面上待接触的接触面(1)。本发明的特征在于使露出的接触面(1)与一绝缘膜(4)上的至少一个金属镀层(5)进行平面接触。

Description

一种接触方法和利用该方法产生的器件
技术领域
本发明涉及一种接触一个或多个位于一基板和/或至少一个组件的表面上的电接触面的方法，所述方法包括下述步骤：在真空条件下将至少一个由电绝缘塑料材料制成的绝缘膜层压到所述基板和组件的表面上，使得绝缘膜紧密地覆盖且附着在所述表面上，其中该表面具有一个或多个接触面。
背景技术
WO03/030247中公开了一种接触方法，其还包括以下其他步骤：通过在绝缘膜上开窗口露出表面上需要接触的各个接触面，用一导电材料层对露出的接触面进行平面接触(sheet contacting)。根据这种方法，进行过平面接触后，在所述导电材料层中或在所述导电材料层上会产生至少一个导电迹线(conductor track)。制备多层器件时，须重复实施层压、露出接触面、接触和产生导电迹线等各步骤。
传统接触方法的不足之处在于实现接触的过程很复杂，特别是对一基板表面上的组件的接触。在此过程中需要实施大量的处理步骤。
发明内容
本发明的目的是克服传统方法的缺点和简化对一基板表面上的接触面的接触，特别是简化对一基板表面上的组件上的接触面的接触。
这个目的通过下述的接触方法和利用该方法产生的器件实现。
一种接触至少一个位于一基板和/或至少一个布置在所述基板上的组件的一表面上的电接触面的方法，所述方法包括下列步骤：在真空条件下将至少一个由电绝缘塑料材料制成的绝缘膜层压在所述基板和/或所述组件的具有所述电接触面的表面上，通过在所述绝缘膜上开一窗口来露出所述表面上待接触的电接触面，进行所述层压之前将所述金属镀层涂覆在所述的至少一个绝缘膜的至少一个表面侧上，使露出的电接触面与一绝缘膜上的至少一个金属镀层进行平面接触。
一种具有至少一个位于一基板和/或至少一个布置在所述基板上的组件的一表面上的电接触面的器件，其中，所述基板和/或所述组件的表面上通过真空技术层压有至少一个电绝缘的绝缘膜，所述绝缘膜的至少一个表面侧上涂覆有至少一个金属镀层，所述绝缘膜具有一从所述电接触面到所述金属镀层的窗口，所述电接触面在所述窗口处与所述金属镀层彼此平面接触。
所述方法用于仅对一个基板结构的接触或对一基板上的至少一个组件的接触或对至少一个带有一基板的组件的接触。在此情况下，可以通过将绝缘膜紧密地覆盖和附着在其各自下面的表面上，以将至少一个用电绝缘塑料材料制成的绝缘膜层压在基板或组件的表面上，特别是在真空条件下。
在层压之前或之后，制备至少一个建构在绝缘膜的至少一个表面侧上的金属镀层。这用于制备导电迹线或导电迹线结构或接触结构。可在层压之前就用传统方法来建构这种连接结构。这样，可以在一绝缘膜上生成具有单侧金属镀层或双侧金属镀层的薄膜。涂覆在一塑料薄膜整个表面或部分表面上的铜镀层或一塑料薄膜上预建构有导电迹线的铜镀层特别适合用作金属化绝缘膜。也可使用在电阻率或可加工性方面类似的其他金属。可在各层压步骤之前或之后，可以用一简单的方式形成窗口，机械方式例如有冲压，化学方式例如有刻蚀，物理方式例如有激光、等离子。可通过将金属镀层从外向内导向电接触面或将电接触面从内向外导向金属镀层来实现接触。在一有利的压力与一有利的温度条件下进行接触。平面接触为优选接触形式。电子组件、LED、半导体芯片或功率半导体芯片适合用作所述组件。这也可以通过传统接触方法的大量处理步骤实现。
可考虑将任意一种基于有机物质或无机物质的电路载体用作所述基板。这种基板例如是PCB(Printed Circuit Board，印刷电路板)基板、DCB基板、IM(Insulated Metal，绝缘金属)基板、HTCC(High Temperature CofiredCeramics，高温共烧陶瓷)基板和LTCC(Low Temperature Cofired Ceramics，低温共烧陶瓷)基板。
在一真空压机(vacuum press)中进行层压是有利的。为此可考虑使用真空成型(vacuum forming)、液压真空压制(hydraulic vacuum forming)、真空气压压制(vacuum gas-pressure pressing)或类似的层压方法。均衡地施加压力是有利的。例如在温度为100℃至250℃、压力为1巴(bar)至10巴的条件下进行层压。对精确的层压处理参数，也就是说压力、温度、时间等等决定于基板的拓扑、用于制作绝缘膜的塑料材料和绝缘膜的厚度。
为进行平面接触，对导电材料进行物理或化学沉积是有利的。这种物理方法指的是溅射和气相沉积(Physical Vapor Deposition，PVD，物理气相沉积)。化学沉积可以气相(Chemical Vapor Deposition，CVD，化学气相沉积)和/或液相(Liquid Phase Chemical Vapor Deposition，液相化学气相沉积)形式进行。也可考虑先用其中一种方法涂覆一较薄的导电部分层(electricallyconducting partial layer)，再在这个导电部分层上通过电流沉积法形成一较厚的导电部分层。
本发明的方法优选且有利地使用一种基板，其表面上装配有一个或多个半导体芯片，特别是功率半导体芯片，在每个半导体芯片中存在一个或多个待接触的接触面，并且在真空条件下将所述的至少一个绝缘膜层压在这个表面上，使得绝缘膜紧密地覆盖在这个包括每个半导体芯片和每个接触面在内的表面上以及附着在这个包括每个半导体芯片在内的表面上。
其中，绝缘膜例如建构为特别可克服一最大约为5mm的高度差。这一高度差由基板的拓扑和布置在基板上的半导体芯片引起。也可例如以焊接方式安装SMD(surface mounted device表面贴装器件)组件。
绝缘膜可用任意一种热塑性塑料、热固性塑料及其混合物制成。本发明的方法所使用的薄膜优选及有利地为一基于聚酰亚氨(PI)、聚乙烯(PE)、多酚、聚醚醚酮(PEEK)和/或环氧化物的塑料材料制成的薄膜。其中，为改善表面的附着性，薄膜可具有一胶粘涂层(adhesive coating)。
根据一有利改进方案，进行层压前先将金属镀层涂覆在一另外的位于朝向接触面的表面侧上、由电绝缘塑料制成的即将被层压的绝缘膜上。这一附加的绝缘膜不具有开口，而是优选在开口区域内具有所述金属镀层。
根据一有利改进方案，使用一具有一配有一个或多个功率半导体芯片的表面的基板。
根据一有利改进方案，不同表面侧上的金属镀层彼此之间存在电连接。这一点可借助触针实现。
根据一进一步有利改进方案，使用一由基于聚酰亚氨、聚乙烯、多酚、聚醚醚酮和/或环氧化物的塑料制成的绝缘膜，将铜、铝、铁和/或银或类似的导电体用作单侧或双侧金属镀层。借此可使塑料薄膜的一个表面侧或两个表面侧上均涂镀有金属。原则上也可使用纯金属层。
根据一进一步有利改进方案，绝缘膜的金属镀层制备成涂覆在绝缘膜的整个表面或部分表面上，或制备成预建构。连接结构符合电气或电子组件之间的必要连接，所述电气或电子组件可用传统方法安装在一基板上。金属结构例如可通过光刻工艺形成。也可使用传统的建构方法。
可通过激光烧蚀(laser ablation)、冲压、刻蚀或光刻等方法来建构绝缘膜的金属镀层。
可通过对具有金属镀层的金属化绝缘膜进行热压、焊接和/或粘接来实施对每个露出的接触面的平面接触。
附加的金属化连接膜可用于平面接触，其中金属化连接膜具有至少一个金属镀层。可通过焊接或粘接来固定所述连接膜。
根据一进一步改进方案，通过焊接和/或粘接金属化绝缘膜(即具有金属镀层的绝缘膜)来实施对每个露出的接触面的接触。所述接触为平面接触。可通过将金属化绝缘膜向内导向露出的接触面来实现所述接触。在接触面以相应方法制备而成的情况下，也可相反地通过将露出的接触面向外导向金属导电迹线来实现接触。
根据一进一步有利改进方案，通过重复绝缘层的层压步骤来形成一多层结构。绝缘层厚度也可以通过这个方法增大。
根据一进一步有利改进方案，使用一厚度(d)例如特别为25μm至250μm的金属化绝缘膜。
根据一进一步有利改进方案，先在最上层的绝缘膜远离基板的一侧上涂覆一绝缘覆层，再以形成一密封结构(hermetic seal)为目的在这个绝缘覆层上涂覆一金属层，所述金属层借助一直接的金属连接部分实现与基板的一边缘区域的直接接触。所述金属层用作具有传热特性的覆盖物，能起到机械保护的作用。位于金属层和具有一金属镀层的金属化绝缘膜之间的绝缘覆层起到的是电绝缘的作用。
根据一进一步有利改进方案是在所述密封结构的上方和/或基板的下方安装散热体。借此可更好地向周围散热。
其他有利改进方案涉及的是借助所述方法而产生的器件。
附图说明
下面借助附图对本发明的有利实施方式进行详细说明，其中：
图1为本发明的器件或方法的一第一实施例的图示；
图2为本发明的器件或方法的一第二实施例的图示；
图3为本发明的器件的一第三实施例的图示；以及
图4为本发明的器件的第三实施例的简化俯视图。
具体实施方式
图1显示的是一器件根据一实施例所具有的构造，所述器件具有至少一个电接触面1，所述电接触面位于一基板2和/或至少一个布置在所述基板上的组件3的一表面上。基板2和组件3的表面上通过真空技术层压有至少一个电绝缘的绝缘膜4，所述绝缘膜紧贴并附着在其下面的表面上。所述的至少一个绝缘膜4的至少一个表面侧上涂覆有至少一个金属镀层5。绝缘膜4在接触面1处具有至少一个窗口6，接触面1在所述窗口处与金属镀层5平面接触。此外，绝缘膜4上涂覆有一绝缘覆层7，绝缘覆层7上涂覆有一金属层8，其中，所述金属层借助一直接的金属连接部分与基板的一边缘区域直接接触，从而形成所述器件的一密封结构。所述密封结构的上方和基板的下方分别布置有一散热体9。
图2显示的是通过所述的至少一个绝缘膜4上的窗口6进行接触的一实施方式。举例而言，通过焊接和/或粘接金属化绝缘膜4a来实施对每个露出的接触面1的接触。也可使用类似的连接方法。所述接触为平面接触。可通过将金属化绝缘膜4a向内导向露出的接触面1来实现所述接触。在接触面1以相应方法制备而成的情况下，也可相反地通过将露出的接触面1的金属化连接膜4b(建构为独立结构或接触面1的延续部分)向外导向金属导电迹线5来实现接触。
图3显示的是如何利用建构为露出在基板2的外缘之外的一金属化绝缘膜4a来连接外部的连接件。借此还可平衡高度差。这种灵活的接触类型可代替或补充附加的插接或类似的连接方式。可通过改变薄膜和铜的厚度使之与机械、电气、热和类似的要求相匹配。
如图3所示，位于一绝缘膜4上的金属化绝缘膜4a从基板2左侧突出基板2之外，并位于一非粘附性的覆层结构10之上，所述覆层结构例如为一聚四氟乙烯结构10。从绝缘膜4和4a上取下聚四氟乙烯层10或使聚四氟乙烯层10与绝缘膜4和4a分离后，可使绝缘膜4和4a露出或突出在基板2之外。
图4显示的是图3的一简化俯视图。从中可清楚看到露出的绝缘膜4和4a。绝缘膜4和4a均突出在基板2的表面之外。此外还可通过在一绝缘覆层7上建构一金属层8来形成所述器件的一密封结构。

Claims (17)

1.一种接触至少一个位于一基板(2)和/或至少一个布置在所述基板(2)上的组件(3)的一表面上的电接触面(1)的方法，所述方法包括下列步骤：
在真空条件下将至少一个由电绝缘塑料材料制成的绝缘膜(4)层压在所述基板(2)和/或所述组件的具有所述电接触面(1)的表面上，
通过在所述绝缘膜(4)上开一窗口(6)来露出所述表面上待接触的电接触面(1)，
其特征在于，
进行所述层压之前将所述金属镀层(5)涂覆在所述的至少一个绝缘膜(4)的至少一个表面侧上，
使露出的电接触面(1)与一绝缘膜(4)上的至少一个金属镀层(5)进行平面接触。
2.根据权利要求1所述的方法，其特征在于，
所述组件为半导体芯片。
3.根据权利要求1或2所述的方法，其特征在于，
进行所述层压之前将所述金属镀层(5)涂覆在一绝缘膜(4)的朝向所述电接触面(1)的表面侧上，所述绝缘膜(4)为一在露出所述电接触面后附加层压的绝缘膜。
4.根据权利要求1所述的方法，其特征在于，使不同表面侧上的金属镀层(5)彼此电气相连。
5.根据权利要求1所述的方法，其特征在于，绝缘膜(4)由基于聚酰亚氨、聚乙烯、多酚、聚醚醚酮和/或环氧化物的塑料材料制成，使用铜、铝、铁和/或银作为单侧或双侧金属镀层(5)。
6.根据权利要求1所述的方法，其特征在于，所述绝缘膜(4)的金属镀层(5)涂覆在所述绝缘膜的整个表面或部分表面上，或预先制成。
7、根据权利要求1所述的方法，其特征在于，
所述绝缘膜(4)的金属镀层(5)以导电迹线的形式预先制成。
8.根据权利要求1所述的方法，其特征在于，通过激光、冲压或湿化学法建构所述绝缘膜(4)的金属镀层(5)。
9.根据权利要求1所述的方法，其特征在于，通过对具有所述金属镀层(5)的金属化绝缘膜(4a)进行热成型、热压、焊接或粘接来实施对每个露出的电接触面(1)的平面接触。
10.根据权利要求1所述的方法，其特征在于，使用具有至少一个金属镀层(5)的附加金属化连接膜(4b)实现平面接触。
11.根据权利要求1所述的方法，其特征在于，将具有所述金属镀层(5)的金属化绝缘膜(4a)建构为露出在所述基板(2)的外缘之外来连接外部连接件。
12.根据权利要求1所述的方法，其特征在于下列其他步骤：
在最上层的绝缘膜(4)上涂覆一绝缘覆层(7)，
在所述绝缘覆层(7)上涂覆一金属层(8)，所述金属层(8)借助一直接的金属连接部分与所述基板(2)的一边缘区域直接接触，从而形成一密封结构。
13.根据权利要求12所述的方法，其特征在于下述其他步骤：
在所述密封结构的上方和/或所述基板(2)的下方安装至少一个散热体(9)。
14.一种具有至少一个位于一基板(2)和/或至少一个布置在所述基板(2)上的组件(3)的一表面上的电接触面(1)的器件，其中，
所述基板(2)和/或所述组件(3)的表面上通过真空技术层压有至少一个电绝缘的绝缘膜(4)，
所述绝缘膜(4)的至少一个表面侧上涂覆有至少一个金属镀层(5)，
所述绝缘膜(4)具有一从所述电接触面(1)到所述金属镀层(5)的窗口(6)，
所述电接触面(1)在所述窗口处与所述金属镀层(5)彼此平面接触。
15.根据权利要求14所述的器件，其特征在于，具有所述金属镀层(5)的金属化绝缘膜(4a)建构为露出在所述基板(2)的外缘之外来连接外部连接件。
16.根据权利要求14或15所述的器件，其特征在于，
最上层的绝缘膜(4)上附加地涂覆有一绝缘覆层(7)，以及
所述绝缘覆层(7)上附加地安装有一金属层(8)，其中，所述金属层(8)借助一直接的金属连接部分与所述基板(2)的一边缘区域直接接触，从而形成所述器件的一密封结构。
17.根据权利要求16所述的器件，其中，所述密封结构的上方和/或所述基板(2)的下方安装有至少一个散热体(9)。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007043001A1 (de) * 2007-09-10 2009-03-12 Siemens Ag Bandverfahren für elektronische Bauelemente, Module und LED-Anwendungen
DE102007057346B3 (de) * 2007-11-28 2009-06-10 Fachhochschule Kiel Laminierte Leistungselektronikbaugruppe
DE102008003788A1 (de) * 2008-01-10 2009-07-16 Robert Bosch Gmbh Elektrische Schaltungsanordnung mit mindestens einem Leistungshalbleiter und Verfahren zu deren Herstellung
US8410600B2 (en) * 2009-10-02 2013-04-02 Arkansas Power Electronics International, Inc. Semiconductor device with protecting film and method of fabricating the semiconductor device with protecting film
US20110126880A1 (en) * 2009-11-30 2011-06-02 Du Pont Apollo Limited Thin-Film Photovoltaic Panel and Method of Producing the Same
DE102010012457B4 (de) * 2010-03-24 2015-07-30 Semikron Elektronik Gmbh & Co. Kg Schaltungsanordnung mit einer elektrischen Komponente und einer Verbundfolie
DE102011083423A1 (de) * 2011-09-26 2013-03-28 Siemens Aktiengesellschaft Kontaktfederanordnung und Verfahren zur Herstellung derselben
US8716870B2 (en) * 2011-12-16 2014-05-06 General Electric Company Direct write interconnections and method of manufacturing thereof
US20130264721A1 (en) 2012-04-05 2013-10-10 Infineon Technologies Ag Electronic Module
DE102012218561A1 (de) * 2012-10-11 2014-04-17 Siemens Aktiengesellschaft Elektronikmodul, Mehrfachmodul und Verfahren zum Herstellen eines Elektronikmoduls
WO2016080333A1 (ja) * 2014-11-21 2016-05-26 株式会社村田製作所 モジュール
DE102017210894A1 (de) * 2017-06-28 2019-01-03 Robert Bosch Gmbh Elektronikmodul und Verfahren zur Herstellung eines Elektronikmoduls

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL159818B (nl) * 1972-04-06 1979-03-15 Philips Nv Halfgeleiderinrichting, bevattende een flexibele isolerende folie, die aan een zijde is voorzien van metalen geleider- sporen.
US4918811A (en) * 1986-09-26 1990-04-24 General Electric Company Multichip integrated circuit packaging method
JPH03211757A (ja) * 1989-12-21 1991-09-17 General Electric Co <Ge> 気密封じの物体
DE4219410A1 (de) * 1992-06-13 1993-12-16 Hoechst Ag Heißsiegelfähige, antistatisch beschichtete Folien und Folienlaminate, Verfahren zu deren Herstellung und deren Verwendung
US5336928A (en) 1992-09-18 1994-08-09 General Electric Company Hermetically sealed packaged electronic system
US5492586A (en) * 1993-10-29 1996-02-20 Martin Marietta Corporation Method for fabricating encased molded multi-chip module substrate
US5745984A (en) * 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
DE19617055C1 (de) * 1996-04-29 1997-06-26 Semikron Elektronik Gmbh Halbleiterleistungsmodul hoher Packungsdichte in Mehrschichtbauweise
US6239980B1 (en) * 1998-08-31 2001-05-29 General Electric Company Multimodule interconnect structure and process
US6710456B1 (en) * 2000-08-31 2004-03-23 Micron Technology, Inc. Composite interposer for BGA packages
US7432116B2 (en) * 2001-02-21 2008-10-07 Semiconductor Energy Laboratory Co., Ltd. Method and apparatus for film deposition
DE10121970B4 (de) * 2001-05-05 2004-05-27 Semikron Elektronik Gmbh Leistungshalbleitermodul in Druckkontaktierung
US6788724B2 (en) * 2001-07-06 2004-09-07 Intel Corporation Hermetically sealed external cavity laser system and method
DE10136743B4 (de) 2001-07-27 2013-02-14 Epcos Ag Verfahren zur hermetischen Verkapselung eines Bauelementes
JP2005515616A (ja) * 2001-09-28 2005-05-26 シーメンス　アクチエンゲゼルシヤフト 基板の電気的コンタクト面の接続方法及び電気的コンタクト面を備えた基板からなるデバイス
DE10164502B4 (de) * 2001-12-28 2013-07-04 Epcos Ag Verfahren zur hermetischen Verkapselung eines Bauelements
DE10308928B4 (de) * 2003-02-28 2009-06-18 Siemens Ag Verfahren zum Herstellen freitragender Kontaktierungsstrukturen eines ungehäusten Bauelements
EP1597756A2 (de) * 2003-02-28 2005-11-23 Siemens Aktiengesellschaft Verbindungstechnik für leistungshalbleiter mit grossflächigen anschlüssen
CN100499053C (zh) * 2003-02-28 2009-06-10 西门子公司 用于具有遵循表面轮廓的电绝缘材料层的功率半导体的布线工艺
DE10314172B4 (de) 2003-03-28 2006-11-30 Infineon Technologies Ag Verfahren zum Betreiben einer Anordnung aus einem elektrischen Bauelement auf einem Substrat und Verfahren zum Herstellen der Anordnung
JP4471735B2 (ja) * 2004-05-31 2010-06-02 三洋電機株式会社 回路装置
DE102006009723A1 (de) * 2006-03-02 2007-09-06 Siemens Ag Verfahren zum Herstellen und planaren Kontaktieren einer elektronischen Vorrichtung und entsprechend hergestellte Vorrichtung

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JP2008522394A (ja) 2008-06-26
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CN101061582A (zh) 2007-10-24
US7910470B2 (en) 2011-03-22
EP1817795A1 (de) 2007-08-15

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