CN105518853A - 嵌入式电子封装和相关联的方法 - Google Patents
嵌入式电子封装和相关联的方法 Download PDFInfo
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- CN105518853A CN105518853A CN201480049617.0A CN201480049617A CN105518853A CN 105518853 A CN105518853 A CN 105518853A CN 201480049617 A CN201480049617 A CN 201480049617A CN 105518853 A CN105518853 A CN 105518853A
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- semiconductor die
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- 238000004100 electronic packaging Methods 0.000 title claims description 35
- 238000000034 method Methods 0.000 title claims description 16
- 229920000106 Liquid crystal polymer Polymers 0.000 claims abstract description 110
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 claims abstract description 110
- 239000004065 semiconductor Substances 0.000 claims abstract description 53
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 239000010949 copper Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000004927 fusion Effects 0.000 claims description 4
- 239000011159 matrix material Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 49
- 238000005538 encapsulation Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012792 core layer Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 210000001525 retina Anatomy 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4817—Conductive parts for containers, e.g. caps
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- H—ELECTRICITY
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4864—Cleaning, e.g. removing of solder
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
- H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
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- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H—ELECTRICITY
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
- A61N1/00—Electrotherapy; Circuits therefor
- A61N1/18—Applying electric currents by contact electrodes
- A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
- A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
- A61N1/372—Arrangements in connection with the implantation of stimulators
- A61N1/375—Constructional arrangements, e.g. casings
- A61N1/3758—Packaging of the components within the casing
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/2401—Structure
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- H01L2224/732—Location after the connecting process
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- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
电子封装包含半导体裸片(60)、从所述半导体裸片向外延伸的导电柱(62)以及液晶聚合物(LCP)主体(74),所述液晶聚合物主体包围所述半导体裸片且具有在其中接纳所述导电柱中的对应导电柱的开口(77)。第一互连层(80)在所述LCP主体上且接触所述开口。导电主体(82)在所述开口中以将所述导电柱连接到所述第一互连层。
Description
技术领域
本发明涉及封装电子组件的领域,并且更具体来说,涉及封装嵌入式半导体裸片以及相关方法。
背景技术
封装电子组件的基本目的是为了保护组件且同时通过封装从组件中提供电气互连。可制造性和保护是关键问题。由于持续增长的市场需求,电子封装不断地朝向较小尺寸和减小的占用面积而同时仍保持环境稳固发展。尽管这些电子封装是小型化的,但是它们仍然是高度功能性的。
嵌入式电子封装集成需要具有相容的处理温度、相容的材料特性以及有利的电特性的介电材料。当前,若干嵌入式技术已经展示为使用层合板和聚合物电路板。
因特尔公司(IntelCorporation)已经研发出无焊内建层,其不使用焊接凸点来将半导体裸片附接到封装线。内建层围绕半导体裸片形成或内建。内建层通常单独地制造且随后粘合在一起。ImberaElectronicsOY已经研发出集成模块板(IMB),其中待嵌入的组件具有在所述组件的两侧上的接触端子,因此节约空间。通用电气公司(GeneralElectricCompany)具有ChipsFirstBuild-UpTM,其中使用无焊过程。弗劳恩霍夫IZM(FraunhoferIZM)基于标准电路板设备和技术使用层合嵌入式裸片“聚合物内芯片”封装方法,其中半导体裸片粘合到衬底、与介电质层合,且连接到外部电路。卡西欧计算机有限公司(CasioComputerCo.Ltd.)使用晶片级封装(WLP),其中所述封装直接在晶片上完成且随后通过切割而单体化以用于组装。裸片的所有封装和测试操作由整个晶片制造和晶片级测试替代。
上述方法均无法利用液晶聚合物材料(LCP),所述液晶聚合物材料自从在2003年变得可商购后已经获得相当大的注意。LCP材料具有非常低的透湿性且可以提供近气密密封而不会相对较厚。此外,LCP材料的介电特性在暴露于湿气下时不会发生改变。
在Thompson等人的标题为《多层LCP衬底中的MMIC的封装(PackagingofMMICsinMultilayerLCPSubstrates)》的文章中揭示了用于保护半导体裸片的LCP封装。如图1中所说明,电子封装20包含使用具有用于半导体裸片的经切开空腔50的层合工艺嵌入在LCP层30到42之间的半导体裸片22。
LCP核心层30、34、38和42是4密耳厚,而LCP粘合层32、36和40是2密耳厚。如在所述文章中所论述,低熔解温度(285℃)LCP粘合层32、36和40用于粘附大体上较厚较高熔解温度(315℃)LCP核心层30、34、38和42以产生均质的LCP电子封装20。
即使鉴于上述技术,出现的无线通信和传感器应用也需要超薄的、柔性的、耐化学的、近气密的且买得起的嵌入式电子封装。当涉及例如生物医学感测和成像时尤其如此。因此,仍需要改进将半导体裸片嵌入在电子封装中的技术。
发明内容
鉴于前述背景,本发明的目标因此是提供一种低剖面电子封装,其具有相对较简单地产生的嵌入式半导体裸片。
根据本发明的此目标、特征和优点以及其它目标、特征和优点通过一种电子封装提供,所述电子封装包括半导体裸片、从半导体裸片向外延伸的多个导电柱以及液晶聚合物(LCP)主体,所述液晶聚合物主体包围半导体裸片且具有在其中的多个开口,所述开口接纳多个导电柱中的对应导电柱,同时使对应的间隙与导电柱的顶部相邻。第一互连层可以在LCP主体上,且多个导电主体可以在对应的间隙中以将多个导电柱连接到第一互连层。
所述电子封装可以进一步包括在LCP主体上在其与第一互连层相反的一侧上的第二互连层。多个导电通孔可以延伸穿过LCP主体以连接第一和第二互连层。
LCP主体有利地允许电子封装为低剖面且具有高灵活性的以用于应用在共形电路中。半导体裸片可以是近气密密封的,且LCP主体的介电特性在暴露于湿气下时仍相对不变。并且,因为LCP封装与人体生物相容,所以所述电子封装具有广泛范围的手术植入应用。
所述电子封装的又另一个优点是它可以用作用于更加复杂的架构的构建块,其中LCP主体可以一个在另一个上面的方式堆叠,同时仍提供经堆叠层中的半导体裸片之间的电气接口。这在半导体裸片并不处于丝焊或倒装芯片配置的情况下实现。替代地,在LCP主体已经围绕半导体裸片形成之后,导电主体有利地将导电柱连接到第一互连层,且导电通孔有利地将第一和第二互连层连接在一起。导电柱和导电通孔可以使用电镀形成。因此,电子封装以减少的成本相对较简单地产生。
LCP主体可以在半导体裸片的所有侧上包围半导体裸片且与其连续接触。另外,LCP主体可以侧向包围导电柱中的每一个且与其连续接触。
第一互连层、导电柱以及导电主体可以各自包含例如铜。半导体裸片可以包括例如射频(RF)集成电路。
另一个方面涉及一种用于制造电子封装的方法,其包括:提供半导体裸片,其具有多个向外延伸的导电柱;以及形成LCP主体,其包围半导体裸片且具有在其中的多个开口,所述开口接纳多个导电柱中的对应导电柱,同时使对应的间隙与导电柱的顶部相邻,且所述LCP主体具有在LCP主体上的第一互连层。所述方法可以进一步包括在对应的间隙中形成多个导电主体以将多个导电柱连接到第一互连层。
附图说明
图1是根据现有技术的电子封装的截面视图。
图2是根据本发明的电子封装的截面视图。
图3是图2中的区域A的放大截面视图。
图4是图2中的电子封装的分解截面视图,其说明具有裸片接纳空腔的第一LCP主体区段、半导体裸片以及第二LCP主体区段。
图5是没有导电柱和导电通孔的在图2中说明的电子封装的截面视图。
图6是具有在于第一互连层上形成互连轨迹(trace)之前处于适当的位置处的导电柱和导电通孔的在图2中说明的电子封装的截面视图。
图7是说明用于制造图2中说明的电子封装的方法的流程图。
具体实施方式
现在将参考附图在下文中更加全面地描述本发明,在这些附图中示出了本发明的优选实施例。然而,本发明可以按许多不同形式实施,并且不应被解释为限于本文所阐述的实施例。更准确地说,提供这些实施例是为了使得本发明将是透彻并且完整的,并且这些实施例将把本发明的范围完整地传达给所属领域的技术人员。相同数字始终指代相同元件。
首先参考图2和3,电子封装50包括半导体裸片60、从半导体裸片向外延伸的多个导电柱62以及包围半导体裸片60的液晶聚合物(LCP)主体70。LCP主体70具有在其中的多个开口77,所述开口接纳多个导电柱62中的对应导电柱,同时使对应的间隙与导电柱的顶部相邻。第一互连层80在LCP主体70上。多个导电主体82在对应的间隙中以将导电柱62连接到第一互连层80。
如下文将更详细地解释,LCP主体70包含第一LCP主体区段72和第二LCP主体区段74,所述第二LCP主体区段在熔合接口76处与第一LCP主体区段接合。作为实例,LCP主体50的总厚度可以在8到12密耳的范围内。取决于半导体裸片60的厚度和既定应用,LCP主体70的厚度将相应地改变,如所属领域的技术人员容易地了解。
除电子封装50为低剖面且具有高灵活性之外,半导体裸片60可以是近气密密封的,且LCP主体70的介电特性在暴露于湿气下时仍相对较稳定。并且,因为LCP主体70与人体生物相容,所以电子封装50具有广泛范围的手术植入应用,例如具有医师可访问远程监控系统的无线起搏器或可植入视网膜假体。
电子封装50进一步包含在LCP主体上在其与第一互连层80相反的一侧上的第二互连层90。导电通孔100延伸穿过LCP主体70以连接第一和第二互连层80、90。此配置有利地准许将电子封装50用作用于更加复杂架构的构建块,其中LCP主体70可以一个在另一个上面的方式堆叠,同时仍提供经堆叠层中的半导体裸片60之间的电气接口。组装成本减少且制造的容易性得到改进,因为提供了与半导体裸片60之间的电气接口,而不必使半导体裸片处于丝焊或倒装芯片配置。
现在参考其余图式,包含图7中说明的流程图300,将论述制造所说明的电子封装50的步骤。从开始(框302)起,具有多个向外延伸的导电柱62的半导体裸片60提供在304框处且如通过图4中的电子封装50的分解视图所说明。导电柱62是例如铜,且用于对准和随后的互连目的。其它金属可以用于替代铜或可以与铜一起使用,如所属领域的技术人员容易地了解。半导体裸片60可以是例如射频(RF)集成电路。
第一LCP主体区段72包含具有裸片接纳空腔79的第一LCP层112,提供在框306处。尽管第一LCP层112说明为单一LCP层,但多个LCP层通过被使用。在框308处,半导体裸片60定位在裸片接纳空腔79中,其中多个导电柱62延伸远离裸片接纳空腔。
第二LCP主体区段74提供在框310处且包含第二LCP层114,且第一互连层80在第二LCP层上,其中多个开口或通孔77延伸穿过第一互连层和第二LCP层两者。激光可以用于形成开口77。第一互连层80是例如铜。其它金属可以用于替代铜或可以与铜一起使用,如所属领域的技术人员容易地了解。如同第一LCP层112一样,第二LCP层114可以形成有单一或多个LCP层。
在框312处,第二LCP主体区段74中的开口77与导电柱62对准。从半导体裸片60向外延伸的导电柱62有利地用于对准和互连目的。参考图5,在314框处,第一和第二LCP主体区段72、74随后接合在一起,其中第二LCP主体区段中的多个开口77接纳导电柱62中的对应导电柱以使对应的间隙97与导电柱62的顶部相邻。导电柱62因此凹进开口77中。
第一和第二LCP主体区段72、74与其间包含的半导体裸片60层合,使得LCP主体70在半导体裸片60的所有侧上包围所述半导体裸片且与其连续接触。并且,LCP主体70侧向包围导电柱62中的每一个且与其连续接触。
在第一和第二LCP主体区段72、74中的LCP层112、114连同半导体裸片60的层合在约285℃到315℃的温度范围内实现,如所属领域的技术人员容易地了解。如图5中所说明,形成熔合接口76,其中LCP层112、114接合在一起。
在框316处,第二互连层90形成于第一LCP主体区段72中的LCP层112上,且在LCP层112的与第二LCP主体区段74中的LCP层114相反的一侧上。第二互连层90也是铜。然而,其它金属可以用于替代铜或可以与铜一起使用,如所属领域的技术人员容易地了解。第二互连层90可以在第一和第二LCP层112、114的层合之前形成,而非在所述层合之后形成。举例来说,框306还可以包含提供第一LCP主体区段72以将LCP层112和第二互连层90包含在其上。
在第一和第二LCP主体区段72、74的层合之后,在框318处且如图5中所说明,使用通过第一和第二LCP主体区段72、74的激光形成通孔或贯通孔99。另外,激光还可以用于清洁、铣削和重新界定第二LCP主体区段74中的开口77中的对应的间隙。
在320框处且如图6中所说明,导电主体82形成于对应的间隙97中以将导电柱62连接到第一互连层80,且形成导电通孔100,其延伸穿过第一和第二LCP主体区段72、74以连接第一和第二互连层80、90。如上文所提到,导电柱62和第一和第二互连层80、90是铜。导电主体82和导电通孔100使用电镀铜形成。在电镀之后,如图2中所说明的互连轨迹130经蚀刻界定以完成电子封装50,如所属领域的技术人员容易地了解。所述方法在框322处结束。
所属领域的技术人员将想到本发明的许多修改及其它实施例,其具有前述描述和相关联的图式中所呈现的教示内容的益处。因此,应理解,本发明不限于所揭示的具体实施例并且意图将修改和实施例包含于所附权利要求书的范围内。
Claims (10)
1.一种电子封装,其包括:
半导体裸片;
多个导电柱,其从所述半导体裸片向外延伸;
液晶聚合物(LCP)主体,其包围所述半导体裸片且具有在其中的多个开口,所述开口接纳所述多个导电柱中的对应导电柱,同时使对应的间隙与所述导电柱的顶部相邻;
在所述LCP主体上的第一互连层;以及
在所述对应的间隙中的多个导电主体,其用于将所述多个导电柱连接到所述第一互连层。
2.根据权利要求1所述的电子封装,其进一步包括:
在所述LCP主体上在其与所述第一互连层相反的一侧上的第二互连层;以及
多个导电通孔,其延伸穿过所述LCP主体以连接所述第一和第二互连层。
3.根据权利要求1所述的电子封装,其中所述LCP主体在所述半导体裸片的所有侧上包围所述半导体裸片且与其连续接触,并且其中所述LCP主体侧向包围所述多个导电柱中的每一个且与其连续接触。
4.根据权利要求1所述的电子封装,其中所述第一互连层、所述多个导电柱以及所述多个导电主体各自包括铜。
5.根据权利要求1所述的电子封装,其中所述LCP主体包括:
第一LCP主体区段,其具有接纳所述半导体裸片的裸片接纳空腔;以及
第二LCP主体区段,其具有在其中的所述多个开口且在熔合接口处与所述第一LCP主体区段接合。
6.一种用于制造电子封装的方法,其包括:
提供半导体裸片,其具有多个向外延伸的导电柱;
形成液晶聚合物(LCP)主体,其包围所述半导体裸片且具有在其中的多个开口,所述开口接纳所述多个导电柱中的对应导电柱,同时使对应的间隙与所述导电柱的顶部相邻,且所述液晶聚合物主体具有在所述LCP主体上的第一互连层;以及
在所述对应的间隙中形成多个导电主体以将所述多个导电柱连接到所述第一互连层。
7.根据权利要求6所述的方法,其中形成所述LCP主体包括:
提供第一LCP主体区段,其具有接纳所述半导体裸片的裸片接纳空腔,所述半导体裸片具有延伸远离所述裸片接纳空腔的所述多个向外延伸的导电柱;
提供第二LCP主体区段,其包括LCP层,所述LCP层具有在其上的所述第一互连层,且具有延伸穿过所述第一互连层和所述LCP层两者的所述多个开口;
使所述第二LCP主体区段中的所述多个开口与所述多个导电柱对准;以及
在熔合接口处将所述第一和第二LCP主体区段接合在一起。
8.根据权利要求6所述的方法,其进一步包括
在所述LCP主体上在其与所述第一互连层相反的一侧上形成第二互连层;以及
形成多个导电通孔,其延伸穿过所述LCP主体以连接所述第一和第二互连层。
9.根据权利要求6所述的方法,其中所述LCP主体经形成以在所述半导体裸片的所有侧上包围所述半导体裸片且与其连续接触,并且其中所述LCP主体经形成以侧向包围所述多个导电柱中的每一个且与其连续接触。
10.根据权利要求6所述的方法,其中所述第一互连层和所述多个导电柱各自包括铜,并且其中所述多个导电主体各自包括电镀铜。
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IT201700055942A1 (it) | 2017-05-23 | 2018-11-23 | St Microelectronics Srl | Procedimento per fabbricare dispositivi a semiconduttore, dispositivo e circuito corrispondenti |
IT201700055983A1 (it) | 2017-05-23 | 2018-11-23 | St Microelectronics Srl | Procedimento per produrre dispositivi a semiconduttore, dispositivo a semiconduttore e circuito corrispondenti |
US20200111765A1 (en) * | 2018-10-09 | 2020-04-09 | Medtronic, Inc. | Electronic assembly and method of forming same |
FR3089423B1 (fr) * | 2018-12-07 | 2020-12-18 | Commissariat Energie Atomique | Dispositif médical implantable à architecture améliorée |
JP7353255B2 (ja) * | 2020-10-30 | 2023-09-29 | 三菱電機株式会社 | 半導体装置用の筐体の製造方法 |
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- 2014-07-31 KR KR1020167006771A patent/KR101719112B1/ko active IP Right Grant
- 2014-07-31 WO PCT/US2014/049177 patent/WO2015038250A1/en active Application Filing
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Also Published As
Publication number | Publication date |
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KR20160054488A (ko) | 2016-05-16 |
KR101719112B1 (ko) | 2017-03-22 |
US9443789B2 (en) | 2016-09-13 |
US20160351459A1 (en) | 2016-12-01 |
CN105518853B (zh) | 2017-09-19 |
US9892984B2 (en) | 2018-02-13 |
WO2015038250A1 (en) | 2015-03-19 |
US20150069621A1 (en) | 2015-03-12 |
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