CN100463181C - 存储设备的电容器及其制造方法 - Google Patents
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Abstract
提供了一种存储设备的电容器及其制造方法,用于实现高集成度的半导体存储设备并保持优良的疲劳特性。在具有晶体管结构的存储设备的电容器中,电容器包括形成在晶体管结构的掺杂区上的、包括金属电极和金属氧化物电极的下部电极,围绕下部电极的铁电层,和形成在铁电层上的上部电极。
Description
技术领域
本发明涉及一种存储设备的电容器及其制造方法,尤其涉及一种具有垂直形状的、不需蚀刻下部电极的金属电极/金属氧化物电极的存储设备的电容器及其制造方法。
背景技术
铁电随机存取存储器(FRAM)是一种非易失性存储设备,应用于计算机、MP3播放器、数字照相机、PDA和其它电子设备中。为了提供高集成度的铁电存储设备,应当增大单位面积铁电电容器的电容。
对于给定的介电材料,为了增大电容必须增大电容器的面积。这由下面的公式1给出。
<公式1>
其中ε是介电常数,A是有效面积,t是介电层的厚度。
也就是说,通过减小介电层的厚度和增大有效面积能够增大电容。然而,当采用平面电容器结构时,增大电容器的面积限制了半导体设备的集成度。特别地,在由一个晶体管和一个电容器组成的存储结构中,用于电容器的空间必然被减小,如果用于电容器的空间被减小,那么电容器的平面面积也被减小,从而降低其电容。因此,为了增大电容和提高设备的集成度,一直致力于发展三维电容器结构。
三维铁电电容器包括两种类型的结构:沟槽型(trench type)和堆栈型(stack type)。沟槽型采用形成在晶体管结构中的下部金属电极,其被蚀刻为凹形,其上淀积铁电薄膜。堆栈型通过在具有突出的下部金属电极的晶体管结构上淀积铁电薄膜形成。参照美国专利No.6368910解释这两种类型的三维铁电电容器。
图1A和1B是分别说明沟槽型和堆栈型三维铁电电容器的截面图,其公开于美国专利No.6368910中。
图1A说明沟槽型铁电电容器,其中第三绝缘层(SiO2)3淀积在第二绝缘层2上,并且蚀刻第三绝缘层3,从而形成凹形开口5。在凹形开口5上形成Ru或Ru氧化物层6,并采用化学机械抛光(CMP),暴露出第三绝缘层3的上表面。因此,Ru或Ru氧化物层6仅保留在凹形开口5内部。然后,依次淀积铁电薄膜7和上部电极8,从而形成三维铁电电容器。参考数字1表示第一绝缘层,参考数字4表示Ru插塞(plug),参考数字9表示多晶硅插塞。
铁电电容器具有下部电极/铁电/上部电极结构,特别地,为了保持铁电电容器的疲劳特性(fatigue characteristics),下部电极应当采用金属氧化物电极。然而,通常用于铁电电容器的金属氧化物电极,例如IrO2、RuO2等,在高温真空气氛中自身分解。因此,如果在金属氧化物电极上淀积铁电薄膜,其铁电特性会退化。因此,铁电电容器的下部电极应当形成为使得金属电极覆盖金属氧化物电极,且三维铁电电容器应当具有同样的下部电极结构。
结果是,下部电极变厚,并且如果在窄直径的沟槽(凹形开口)上淀积厚的下部电极6,高宽比迅速增大。因此,在铁电薄膜形成期间难于获得稳定的阶梯覆盖率(stable step coverage)。当在具有高的高宽比的下部电极上采用化学气相淀积(CVD)淀积典型的铁电材料如PZT或BST时,在高于约500℃的温度下几乎不可能获得阶梯覆盖率。
图1B是说明堆栈型三维电容器结构的截面图。Ru插塞11形成在介电层12内部,且连接到下部电极14,并在其上依次形成铁电层15和上部电极16。
因为根据下部金属电极的厚度的阶梯覆盖率对铁电层影响很小,堆栈型电容器结构比图1A中示出的沟槽型电容器结构易于形成。然而,如图1B中所示的通过形成下部电极和蚀刻电极制造的堆栈型电容器结构在其实际制造工艺中也有许多问题,下面具体解释。
第一,由于化学性质稳定的贵金属通常用作下部电极14,如Ir、Pt、Ru等,几乎不可能在垂直方向上蚀刻下部电极。因此,通常以约70°的角度进行蚀刻。然而,因为下部表面变的比上部表面更大,这增大了电容器的面积。结果是,存储器设备的单位单元面积也增大,从而导致难于制造高集成度的存储器。
第二,生产昂贵。与平面型电容器结构相比较,三维电容器结构的面积由形成在下部电极14的侧面上的面积而增大,因此在堆栈型中必须尽可能厚的形成下部电极14。然而,考虑生产成本,由于贵金属下部电极14的成本是整个制造成本中的主要考虑因素,优选不制造厚的下部电极14。而且,由于拉长了用于淀积和蚀刻下部电极14的时间,主要地增大了生产成本。
第三,通过蚀刻形成的堆栈型电容器引起提高金属氧化物电极的疲劳特性的问题。如果在上部电极16和下部电极14上施加电场,在垂直方向上在垂直的上部和下部电极16和14中产生铁电层15的极化现象。已知金属氧化物电极中氧原子沿垂直于电场的方向移动,从而改善疲劳特性。为了通过蚀刻得到堆栈型电容器,如果将下部电极层涂布在金属氧化物电极上并蚀刻,由于金属氧化物电极垂直于电场,形成在下部电极14上的铁电层15表现出优良的疲劳特性。然而,下部电极14侧面上的金属氧化物电极并不垂直于电场,从而使疲劳特性退化。
发明内容
本发明提供了一种存储设备的垂直堆栈型电容器,其能够不需蚀刻下部电极而形成、具有改善的疲劳特性,及其制造方法。
根据本发明的一个方面,提供了一种具有晶体管结构的存储设备的电容器,其包括形成在晶体管结构的掺杂区上的、包括金属电极和金属氧化物电极的下部电极,围绕下部电极形成的铁电层,和形成在铁电层上的上部电极。
本发明的下部电极可以包括形成在垂直于晶体管结构的方向上的金属电极,和形成在金属电极内部的金属氧化物电极。
本发明的金属电极可以包括选自Pt、Ir、Ru、Pd和Rh的材料,金属氧化物电极可以包括选自RuO2、IrO2、SrRuO和CaRuO的材料。
本发明的下部电极可以形成为圆柱状。
本发明的电容器还可以包括位于晶体管结构和下部电极之间的氧化停止层,其电连接到晶体管结构的掺杂区。
本发明的氧化停止层可以由至少包括TiN和TiAlN之一的材料组成。
根据本发明的另一方面,提供了一种具有晶体管结构的存储设备的电容器,其包括形成在晶体管结构的掺杂区上的、包括金属电极和金属氧化物电极的下部电极,围绕下部电极下部、形成在晶体管结构上的绝缘层,形成在绝缘层上的粘接层,围绕下部电极暴露出的外部形成的铁电层,和形成在铁电层上的上部电极。
本发明的粘接层可以由包括选自Ti、TiN、TiO2和TiAlN的至少一种材料组成。
根据本发明的另一方面,提供了一种包括晶体管结构的存储设备的电容器的制造方法,其包括依次在电连接到晶体管结构的掺杂区的部分上形成氧化停止层,在氧化停止层上形成绝缘层,蚀刻绝缘层,从而形成暴露氧化停止层的沟槽;在沟槽内部淀积金属和金属氧化物,从而形成下部电极,除去沟槽外部的金属、金属氧化物和绝缘层;以及依次在下部电极上形成铁电层和上部电极。
而且,淀积和除去的第二步操作可以包括在沟槽内部淀积金属,从而形成金属电极;在沟槽内部的金属电极上淀积金属氧化物填满沟槽,从而形成金属氧化物电极;通过CMP工艺除去绝缘层上的金属和金属氧化物;以及通过蚀刻除去绝缘层。
根据本发明的另一方面,提供了一种包括晶体管结构的存储设备的电容器的制造方法,其包括依次在电连接到晶体管结构的掺杂区的部分上形成氧化停止层,形成绝缘层、粘接层和第二绝缘层,并蚀刻第二绝缘层、粘接层和绝缘层,从而形成暴露氧化停止层的沟槽;在沟槽内部淀积金属和金属氧化物,从而形成下部电极,除去沟槽外部的金属、金属氧化物和第二绝缘层;以及依次在粘接层上的暴露出的下部电极上形成铁电层和上部电极。
而且,形成铁电层和上部电极的第三步操作可以包括在粘接层上暴露出的下部电极表面上淀积铁电材料,从而形成铁电层;在铁电层表面上淀积上部电极材料,从而形成上部电极;以及除去淀积在粘接层上的、平行于粘接层的方向上的铁电材料和上部电极材料。
附图说明
通过参照附图的具体的典型实施例的描述,本发明的上述和其它特点和优点将更清楚,其中:
图1A和1B是说明传统技术的存储设备的电容器的图;
图2A是说明根据本发明的第一实施例的存储设备的电容器的图;
图2B是说明根据本发明的第二实施例的存储设备的电容器的图;
图3A-3F是说明根据本发明的第一实施例的存储设备的制造方法的图;
图4A-4F是说明根据本发明的第二实施例的存储设备的制造方法的图。
具体实施方式
现在将在下文中参照示出优选实施例的附图更充分地描述本发明。然而,本发明可以表达为各种形式,并且不应当被限制为这里给出的实施例。而且,提供这些实施例是为了使公开内容充分和完整,并充分地将本发明的思想传达给本领域技术人员。在图中,为清晰起见放大了层和区域的厚度。整个说明中相同的数字指的是相同的部件。
图2A是说明根据本发明的第一实施例的存储设备的电容器的图。见图2A,本发明的电容器形成在包括晶体管结构的下部结构上。图2A中示出的晶体管结构与典型的存储设备的下部结构相同。也就是说,第一掺杂区22a和第二掺杂区22b形成在半导体衬底21的预定部分中,且第一掺杂区22a和第二掺杂区22b以与半导体衬底21相反的极性掺杂。栅结构23、24形成在第一掺杂区22a和第二掺杂区22b之间的半导体衬底21上。栅结构包括栅绝缘层23和栅电极24。在图中,参考数字25表示位线,参考数字26表示连接到第二掺杂区22b的金属插塞。
因此,根据本发明的存储设备的电容器形成在如上形成的下部结构上。包括金属电极36和金属氧化物电极35的、具有圆柱形的下部电极35、36形成在氧化停止层31上。围绕下部电极35、36,依次形成铁电层37和上部电极38。
图2B是说明根据本发明的第二实施例的存储设备的电容器的图。见图2B,本发明的电容器形成在包括晶体管结构的下部结构上。图2B中示出的晶体管结构与典型的存储设备的下部结构相同。也就是说,第一掺杂区22a和第二掺杂区22b形成在半导体衬底21的预定部分中,且第一掺杂区22a和第二掺杂区22b以与半导体衬底21相反的极性掺杂。栅结构23、24形成在第一掺杂区22a和第二掺杂区22b之间的半导体衬底21上。栅结构包括栅绝缘层23和栅电极24。
因此,根据本发明的第二实施例存储设备的电容器形成在如上形成的下部结构上。包括金属电极36和金属氧化物电极35的、具有圆柱形的下部电极35、36形成在氧化停止层31上。围绕下部电极35、36,在氧化停止层31上形成绝缘层32和粘接层33。围绕下部电极35、36,依次在粘接层33上形成铁电层37和上部电极38。
根据本发明的第二实施例的存储设备的电容器不同于第一实施例的地方在于绝缘层32支撑下部电极35、36的侧面。这是因为绝缘层32稳定地支撑具有高的高宽比的下部电极35、36。如果下部电极35、36具有低的高宽比,那么根据本发明的第一实施例的电容器是更有利的,但是如果下部电极35、36具有高的高宽比,那么根据本发明的第二实施例的电容器是更有利的。
以下,参照附图,具体解释根据本发明的实施例的存储设备的电容器的制造方法。图3A-3F是说明根据本发明的第一实施例的存储设备的电容器的制造方法的图。
见图3A,氧化停止层31形成在具有电连接到晶体管结构的第二掺杂区的金属插塞26的下部结构上,绝缘层32形成在氧化停止层31上。由于下部结构能够采用传统技术的晶体管结构形成,因此下面简单解释一下。形成具有栅绝缘层23和栅电极24的晶体管结构,并淀积层间绝缘层27例如氧化硅层(SiO2)。然后,蚀刻预定部分,从而形成用于电连接第二掺杂区22b和铁电电容器的孔。淀积导电材料例如钨(W),并通过CMP工艺平坦化,从而完成下部结构的形成。
淀积氧化停止层31,其由例如TiAlN或TiN材料组成,以阻止在用于淀积铁电薄膜的氧化气氛中由例如钨材料组成的导电插塞26的氧化。可以选择性调节淀积厚度和淀积装置,并且在本发明的实施例中,使用MOCVD、ALD(原子层淀积)等淀积约5nm的厚度。然后,在氧化停止层31上使用例如PECVD形成由氧化硅(SiO2)等组成的绝缘层32。
然后,如图3B所示,在绝缘层32中对应于导电插塞26的部分上,使用干法蚀刻等形成具有几十或几百纳米直径的沟槽或孔32′。
然后,如图3C所示,通过ALD工艺形成由例如Pt、Ir、Ru、Pd、Rh等金属材料组成的金属电极36。在金属电极36上形成由例如RuO2、IrO2、SrRuO和CaRuO等金属氧化物组成的金属氧化物电极35,从而形成包括金属/金属氧化物电极36、35的混合状(hybrid shape)下部电极36、35。
然后,如图3D所示,除去形成在绝缘层32上的混合电极(hybridelectrodes)35、36的材料并通过CMP工艺平坦化,通过BOE(缓冲氧化物蚀刻)工艺化学蚀刻除去绝缘层32。因此,在氧化停止层31上仅保留圆柱状的金属/金属氧化物电极36、35。
然后,如图3E所示,以约500℃的温度通过MOCVD工艺在下部电极35、36上形成铁电层37,并使用ALD法在铁电层37上淀积例如Ir或Ru材料,从而形成上部电极38。
然后,如图3F所示,通过构图和蚀刻除去除了垂直状的铁电层37和上部电极38部分之外的铁电材料和金属材料,从而完成根据本发明的第一实施例的存储设备的电容器的形成。
下文中,参照附图4A-4F具体解释根据本发明的第二实施例的存储设备的电容器的制造方法。图4A-4F是说明根据本发明的第二实施例的存储设备的电容器的制造方法的图。
见图4A,氧化停止层31形成在具有电连接到晶体管结构的第二掺杂区22b的金属插塞26的下部结构上,绝缘层32形成在氧化停止层31上。由于下部结构能够采用传统技术的晶体管结构形成,因此这里省略其具体解释。
淀积氧化停止层31,其由例如TiAlN或TiN材料组成,以阻止在用于淀积铁电薄膜的氧化气氛中由例如钨材料组成的导电插塞26的氧化。可以选择性调节淀积厚度和淀积装置,并且在本发明的实施例中,使用MOCVD、ALD等淀积。通过除去其两侧能够使氧化停止层31形成为具有预定长度。然后,在氧化停止层31上使用例如PECVD形成由氧化硅(SiO2)等组成的绝缘层32。在绝缘层32上淀积如Ti、TiN、TiO2、TiAlN等材料,从而形成粘接层33。在粘接层33上形成由氧化硅(SiO2)组成的第二绝缘层34。因为仍要保留绝缘层32,所以必须形成粘接层33,不同于本发明的第一实施例,如果绝缘层32直接接触铁电层37,会发生一些问题,其中绝缘层32中的硅材料扩散,由于两者界面处的粘接性弱,诸层会相互分离。
然后,如图4B所示,在绝缘层32、粘接层33和第二绝缘层34中对应于导电插塞26的部分上,使用干法蚀刻等形成具有几十或几百纳米直径的沟槽或孔32′。
然后,如图4C所示,通过ALD工艺淀积由例如Pt、Ir、Ru、Pd、Rh等金属材料组成的金属电极36。然后,在金属电极36上形成由例如RuO2、IrO2、SrRuO和CaRuO等金属氧化物组成的金属氧化物电极35,从而形成包括金属/金属氧化物电极36、35的混合状下部电极36、35。这样,金属/金属氧化物电极36、35能够完全填满沟槽或孔32′。
然后,如图4D所示,除去形成在第二绝缘层34上的混合电极35、36的材料并通过CMP等平坦化,通过BOE(缓冲氧化物蚀刻)工艺化学蚀刻除去第二绝缘层34。因此,在粘接层33上仅保留圆柱状的金属/金属氧化物电极36、35。
然后,如图4E所示,以约500℃的温度通过MOCVD工艺在下部电极35、36上形成铁电层37,并使用ALD法在铁电层37上淀积例如Ir或Ru材料,从而形成上部电极38。
然后,如图4F所示,通过构图和蚀刻除去除了垂直状的铁电层37和上部电极38之外的粘接层33上的部分的铁电材料和金属材料,从而完成根据本发明的第二实施例的存储设备的电容器的形成。
如上所述,本发明具有以下优点。
第一,下部电极为混合状,包括金属电极和金属氧化物电极,从而提供了一种具有稳定的疲劳特性的存储设备的三维铁电电容器。
第二,通过提供薄的下部电极,其在半导体存储设备的制造中占生产成本的主要部分,从而减小了生产成本。
第三,通过提供堆栈型三维铁电电容器能够获得一种高集成度的半导体存储设备。
虽然参照其典型实施例特别示出和描述了本发明,但是本领域技术人员应当理解为,不脱离权利要求限定的本发明的精神和范围,可以在对其形式和细节做各种变形。
Claims (17)
1.一种包括晶体管结构的存储设备的电容器,所述电容器包括:
形成在晶体管结构的掺杂区上的、包括金属电极和金属氧化物电极的下部电极;
围绕下部电极形成的铁电层;和
形成在铁电层上的上部电极,
其中,所述下部电极包括:
形成在垂直于所述晶体管结构的方向上的金属电极;和
形成在所述金属电极内部的金属氧化物电极。
2.根据权利要求1的存储设备的电容器,其中所述金属电极包括选自由Pt、Ir、Ru、Pd和Rh构成的组中的至少一种材料。
3.根据权利要求1的存储设备的电容器,其中所述金属氧化物电极包括选自由RuO2、IrO2、SrRuO和CaRuO构成的组中的至少一种材料。
4.根据权利要求1的存储设备的电容器,其中所述下部电极形成为圆柱形。
5.根据权利要求1的存储设备的电容器,其中所述电容器还包括位于所述晶体管结构和所述下部电极之间的氧化停止层,其电连接到所述晶体管结构的掺杂区。
6.根据权利要求5的存储设备的电容器,其中所述氧化停止层至少包括TiN和TiAlN之一。
7.一种包括晶体管结构的存储设备的电容器,所述电容器包括;
形成在晶体管结构的掺杂区上的、包括金属电极和金属氧化物电极的下部电极;
围绕所述下部电极下部、形成在所述晶体管结构上的绝缘层;
形成在所述绝缘层上的粘接层;
围绕所述下部电极暴露出的外部的铁电层;和
形成在所述铁电层上的上部电极,
其中,所述下部电极包括:
形成在垂直于所述晶体管结构的方向上的金属电极;和
形成在所述金属电极内部的金属氧化物电极。
8.根据权利要求7的存储设备的电容器,其中所述金属电极包括选自由Pt、Ir、Ru、Pd和Rh构成的组中的至少一种材料。
9.根据权利要求7的存储设备的电容器,其中所述金属氧化物电极包括选自由RuO2、IrO2、SrRuO和CaRuO构成的组中的至少一种材料。
10.根据权利要求7的存储设备的电容器,其中所述下部电极形成为圆柱形。
11.根据权利要求7的存储设备的电容器,其中所述电容器还包括位于所述晶体管结构和所述下部电极之间的氧化停止层,其电连接到所述晶体管结构的掺杂区。
12.根据权利要求11的存储设备的电容器,其中所述氧化停止层至少包括TiN和TiAlN之一。
13.根据权利要求7的存储设备的电容器,其中所述粘接层由包括选自由Ti、TiN、TiO2和TiAlN构成的组中的至少一种材料组成。
14.一种包括晶体管结构的存储设备的电容器的制造方法,所述方法包括:
a)依次在电连接到晶体管结构的掺杂区的部分上形成氧化停止层,在所述氧化停止层上形成绝缘层,蚀刻所述绝缘层,从而形成暴露所述氧化停止层的沟槽;
b)在所述沟槽内部淀积金属来形成金属电极,在所述沟槽内部的金属电极上淀积金属氧化物以填满沟槽来形成金属氧化物电极,从而形成下部电极,除去所述沟槽外部的金属、金属氧化物和绝缘层;和
c)依次在所述下部电极上形成铁电层和上部电极。
15.根据权利要求14的方法,其中在所述b)操作中:
通过CMP工艺除去所述绝缘层上的金属和金属氧化物;和
通过蚀刻除去所述绝缘层。
16.一种包括晶体管结构的存储设备的电容器的制造方法,所述方法包括:
a)依次在电连接到晶体管结构的掺杂区的部分上形成氧化停止层、绝缘层、粘接层和第二绝缘层,并蚀刻所述第二绝缘层、粘接层和绝缘层,从而形成暴露出所述氧化停止层的沟槽;
b)在所述沟槽内部淀积金属来形成金属电极,在所述沟槽内部的金属电极上淀积金属氧化物以填满沟槽来形成金属氧化物电极,从而形成下部电极,并除去所述沟槽外部的金属、金属氧化物和第二绝缘层;和
c)在所述粘接层上的暴露出的下部电极上依次形成铁电层和上部电极。
17.根据权利要求16的方法,其中在所述b)操作中:
通过CMP工艺除去所述第二绝缘层上的金属和金属氧化物;和
通过蚀刻除去所述第二绝缘层。
18.根据权利要求16的方法,其中所述c)操作包括:
在所述粘接层上暴露出的下部电极表面上淀积铁电材料,从而形成铁电层;
在所述铁电层表面上淀积上部电极材料,从而形成上部电极;和
除去淀积在所述粘接层上的、平行于粘接层的方向上的铁电材料和上部电极材料。
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- 2005-05-06 JP JP2005134840A patent/JP2005322925A/ja not_active Withdrawn
- 2005-05-08 CN CNB2005100762580A patent/CN100463181C/zh not_active Expired - Fee Related
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US7250649B2 (en) | 2007-07-31 |
KR20050105695A (ko) | 2005-11-08 |
KR100601953B1 (ko) | 2006-07-14 |
CN1694256A (zh) | 2005-11-09 |
JP2005322925A (ja) | 2005-11-17 |
US20080038846A1 (en) | 2008-02-14 |
US20060001070A1 (en) | 2006-01-05 |
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