CN100431396C - 减小粘附体之间的伸长失配的芯片接合工艺以及由此制造的半导体封装 - Google Patents
减小粘附体之间的伸长失配的芯片接合工艺以及由此制造的半导体封装 Download PDFInfo
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Abstract
一种减小粘附体之间伸长失配的芯片接合工艺涉及使热膨胀系数失配的半导体芯片和衬底在沿待通过焊接来接合的表面的方向上从它们的室温状态基本上等量地热膨胀。然后将热膨胀的半导体芯片和衬底焊接在一起,形成多个焊接接点,然后冷却到室温。所述过程可使焊接产生的伸长失配减小到小于根据在焊接后将衬底和半导体芯片从焊料固化温度冷却到室温所预期的伸长的一半,从而减小了焊接后的残余应力、焊接接点中的残余塑性变形、衬底中的残余塑性变形以及半导体芯片的翘曲。
Description
技术领域
本发明涉及电子组件及其制造方法。更具体地说,本发明涉及将半导体芯片焊接到衬底上的改进方法并且涉及由此制造的半导体封装。
背景技术
图7A和7B所示的传统半导体封装1包括封装衬底2和位于衬底上的芯片或管芯3。芯片的下面或正面携带集成电路,所述集成电路有多个位置或连接线用于使集成电路与封装衬底上的各接触焊盘4相接触,将芯片电连接到封装衬底上。更具体地说,芯片具有安装在其上的一些支座5。支座由导电的高熔化温度材料形成,例如铜。支座电连接到芯片上集成电路的相应的位置或连接线。焊接接点6再将芯片支座连接到封装衬底上的接触焊盘。焊接接点在传统装配过程中形成,在所述过程中,把带支座的芯片和带事先加有焊料的接触焊盘的衬底设置成彼此接触,并一起加热到高于焊料的熔化温度的温度,而且一起冷却。在所述接合过程中衬底上接触焊盘上的焊料回熔,浸湿支座,形成焊接接点。
传统半导体封装中的芯片通常由硅制成,其热膨胀系数(CTE)约为2.6-3.3ppm/℃(每1℃百万分之几)。过去,封装衬底一般用陶瓷材料制造,其CTE通常低于6ppm/℃。在半导体封装加热或冷却时,包括在封装装配时与焊接相关联的加热或冷却,半导体芯片和封装衬底之间CTE的失配幅度还不会引起半导体芯片的显著弯曲。但这种失配仍然会因焊接后的残余应力(特别是在脆性材料中)而出现问题。
近年来,已逐渐从使用陶瓷作为封装衬底材料转向用其它材料,例如塑料或其它有机材料,它们具有较低的成本和优良的电性能。这些代替材料的一个问题是:和半导体芯片相比,它们通常具有较高的CTE。例如,一些塑料衬底的CTE在17ppm/℃左右。利用较高的CTE封装衬底材料在封装中造成的较大的CTE失配会导致一些有害的影响,例如焊料疲劳,封装和芯片翘曲,芯片断裂等。
已提出许多建议来减少因封装材料CTE失配引发的问题。例如,美国专利No.5,369,551提出一种表面安装应力消除界面系统和方法,其中将柔顺的界面装置既连接到衬底又连接到芯片上来消除CTE失配。在受让人的美国专利No.5,889,652中,用一个柔性部分将衬底的焊接部分与衬底的接触部分分隔开以便允许相对移动而将焊料接点上的应力减至最小。
美国专利No.5,931,311公开了在焊接过程中使用的一种受控支座互连,来减少CTE失配引起的焊接接点的塑性变形。专利权人解释说支座越大,发生的塑性变形越小,这样就可得到元件/互连的较长的耐用性和循环寿命。
为减少CTE失配对半导体封装寿命的影响所采用的另一种途径涉及到增强芯片抗翘曲的能力。例如,在受让人的美国专利No.5,936,304中,建议在芯片背面使用一层保护层。在另一实例中,半导体芯片形成有倒角边缘,在封装被加热时这些倒角边缘和位于其上的环氧树脂一起降低了芯片上的应力,如受让人的美国专利No.6,049,124中所述。
发明内容
随着芯片日趋增大,由于从芯片中心到芯片和衬底相互接合处的距离增大,有关CTE失配引发的对半导体封装影响的问题也日益明显。需要有一种改进的方法来接合CTE失配材料和用其制造的电子组件/半导体封装,以降低或减少CTE失配引发的影响,如焊料疲劳、封装和芯片翘曲、芯片断裂等。
按照本发明,提供了一种将热膨胀系数失配的半导体芯片和衬底相互焊接的方法,所述方法包括:使所述半导体芯片和所述衬底在沿其待焊接的表面的方向上基本上等量地热膨胀;以及将所述热膨胀后的半导体芯片和衬底相互焊接在一起。
按照本发明,提供了一种将热膨胀系数失配的第一和第二部分彼此接合的方法,所述方法包括:使所述第一和第二部分的每一部分在沿其待接合的表面的方向上基本上等量地热膨胀;在高温下将所述热膨胀的第一和第二部分相互接合在一起;以及将所述接合的第一和第二部分冷却到室温。
按照本发明,提供了一种电子组件,包括:具有第一热膨胀系数的衬底;具有不同于所述第一热膨胀系数的第二热膨胀系数的半导体芯片;连接所述半导体芯片和所述衬底的多个焊接接点;其中,由于焊接,在所述电子组件的所述多个焊接接点两端的所述芯片和衬底在室温下具有由热膨胀系数差引起的伸长失配和由此在所述电子组件中引起的应力;以及其中,所述伸长失配的幅度和由此在所述电子组件中引起的应力小于根据在所述多个焊接接点焊接之后将所述衬底和半导体芯片从所述焊料的固化温度冷却到室温所预期值的一半。
按照本发明,提供了一种电子组件,包括:具有第一热膨胀系数的衬底;具有不同于所述第一热膨胀系数的第二热膨胀系数的半导体芯片;连接所述半导体芯片和所述衬底的多个焊接接点;其中,由于焊接,在所述电子组件的所述多个焊接接点两端的所述芯片和衬底在室温下具有由热膨胀系数差引起的伸长失配;其中,所述伸长失配的幅度小于根据在所述多个焊接接点焊接之后将所述衬底和半导体芯片从所述焊料的固化温度冷却到室温所预期幅度的一半;以及其中,所述衬底包括凸起在所述衬底表面上的多个支座元件,以及所述多个焊接接点将所述半导体芯片连接到所述多个支座元件中相应的支座元件的上部。
按照本发明,提供了一种半导体封装,包括:具有至少15ppm/℃的第一热膨胀系数的封装衬底,所述封装衬底具有多个接触部分;半导体芯片,具有小于所述封装衬底的所述热膨胀系数的至少2.7ppm/℃的第二热膨胀系数,所述多个芯片的正面具有多个焊接接头,所述半导体芯片位于所述衬底上,所述多个焊接接头通过将所述半导体芯片电连接到所述封装衬底上的所述焊接接点连接到所述多个接触部分中相应的接触部分上;其中,由于焊接,在所述半导体封装的所述各个焊接接点两端的所述半导体芯片和封装衬底在室温下具有由热膨胀系数差引起的伸长失配和由此在所述半导体封装中引起的应力;其中,所述伸长失配的幅度和由此在所述半导体封装中引起的应力小于根据在所述焊接接点焊接之后将所述衬底和半导体芯片从所述焊料的固化温度冷却到室温所预期值的一半。
按照本发明,还提供了一种半导体封装,包括:具有至少15ppm/℃的第一热膨胀系数的封装衬底,所述封装衬底具有多个接触部分;半导体芯片,具有小于所述封装衬底的所述热膨胀系数的至少2.7ppm/℃的第二热膨胀系数,所述多个芯片的正面具有多个焊接接头,所述半导体芯片位于所述衬底上,所述多个焊接接头通过将所述半导体芯片电连接到所述封装衬底上的所述焊接接点连接到所述多个接触部分中相应的接触部分上;其中,由于焊接,在所述半导体封装的所述各个焊接接点两端的所述半导体芯片和封装衬底在室温下具有由热膨胀系数差引起的伸长失配;其中,所述伸长失配的幅度小于根据在所述焊接接点焊接之后将所述衬底和半导体芯片从所述焊料的固化温度冷却到室温所预期幅度的一半;以及其中,所述多个接触部分包括凸起在所述衬底表面上的多个支座元件,以及所述焊接接点将所述半导体芯片连接到所述多个支座元件中相应的支座元件的上部。
附图说明
本专利文档包含至少一幅彩色附图。带彩色附图的专利复制件可在提出要求并支付所需费用后由专利和商标局提供。
图1为衬底上芯片组件的中心线CL右半部的示意的截面图;
图2为用于按照本发明制造半导体封装的本发明示范实施例的方法示意图;
图3A-3C和3D-3E分别为按照图2的方法制造的芯片和衬底上在不同时间的彩色编码温度分布,例如,其中图3A-3C对应于芯片放到衬底上一秒钟后的时间,图3A是芯片和衬底组件的一部分的截面图,图3B是图3A中衬底的右端的视图,图3C是图3A的方框A中接点区的放大视图,而图3D-3E对应于冷却10分钟的时间,图3D是组件的一部分的截面图,而图3E是图3D所示衬底右侧的端视图。
图4示出在用本发明的方法时,利用示范实施例的瞬态热模型通过模拟导出的封装代表区域的温度和时间的关系曲线图。
图5示出利用所述瞬态热模型通过模拟获得的示范实施例的半导体封装的应力和翘曲的图表,与用传统工艺制造的同样封装进行比较。
图6示出利用所述瞬态热模型通过模拟获得的示范实施例的表面翘曲与距芯片中心距离的关系曲线图,与用传统方法制造的同样封装的翘曲进行比较。
图7A示出传统封装的中心线CL右半部的示意的截面图。
图7B是图7A的方框B中部分图7A的半导体封装的放大视图。
具体实施方式
本发明的将第一和第二CTE失配部分互相接合的改进方法,通过在示范实施例中降低这些部分在高温接合后冷却时所产生的伸长失配,并通过焊接而解决了上述问题。和上述参阅图7A和7B所述的传统方法不同(在传统方法中在焊接时将各部分一起加热到高于焊料的熔化温度并一起冷却),本发明基于以下原理,即,当两个粘附体在高温粘结时,如果它们在粘结剂/焊料固化时具有相同的伸长,两个粘附体的收缩量就相等,于是就不会引入应力。对于CTE匹配的粘附体,粘附体伸长相等这个条件在任何温度下都成立。对于CTE失配的粘附体,要使这个条件成立,粘附体必需处于不同的温度。本发明的方法利用这个原理的方法是:在高温下将每个CTE失配的部分沿待粘结的表面的方向热膨胀基本上相同的数量,然后将热膨胀的部分互相接合。
在图1-3E所示的示范实施例中,这两个部分是半导体芯片7和衬底8,二者通过焊接互相接合以形成半导体封装9。芯片和衬底在被放到一起进行焊接的那一刻处于不同的均匀温度下。然后让它们一起冷却到室温。这样计算芯片和衬底的温度,使得它们在焊料固化温度下的热膨胀或伸长基本上相同。
参阅图1对本发明的技术基础加以说明,图1中芯片7通过多个焊接接点10接合到衬底8上。芯片的CTEαdie和衬底的CTE αsub不同,例如在示范实施例中,二者CTE之间的差大于2.7ppm/℃。更具体地说,在示范实施例中,假定αdie为2.6ppm/℃,αsub为16ppm/℃。当芯片接合到衬底上时(此时熔化的焊料在芯片上,Tdie=Tmelting焊料的熔点),芯片和衬底的温度分别用Tdie和Tsub来表示。图1中参数L是芯片的一半长度(或更精确一些,是从芯片中心到最外部凸起或焊接接点10的距离)。在焊料固化温度(或者,如果是低共熔焊料,则是焊料熔化温度),芯片的伸长Δldie和衬底的伸长Δlsub(在最外部的焊接接点10区)可用下式表示:
(1)Δldie=αdie(Tdie-Troom)L
(2)Δlsub=αsub(Tsub-Troom)L
如果Δldie和Δlsub相等,则当焊接的组件冷却到室温时,芯片和衬底收缩的量等于它们膨胀的量(几乎),从粘结方法上不会有CTE失配所引发的影响(理想情况)。
为实现所述理想情况,
(3)Δldie=Δlsub=αdie(Tdie-Troom)L=αsub(Tsub-Troom)L,亦即:
考虑到实例情况中封装9是用熔点为221℃的低共熔AgSn焊料焊接,其中在接合之前焊料是在芯片侧,铜凸起或支座11是在衬底侧,焊接时芯片温度Tdie需至少为221℃。假定在本发明的接合方法中将Tdie选择为240℃,则衬底温度Tsub需为57.4℃,芯片和衬底在要用焊接接点10接合的表面方向上才会有基本等量的热膨胀。
本发明示范实施例的方法示于图2,其中,如图2左侧示意图所示,芯片7和衬底8用各自的热源11和12分别加热。具体地说,在连接处有低共熔AgSn的芯片由热源11加热到240℃,而衬底8由热源12加热到57.4℃,这样它们各自的热膨胀量基本相等。这些温度是焊接温度和热膨胀系数比αsub/αdie的函数,在所述实例中,所述比率为6.15。芯片和衬底均匀加热到各自的温度后,将它们对准,把芯片置于衬底上,如图2中间的示意图所示。装配后在芯片和衬底中间形成焊接接点10,因为芯片上的熔化焊料湿润了衬底上铜凸起的表面,然后固化。然后将接合的装配件冷却到室温,如图2右侧示意图所示。
图3A-3E示出在示范实施例中瞬态热模型的温度分布。在本发明方法中时间为零时,芯片和其上的AgSn焊料为240℃,而衬底和衬底支座或其上的凸起为57.4℃。在所述实例中,装配过程(在开始冷却之前芯片在衬底上的时间)假定进行了10秒钟。在此期间,通过衬底凸起发生热传导,凸起附近的衬底局部区域被加热(改变理想条件)。在开始冷却之前芯片在衬底上停留的时间越长(大致上可解释为撤销对芯片的加热前的一段时间),情况就越偏离最佳状态。装配过程之后,芯片和封装在空气中冷却到室温。图3A-3E示出在装配步骤和冷却步骤中在不同时间封装中温度分布,即:图3A-3C为芯片放到衬底上后1秒钟,图3D-3E为冷却10分钟。
图4以曲线图的形式示出冷却时封装9的代表区域中的温度分布。当焊料温度冷却到221℃(熔化/固相温度)以下时,芯片和衬底间的相对移动被制止,它们形成了一个装配件。应当指出,在所述偏离理想情况的实例中,在冷却步骤的每个时刻,芯片和衬底的温度并不是使它们的Δ1相等的温度。这就是说,在冷却时在焊接接点中会积聚起一些残余塑性变形,偏离了最佳情况。有可能推导出一个冷却方案来减小对最佳情况的偏离。在任何情况下,对于示范实施例,应强调,比起如果用传统过程粘结芯片和衬底在同样情况下的应力和翘曲,本发明半导体封装所关联的应力和翘曲在冷却到室温后显著减小。这一点从图5可见。
图5对用上述本发明的装配方法装配的示范实施例中,以及用传统回熔工艺过程接合的同样元件的装配件中,关键区域中的应力和芯片表面的翘曲进行了比较。结果表明,本发明的封装有显著的改进,应力和翘曲以及凸起上的法向力都减少到用传统方法制造的封装中的一半以下,在传统方法中对焊接接点作焊接后衬底和芯片一起从焊料固化温度冷却到室温。通过减少装配过程所用的时间(芯片放到衬底上后被加热的时间),按照本发明的方法制造的半导体封装的应力和翘曲幅度还可进一步减小。所述时间对应于芯片放到衬底上后热夹具(图2中的11)与芯片的接触时间,以及芯片和其上的焊料加热到的焊料熔点以上的温度。
图6对示范实施例的封装中芯片表面翘曲随沿着芯片从芯片中心到焊接接点的距离的变化,与用传统工艺制造的同样的封装的翘曲进行了比较。可以看出,比起用传统回熔芯片接合工艺制备的半导体封装,本发明封装的翘曲较小。在每种情况下,均可见翘曲随距芯片中心距离的增加而增加。这就证明了一个事实,即通过本发明的方法,大芯片(例如宽度为200mm的芯片,其中焊接接点距芯片中心有相当大的距离)在用本发明的方法制造时所发生的翘曲可显著减小。
以上即是对示范实施例的说明。虽然已参阅其说明性的实施例对本发明作了说明,但是,显然,本专业的技术人员可以在本发明原理的精神和范围内设计许多其它的变更和实施例。例如,在示范实施例中,芯片和衬底在焊接前的热膨胀是相同的,但如果膨胀不是丝毫不差,但至少基本上相同,例如,相差±25%或相差不大于2ppm/℃,也可获得显著有利的结果。具体地说,在上述公开的内容、附图和所附权利要求书的范围内可对零部件和/或其组合的结构作合理的变动和更改,而不背离本发明的精神。除了零部件和/或结构的变动和更改外,对于业界的技术人员来说,其它不同的应用也是显而易见的。
Claims (29)
1.一种将热膨胀系数失配的半导体芯片和衬底相互焊接的方法,所述方法包括:
使所述半导体芯片和所述衬底在沿其待焊接的表面的方向上基本上等量地热膨胀;以及
将所述热膨胀后的半导体芯片和衬底相互焊接在一起。
2.如权利要求1所述的方法,其特征在于:所述热膨胀包括将所述半导体芯片至少加热到用于焊接所述芯片和衬底的焊接温度。
3.如权利要求1所述的方法,其特征在于:所述热膨胀包括将所述芯片和衬底分别加热到随它们的热膨胀系数失配程度而变化的不同温度,然后以相互接触的形式装配所述芯片和衬底以便进行焊接。
4.如权利要求1所述的方法,其特征在于:所述焊接包括以通过焊料彼此接触的形式装配所述热膨胀后的半导体芯片和衬底以便形成焊接组件,以及所述方法还包括将所述焊接的组件冷却到室温。
5.如权利要求1所述的方法,其特征在于还包括在使所述芯片热膨胀之前把焊料加到所述半导体芯片上,以及所述焊接包括使所述热膨胀后的芯片上的所述焊料与所述衬底相接触,以便浸湿所述衬底因而形成至少一个焊接接点。
6.如权利要求1所述的方法,其特征在于:所述衬底包括凸起在所述衬底表面上的多个支座元件,以及所述焊接包括形成多个焊接接点,这些焊接接点将所述热膨胀后的半导体芯片连接到所述热膨胀后的衬底上各个所述支座元件的上部。
7.如权利要求6所述的方法,其特征在于:所述支座元件在所述焊接温度下不熔化。
8.如权利要求1所述的方法,其特征在于:所述焊接包括在所述半导体芯片和所述衬底之间同时形成多个焊接接点。
9.如权利要求1所述的方法,其特征在于:所述焊接包括在距所述芯片中心至少4mm的距离上沿所述芯片在所述芯片和所述衬底之间形成多个焊接接点。
10.一种将热膨胀系数失配的第一和第二部分彼此接合的方法,所述方法包括:
使所述第一和第二部分的每一部分在沿其待接合的表面的方向上基本上等量地热膨胀;
在高温下将所述热膨胀的第一和第二部分相互接合在一起;以及
将所述接合的第一和第二部分冷却到室温。
11.如权利要求10所述的方法,其特征在于:所述热膨胀过程包括将所述第一和第二部分中热膨胀系数较低的部分至少加热到进行所述接合的所述高温。
12.如权利要求10所述的方法,其特征在于:所述热膨胀过程包括将所述第一和第二部分中的每一个分别加热到随它们的热膨胀系数失配程度而变化的各自的温度,然后以相互接触的形式装配所述各部分以便接合。
13.如权利要求10所述的方法,其特征在于:所述在高温下的接合是通过焊接的接合。
14.一种电子组件,包括:
具有第一热膨胀系数的衬底;
具有不同于所述第一热膨胀系数的第二热膨胀系数的半导体芯片;
连接所述半导体芯片和所述衬底的多个焊接接点;
其中,由于焊接,在所述电子组件的所述多个焊接接点两端的所述芯片和衬底在室温下具有由热膨胀系数差引起的伸长失配和由此在所述电子组件中引起的应力;以及
其中,所述伸长失配的幅度和由此在所述电子组件中引起的应力小于根据在所述多个焊接接点焊接之后将所述衬底和半导体芯片从所述焊料的固化温度冷却到室温所预期值的一半。
15.如权利要求14所述的电子组件,其特征在于:所述伸长失配和由此在所述电子组件中引起的应力在所述电子组件中通过以下效应中的至少一种反映出来:焊接后的残余应力;所述多个焊接接点中的残余塑性变形;所述衬底中的残余塑性变形;以及半导体芯片的翘曲。
16.如权利要求14所述的电子组件,其特征在于:所述衬底的第一热膨胀系数比所述半导体芯片的所述第二热膨胀系数大两倍以上。
17.如权利要求14所述的电子组件,其特征在于:通过沿所述芯片、距所述芯片中心至少4mm距离的所述各焊接接点将所述半导体芯片接合到所述衬底上。
18.如权利要求14所述的电子组件,其特征在于:所述多个焊接接点各自包括所述半导体芯片上的焊料,所述焊料浸湿到所述衬底表面上,形成所述焊接接点。
19.一种电子组件,包括:
具有第一热膨胀系数的衬底;
具有不同于所述第一热膨胀系数的第二热膨胀系数的半导体芯片;
连接所述半导体芯片和所述衬底的多个焊接接点;
其中,由于焊接,在所述电子组件的所述多个焊接接点两端的所述芯片和衬底在室温下具有由热膨胀系数差引起的伸长失配;
其中,所述伸长失配的幅度小于根据在所述多个焊接接点焊接之后将所述衬底和半导体芯片从所述焊料的固化温度冷却到室温所预期幅度的一半;以及
其中,所述衬底包括凸起在所述衬底表面上的多个支座元件,以及所述多个焊接接点将所述半导体芯片连接到所述多个支座元件中相应的支座元件的上部。
20.如权利要求19所述的电子组件,其特征在于:所述支座元件在所述焊料液化温度下不熔化。
21.如权利要求19所述的电子组件,其特征在于:所述多个支座元件是铜凸起。
22.一种半导体封装,包括:
具有至少15ppm/℃的第一热膨胀系数的封装衬底,所述封装衬底具有多个接触部分;
半导体芯片,具有小于所述封装衬底的所述热膨胀系数的至少2.7ppm/℃的第二热膨胀系数,所述多个芯片的正面具有多个焊接接头,所述半导体芯片位于所述衬底上,所述多个焊接接头通过将所述半导体芯片电连接到所述封装衬底上的所述焊接接点连接到所述多个接触部分中相应的接触部分上;
其中,由于焊接,在所述半导体封装的所述各个焊接接点两端的所述半导体芯片和封装衬底在室温下具有由热膨胀系数差引起的伸长失配和由此在所述半导体封装中引起的应力;
其中,所述伸长失配的幅度和由此在所述半导体封装中引起的应力小于根据在所述焊接接点焊接之后将所述衬底和半导体芯片从所述焊料的固化温度冷却到室温所预期值的一半。
23.如权利要求22所述的半导体封装,其特征在于:所述伸长失配和由此在所述半导体封装中引起的应力在所述半导体封装中通过以下效应中的至少一种反映出来:焊接后的残余应力;所述焊接接点中的残余塑性变形;所述衬底中的残余塑性变形;以及半导体芯片的翘曲。
24.如权利要求22所述的半导体封装,其特征在于:所述衬底的第一热膨胀系数比所述半导体芯片的所述第二热膨胀系数大两倍以上。
25.如权利要求22所述的半导体封装,其特征在于:通过沿所述芯片、距所述芯片中心至少4mm距离的所述各焊接接点将所述半导体芯片接合到所述衬底上。
26.如权利要求22所述的半导体封装,其特征在于:所述焊接接点各自包括所述半导体芯片上的焊料,所述焊料浸湿到所述衬底的接触部分的表面上,形成所述焊接接点。
27.一种半导体封装,包括:
具有至少15ppm/℃的第一热膨胀系数的封装衬底,所述封装衬底具有多个接触部分;
半导体芯片,具有小于所述封装衬底的所述热膨胀系数的至少2.7ppm/℃的第二热膨胀系数,所述多个芯片的正面具有多个焊接接头,所述半导体芯片位于所述衬底上,所述多个焊接接头通过将所述半导体芯片电连接到所述封装衬底上的所述焊接接点连接到所述多个接触部分中相应的接触部分上;
其中,由于焊接,在所述半导体封装的所述各个焊接接点两端的所述半导体芯片和封装衬底在室温下具有由热膨胀系数差引起的伸长失配;
其中,所述伸长失配的幅度小于根据在所述焊接接点焊接之后将所述衬底和半导体芯片从所述焊料的固化温度冷却到室温所预期幅度的一半;以及
其中,所述多个接触部分包括凸起在所述衬底表面上的多个支座元件,以及所述焊接接点将所述半导体芯片连接到所述多个支座元件中相应的支座元件的上部。
28.如权利要求27所述的半导体封装,其特征在于:所述多个支座元件在所述焊料液化温度下不熔化。
29.如权利要求27所述的半导体封装,其特征在于:所述多个支座元件是铜凸起。
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US10/023,819 US7235886B1 (en) | 2001-12-21 | 2001-12-21 | Chip-join process to reduce elongation mismatch between the adherents and semiconductor package made thereby |
US10/023,819 | 2001-12-21 |
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CN1620843A CN1620843A (zh) | 2005-05-25 |
CN100431396C true CN100431396C (zh) | 2008-11-05 |
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US (1) | US7235886B1 (zh) |
EP (1) | EP1457100A2 (zh) |
CN (1) | CN100431396C (zh) |
AU (1) | AU2002340452A1 (zh) |
WO (1) | WO2003059028A2 (zh) |
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Also Published As
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CN1620843A (zh) | 2005-05-25 |
WO2003059028A3 (en) | 2004-02-26 |
AU2002340452A8 (en) | 2003-07-24 |
AU2002340452A1 (en) | 2003-07-24 |
WO2003059028A2 (en) | 2003-07-17 |
EP1457100A2 (en) | 2004-09-15 |
US7235886B1 (en) | 2007-06-26 |
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