CN100397641C - 电路装置及其制造方法 - Google Patents

电路装置及其制造方法 Download PDF

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Publication number
CN100397641C
CN100397641C CNB2003101202943A CN200310120294A CN100397641C CN 100397641 C CN100397641 C CN 100397641C CN B2003101202943 A CNB2003101202943 A CN B2003101202943A CN 200310120294 A CN200310120294 A CN 200310120294A CN 100397641 C CN100397641 C CN 100397641C
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China
Prior art keywords
conductive pattern
circuit element
circuit arrangement
separating tank
conductive
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CNB2003101202943A
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CN1510750A (zh
Inventor
五十岚优助
高草木宣久
坂野纯
坂本则明
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H05K1/0265—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

一种电路装置及其制造方法，进行内装厚度不同的多种电路装置(12)的电路装置(10)的薄型化。将安装比较薄型电路元件(12A)的第一导电图案较厚地形成，将安装比较厚的第二电路元件(12B)的第二导电图案(11B)较薄地形成。另外，也可使用较薄地形成的第二导电图案(12B)构成微细的配线部。由此，即使内装厚的电路元件的情况下，也可以通过在较薄地形成的第二导电图案(11B)上固定该元件，使总厚度变薄。从而，可实施电路装置(10)整体的薄型化。

Description

电路装置及其制造方法
技术领域
本发明涉及电路装置及其制造方法，特别是涉及通过较厚地形成安装比较薄的元件的导电图案，并较薄地形成安装具有厚度的电路元件的导电图案可将装置整体减薄的电路装置及其制造方法。
背景技术
近年来，由于设置在电子设备中的电路装置被使用在手机、笔记本电脑等中，因而谋求小型化、薄型化及轻量化。
例如，作为电路装置以半导体装置为例说明时，作为一般的半导体装置，最近开发了被称为CSP(芯片尺寸模块)的和芯片尺寸相同的晶片级CSP或比芯片尺寸大若干尺寸的CPS。
图13显示作为支承衬底采用玻璃环氧树脂衬底5的，比芯片尺寸大若干的CSP66。在此说明在玻璃环氧树脂衬底65上安装有晶体管芯片T的情况。
在该玻璃环氧树脂衬底65表面形成第一电极67、第二电极68及垫板69，在背面形成第一背面电极70和第二背面电极71。所述第一电极67和第一背面电极70、第二电极68和第二背面电极71介由通孔TH电连接。另外，在垫板69上固定所述裸的晶体管芯片T，并介由金属细线72将晶体管发射极和第一电极67连接，介由金属细线72将晶体管基极和第二电极68连接。另外，在玻璃环氧树脂衬底65上设置树脂层73，以覆盖晶体管芯片T。
所述CSP66采用玻璃环氧树脂衬底65，但和晶片级CSP不同，自芯片T至外部连接用背面电极70、71的延伸结构简单，具有可廉价制造的优点。
但是，上述的CSP66中，将玻璃环氧树脂衬底65作为附加衬底使用，因此，CSP66的小型化及薄型化有限。由此，开发了图14所示不需要安装衬底的电路装置80(例如，参照专利文献1)。
参照图14，电路装置80包括：导电图案81；电路元件82，其固定在导电图案81上；金属细线84，其电连接电路元件82和导电图案81；绝缘性树脂83，露出导电图案81的背面，覆盖电路元件82、电路元件82及导电图案81。从而，电路装置80形成不需要安装衬底的结构，当和CSP66比较时，薄型且小型地形成。
专利文献1
特开2002-076246号公报(第7页、图1)
发明内容
但是，在所述的电路装置80中，导电图案81的厚度被相同地形成。从而，在将厚度不同的多种电路元件82固定在导电图案81上时，绝缘性树脂83也形成得很厚，以覆盖具有厚度的电路元件82。因此，电路装置80整体很厚地形成，电路装置的轻量化、小型化有限。
另外，当为了装置的薄型化减薄导电图案81时，在电路元件82为工作时伴随发热的元件时，具有瞬态热阻增大的问题。
本发明是鉴于所述的问题而开发的，本发明的主要目的在于，提供即使在内装比较厚的电路元件时也可以抑制电路装置整体厚度的增加的电路装置及其制造方法。
本发明的电路装置包括：第一导电图案，其较厚地形成，由第一分离槽分离；第二导电图案，其比所述第一导电图案更薄地形成，且由第二分离槽分离；固定在所述第一导电图案上的第一电路元件及固定在所述第二导电图案上的第二电路元件；绝缘性树脂，露出所述两导电图案的背面，覆盖所述电路元件及所述导电图案，并被填充在所述两分离槽中。
本发明的电路装置包括：第一导电图案，其较厚地形成，由第一分离槽分离；第二导电图案，其比所述第一导电图案更薄地形成，且由第二分离槽分离，构成微细配线；电路元件，其固定在所述第一导电图案上；绝缘性树脂，露出所述两导电图案的背面，覆盖所述电路元件及所述导电图案，并被填充在所述两分离槽中。
本发明的电路装置的制造方法包括如下工序：准备导电箔，在所述导电箔表面涂敷第一抗蚀剂的工序；在形成第一导电图案的区域保留所述第一抗蚀剂进行蚀刻，形成分离所述第一导电图案的第一分离槽，并将形成第二导电图案的区域的所述导电箔同样地刻蚀的工序；至少将形成所述第一导电图案的上面及所述第二导电图案的区域的所述导电箔表面由第二抗蚀剂覆盖来进行蚀刻，更深地形成所述第一分离槽，并形成将比所述第一导电图案薄的所述第二导电图案分离的第二分离槽的工序；将电路元件固定在所述第一导电图案及所述第二导电图案两方或任意一方上的工序；形成绝缘性树脂，以覆盖所述电路元件，并填充所述两分离槽中的工序；除去所述导电箔背面，直至露出填充在所述两分离槽中的绝缘性树脂的工序。
比第一导电图案更薄地形成第二导电图案，通过在第二导电图案上固定厚的电路元件，可较薄地形成装置整体。另外，通过在较厚地形成的第一导电图案上固定工作时伴随发热的元件，可减小瞬态热阻。
附图说明
图1是说明本发明电路装置的剖面图(A)、平面图(B)；
图2是说明本发明电路装置的剖面图；
图3是说明本发明电路装置的制造方法的剖面图；
图4是说明本发明电路装置的制造方法的剖面图；
图5是说明本发明电路装置的制造方法的剖面图；
图6是说明本发明电路装置的制造方法的剖面图；
图7是说明本发明电路装置的制造方法的剖面图(A)、剖面图(B)；
图8是说明本发明电路装置的制造方法的剖面图(A)、剖面图(B)；
图9是说明本发明电路装置的制造方法的剖面图(A)、剖面图(B)；
图10是说明本发明电路装置的制造方法的剖面图(A)、剖面图(B)；
图11是说明本发明电路装置的制造方法的剖面图(A)、剖面图(B)；
图12是说明本发明电路装置的制造方法的剖面图(A)、剖面图(B)；
图13是说明现有电路装置的剖面图；
图14是说明现有电路装置的剖面图。
具体实施方式
说明电路装置结构的第一实施例
参照图1，电路装置10A包括：第一导电图案11A，其较厚地形成，由第一分离槽16A分离；第二导电图案11B，其比所述第一导电图案11A更薄地形成，且由第二分离槽16B分离；固定在第一导电图案11A上的第一电路元件12A及固定在第二导电图案11B上的第二电路元件12B；绝缘性树脂13，露出两导电图案11的背面，覆盖电路元件12及导电图案11，并填充两分离槽16中。以下祥述这样的结构。图1(A)是电路装置10A的剖面图，图1(B)是其平面图。
第一导电图案11A考虑焊剂的黏附性、接合性及镀敷性选择其材料，材料采用以Cu为主材料的导电箔、以Al为主材料的导电箔或Fe-Ni等合金构成的导电箔等。在此，第一导电图案11A形成露出背面并埋入绝缘性树脂13中的结构，通过第一分离槽16A电分离。第一导电图案11A的厚度形成得比第二导电图案11B厚，例如形成在140um以上。另外，在由绝缘性树脂13露出的第一导电图案11A的背面设置由焊锡等焊剂构成的外部电极15。
另外，第一导电图案11A利用第一分离槽16A电分离。而后，在第一分离槽16A的侧部至少设置一个蜂腰部17，因此，第一导电图案11A和绝缘性树脂13的粘附变得很牢固。在此，第一导电图案11A形成上面安装第一电路元件的岛及介由金属细线14和第一电路元件12A电连接的焊盘。另外，装置背面未设置外部电极15的位置由抗蚀剂16覆盖。
第二导电图案11B由和所述的第一导电图案11A相同的材料构成，并形成得比第一导电图案11A更薄。另外，由于第一导电图案11A的背面和第二导电图案11B的背面在同一平面上，因此，第一导电图案11A的表面形成比第二导电图案11B的表面更高。在此，在第二导电图案11B上面固定具有厚度的第二电路元件12B，另外，也可以构成微细的配线部。另外，第二导电图案11B的具体厚度为例如50um左右。另外，第一导电图案11A和第二导电图案11B也可以介由配线部电连接。
第一电路元件12A在此采用半导体元件，由面朝上结合法固定在由第一导电图案11A构成的岛上。第一电路元件12A的电极和由第一导电图案11A构成的焊盘介由金属细线14电连接。如上所述，由于第一导电图案11A较厚地形成，因此，即使第一导电图案12A是工作时伴随发热的元件(例如功率类的半导体元件)，第一导电图案11A也可作为散热部件起作用，降低瞬态热阻。另外，具体地说，作为第一电路元件12A可采用大电流半导体元件。大电流半导体元件在工作中有大量的热产生。从而，为了促进作为这样的大电流半导体元件的第一电路元件12A的散热，优选厚的第一导电图案。
第二电路元件12B在此采用片状电阻或片状电容等具有厚度的片状部件，介由焊锡等导电性粘接剂固定在第二导电图案11B上。特别是在作为所述的第一电路元件12A采用大电流半导体元件时，在其近旁必须形成作为噪声对策的大容量电容，大容量电容一般形成得较高。从而，通过将这种高的大容量电容固定在比第一导电图案11A更薄的第二导电图案上，可将电路装置10A的整体厚度变薄。
露出第一导电图案11A及第二导电图案11B的背面，由绝缘性树脂13覆盖电路元件12、金属细线14及导电图案11。绝缘性树脂13可全部采用热硬性树脂或热塑性树脂。另外，在分离各导电图案11的分离槽16中填充绝缘性树脂13。本发明的电路装置10A整体由绝缘性树脂13支承。
如上所述，说明具有不同厚度的第一导电图案11A及第二导电图案11B的优点。在比较厚地形成的第一导电图案11B上固定薄的第一电路元件12A，在比第一导电图案11A更薄地形成的第二导电图案11B上安装厚的电路元件12B。由此，即使不同厚度的多种电路元件12被内装在电路装置10A上，也可以通过在较薄地形成的第二导电图案11B上安装厚的电路元件12B控制整体厚度。并且可调节两导电图案的高度差，使将第一导电图案11A的高度和第一电路元件12A的高度相加所得的高度与将第二导电图案11B的高度和第二电路元件12B的高度相加所得的高度形成相同程度。由此，可将覆盖这些的绝缘性树脂13的厚度变为最小，因此，可将装置整体厚度变薄。
第一分离槽16A通过多次蚀刻，在第一导电图案11A之间形成，中间部形成蜂腰部17。蜂腰部17的横向宽度比第一分离槽16A的其它位置更窄地形成。从而，通过在蜂腰部17粘附绝缘性树脂13，由于蜂腰部17的侧面与第一导电图案11A的侧面对应，因此，可提高第一导电图案11A和绝缘性树脂13的粘附强度。如上所述，第一分离槽16A通过多次蚀刻作为导电图案11的材料的导电箔的同一位置而形成。从而，第一分离槽16A的深度形成比其宽度更深。另外，蜂腰部17贯穿第一分离槽11A的整个侧面部连续地形成。
在此，利用两次蚀刻形成第一分离槽16A，故第一分离槽16A的深度以其宽度的两倍程度形成。另外，在通过多次蚀刻形成第一分离槽16A时，相对于其宽度可更深地形成其深度。另外，由于第一导电图案11A的厚度与第一分离槽16A的深度对应，因此，在本发明中可形成比第一分离槽11A的宽度更厚地形成的第一导电图案11A。
参照图2说明其它形态的电路装置10B的结构。电路装置10B包括：第一导电图案11A，其被较厚地形成，并由第一分离槽16A分离；第二导电图案11B，其形成得比第一导电图案11A更薄，且由第二分离槽16B分离，构成微细的配线；电路元件12，其固定在第一导电图案11A上；绝缘性树脂13，露出两导电图案11A的背面，覆盖电路元件12及导电图案11，并填充两分离槽16。
具有这样结构的电路装置10B和参照图1说明的电路装置10A的不同点在于，第二导电图案11B构成微细的配线。具体地说，由于第二导电图案11B的厚度可以以50um程度较薄地形成，故可通过蚀刻实现微细的配线结构。由此，为作为工作时伴随发热的电路元件12的散热部件起作用而较厚地形成的第一导电图案和形成微细配线的第二导电图案11B可在同一电路装置10B内部形成。另外，也可以和第一导电图案11B导通而形成第二导电图案11B。作为电路元件12可采用和图1中的第一电路元件12A相同的元件。
说明电路装置制造方法的第二实施例
参照图3～图11说明电路装置10的制造方法。在本发明电路装置的制造方法包括：准备导电箔40，在导电箔40表面涂敷第一抗蚀剂PR1的工序；在形成第一导电图案11A的区域保留第一抗蚀剂PR1，通过进行蚀刻形成分离第一导电图案11A的第一分离槽16A，并将形成第二导电图案的区域的导电箔40相同地刻槽的工序；至少将第一导电图案11A的上面及形成第二导电图案11B的区域的导电箔40的表面由第二抗蚀剂PR2覆盖，通过进行蚀刻，较深地形成第一分离槽11A，并形成分离第二导电图案11B的第二分离槽16B的工序；将电路元件固定在第一导电图案11A及第二导电图案11B两方或任意一方的工序；形成绝缘性树脂13，以覆盖电路元件12，并填充所述两分离槽16的工序；除去导电箔40的背面，直至露出在两分离槽16中填充的绝缘性树脂13的工序。以下详述上述各工序。
本发明的第一工序在于，如图3～图5所示，准备导电箔40，在导电箔40表面涂敷第一抗蚀剂PR1，并在形成第一导电图案11A的区域保留第一抗蚀剂PR1，通过进行蚀刻形成分离第一导电图案11A的第一分离槽16A，并将形成第二导电图案的区域的导电箔40同样地蚀刻。
在本工序中，首先如图3，准备片状导电箔40。该导电箔40考虑焊剂的黏附性、接合性及镀敷性选择其材料，材料采用以Cu为主材料的导电箔、以A1为主材料的导电箔或Fe-Ni等合金构成的导电箔等。导电箔的厚度考虑以后的蚀刻，最好为10um～300um左右。
然后，参照图4，在导电箔40表面形成作为耐蚀刻掩膜的第一抗蚀剂PR1，并对第一抗蚀剂PR1制图，以使除去形成第一导电图案11A的区域外的导电箔40露出。另外，较薄地形成构成第二导电图案11B的区域，该区域的导电箔40表面也露出。
另外，参照图5，通过进行蚀刻形成第一分离槽16A。利用蚀刻形成的分离槽16A的深度为例如50um，由于其侧面形成粗糙面，故提高了和绝缘性树脂13的粘接性。在此使用的蚀刻剂主要采用氯化铁或氯化铜，所述导电箔被浸渍在该抗蚀剂中，或由该蚀刻剂喷射。在此，由于湿蚀法一般为非各向异性蚀刻，故侧面形成弯曲结构。另外，形成第二导电图案11B的区域的导电箔40也和第一分离槽16A的深度相同程度地被蚀刻，其表面基本平坦。
本发明的第二工序在于，参照图6～图8，至少将形成第一导电图案11A的上面及第二导电图案11B的区域的所述导电箔40表面由第二抗蚀剂PR2覆盖，通过进行蚀刻较深地形成所述第一分离槽11A，并形成分离第二导电图案11B的第二分离槽16B。
首先，参照图6，将第一抗蚀剂PR1剥离并除去后，在包含第一分离槽16A表面的导电箔40表面形成第二抗蚀剂PR2。
其次，参照图7(A)，通过进行第二抗蚀剂PR2的曝光及显影，使第一分离槽16A底部及形成分离第二导电图案11B的第二分离槽16B的区域的导电箔40表面露出。关于第一分离槽16A，在其侧边的一部分也粘附第二抗蚀剂PR2。
其次，参照图7(B)，通过蚀刻自第二抗蚀剂PR2露出的导电箔40使第一分离槽16A更深，并形成第二分离槽16B。以各向同性由自第二抗蚀剂PR2露出的第一分离槽16A的底面进行蚀刻，第一分离槽16A被更深地形成，在其深度方向中间部附近形成蜂腰部17。这样，利用多次蚀刻形成第一分离槽16A可形成比其它位置宽度更窄的蜂腰部17。可以和利用一次蚀刻形成的分离槽相同的宽度形成深的分离槽。从而，可不将第一分离槽16A的宽度加宽而较厚地形成第一导电图案11A。
参照图8说明在本工序由第二导电图案11B形成微细的配线部的方法。
首先，参照图8(A)，将第一分离槽16A的底部及予定形成的第二导电图案11B由第二抗蚀剂PR2覆盖。在此，为使第二导电图案11B可构成微细的配线部，第二抗蚀剂PR2也微细地形成。
其次，参照图8(B)，通过进行蚀刻将第一分离槽16A变得更深，且形成第二分离槽16B。由于在上述的第一工序形成第二导电图案11B的区域的导电箔40被较薄地形成，因此，利用第二导电图案11B可构成微细的配线部。在此，第二导电图案相互之间的间隔可形成例如50um左右。
本发明的第三工序在于，如图9所示，将电路元件12固定在第一导电图案11A及第二导电图案11B两方或任何一方。
参照图9(A)，在此，在第一导电图案11A及第二导电图案11B两方上安装电路元件12。最好在较厚地形成的第一导电图案11A上安装薄的电路元件12A，在比第一导电图案11A更薄地形成的第二导电图案上安装厚的第二电路元件12B。在此，在由第一导电图案11A构成的岛上面朝上固定作为半导体元件的第一电路元件12A。第一电路元件12A上面的电极和作为焊盘的第一导电图案11A介由金属细线14电连接。在此，第二电路元件12B为片状电阻或片状电容等片状部件，介由焊锡等焊剂固定在第二导电图案11B上。在此，第一电路元件12A可采用例如大电流半导体元件。另外，第二电路元件12B可采用例如片状电容。
参照图9(B)，在此，由于第二导电图案11B形成微细的配线部，因此，仅在第一导电图案11A上安装电路元件12。安装的电路元件12的种类可采用和上述的第一电路元件12A相同的元件。
本发明的第四工序在于，如图10所示，形成绝缘性树脂13，以覆盖电路元件12，并填充所述两分离槽16。
参照图10(A)，绝缘性树脂13将电路元件12及多个导电图案11覆盖，并在导电图案11之间的分离槽16中填充绝缘性树脂13，和导电图案11侧面的弯曲部结构嵌合，而牢固地结合。由绝缘性树脂13支承导电图案11。
另外，由于在第一分离槽16中形成狭窄地形成的蜂腰部17，故通过在蜂腰部17粘附绝缘性树脂13使绝缘性树脂13和导电图案11的粘附牢固。另外，本工序可通过传递模制、注入模制或浸渍实现。作为树脂材料，环氧树脂等热硬性树脂可通过传递模制实现，聚酰亚胺树脂、硫化聚苯树脂等热塑性树脂可通过注入模制实现。
本工序的优点是，在覆盖绝缘性树脂13之前，形成导电图案11的导电箔40作为支承衬底。在现有例中采用本来没有必要的支承衬底形成导电路，但在本发明中，作为支承衬底的导电箔40作为电极材料是必须的材料。因此，具有可极其节省构成材料来作业的优点，并可实现成本的降低。
另外，厚的第二电路元件12A被固定在较薄地形成的第二导电图案11B上。由此，第二电路元件12B的最上部和第一电路元件12A的最上部形成同程度的高度。从而，即使在内装厚的电路元件12A的情况下也可抑制覆盖它的绝缘性树脂13的厚度的过度增加。
参照图10(B)，在此，第二导电图案11B构成微细的配线部，并在分离第二导电图案11B的第二分离槽16B中填充绝缘性树脂13。
本发明的第五工序在于，如图11所示，除去导电箔40的背面，直至在两分离槽16中填充的绝缘性树脂13露出。
参照图11(A)，在此，除去导电箔40背面，直至在第一及第二分离槽16A、B中填充的绝缘性树脂13露出，进行各导电图案11的分离。本工序是化学及/或物理除去导电箔40的背面，分离为导电图案11的工序。该工序利用研磨、研削、蚀刻、激光金属蒸发等实施。由于第一分离槽16A被较深地形成，故第一导电图案11在此也可较厚地形成。具体地说，可较厚地形成在150um程度以上。
参照图11(B)，在此，利用和上述的方法相同的方法电分离构成微细的配线部的第二导电图案11B。由于形成第二导电图案11B的区域的导电箔40被所述的第一工序充分变薄，故可形成微细的配线部。
在本工序结束以后，由抗蚀剂16覆盖导电图案11的背面，并在所需的位置形成外部电极15。另外，将以矩阵状形成的各电路装置10的分界部的绝缘性树脂13切割，分割成个别的电路装置10。经由所述工序制造如图1或图2所示的电路装置10。
参照图12(A)及图12(B)，通过部分地除去导电箔40背面，可进行各导电图案11的分离。在此，通过由抗蚀剂等选择性地覆盖导电箔40背面，进行蚀刻，进行导电箔40背面的局部除去。局部除去的导电箔40的区域与形成分离槽16的区域对应。利用这样局部的除去方法进行各导电图案11的分离，可将导电图案11的厚度变厚。从而，可提高电路装置整体的散热性。
通过本发明的电路装置，在具有厚度的第一导电图案11A上固定薄的第一电路元件12B，并在比第一导电图案11A更薄地形成的第二导电图案11B上安装厚的电路元件12B。由此，可降低导电图案11和在其上面固定的电路元件12相加的整体厚度。从而，可进行电路装置10整体的进一步薄型化。
另外，通过在较厚地形成的第一导电图案11A上安装功率类半导体等工作时伴随发热的元件，可使第一导电图案11A作为吸热部件起作用，降低瞬态热阻。
另外，由于可利用薄的第二导电图案11B构成微细的配线部，因此，可提供具有作为吸热部件起作用的第一导电图案11A和构成配线部的第二导电图案12B的电路装置10B。
根据本发明电路装置的制造方法，通过使用第一抗蚀剂PR2进行导电箔40的蚀刻形成第一分离槽16A，且使予定形成第二导电图案11B的区域的导电箔40同样变薄。而且，通过使用第二抗蚀剂PR2再次蚀刻导电箔40，将第一分离槽16加深，并形成第二分离槽16A。从而，可形成利用第一分离槽16A分离的厚的第一导电图案11A和利用第二分离槽16A分离的薄的第二导电图案16B。

Claims (14)

1.一种电路装置，其特征在于，包括：第一导电图案，其由第一分离槽分离；第二导电图案，其比所述第一导电图案更薄地形成，且由第二分离槽分离；固定在所述第一导电图案上的第一电路元件和固定在所述第二导电图案上的第二电路元件；绝缘性树脂，露出所述两导电图案背面，覆盖所述电路元件及所述导电图案，并被填充在所述两分离槽中。
2.如权利要求1所述的电路装置，其特征在于，所述第一导电图案表面比所述第二导电图案表面更高地形成。
3.如权利要求1所述的电路装置，其特征在于，在分离所述第一导电图案的分离槽侧部至少设有一个蜂腰部。
4.如权利要求1所述的电路装置，其特征在于，所述第二电路元件比所述第一电路元件厚。
5.如权利要求1所述的电路装置，其特征在于，所述第一电路元件的高度和所述第一导电图案的高度相加所得的高度与所述第二电路元件的高度和所述第二导电图案的高度相加所得的高度相同。
6.如权利要求1所述的电路装置，其特征在于，所述第一电路元件是半导体元件。
7.如权利要求1所述的电路装置，其特征在于，所述第二电路元件是片状电容。
8.一种电路装置，其特征在于，包括：第一导电图案，其由第一分离槽分离；第二导电图案，其比所述第一导电图案更薄地形成，且由第二分离槽分离，构成微细配线；电路元件，其固定在所述第一导电图案上；绝缘性树脂，露出所述两导电图案背面，覆盖所述电路元件及所述导电图案，并被填充在所述两分离槽中。
9.如权利要求8所述的电路装置，其特征在于，所述第一导电图案表面比所述第二导电图案表面更高地形成。
10.如权利要求8所述的电路装置，其特征在于，在分离所述第一导电图案的分离槽侧部至少设有一个蜂腰部。
11.如权利要求8所述的电路装置，其特征在于，所述电路元件是半导体元件。
12.一种电路装置的制造方法，其特征在于，包括如下工序：准备导电箔，在所述导电箔表面涂敷第一抗蚀剂的工序；在形成第一导电图案的区域保留所述第一抗蚀剂进行蚀刻，形成分离所述第一导电图案的第一分离槽，并将形成第二导电图案的区域的所述导电箔相同地刻槽的工序；至少将形成所述第一导电图案上面及所述第二导电图案的区域的所述导电箔表面由第二抗蚀剂覆盖来进行蚀刻，更深地形成所述第一分离槽，并形成将比所述第一导电图案薄的所述第二导电图案分离的第二分离槽的工序；将电路元件固定在所述第一导电图案及所述第二导电图案两方或任意一方上的工序；形成绝缘性树脂，覆盖所述电路元件，并填充在所述两分离槽中的工序；除去所述导电箔背面，直至露出填充在所述两分离槽中的绝缘性树脂的工序。
13.如权利要求12所述的电路装置的制造方法，其特征在于，由所述第二抗蚀剂覆盖所述第一分离槽侧面之后进行蚀刻，在所述第一分离槽侧部形成蜂腰部。
14.如权利要求12所述的电路装置的制造方法，其特征在于，通过部分地除去所述导电箔背面，露出所述绝缘性树脂。
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