CN100380520C - 可稳定地进行数据写入的存储装置 - Google Patents

可稳定地进行数据写入的存储装置 Download PDF

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Publication number
CN100380520C
CN100380520C CNB031786626A CN03178662A CN100380520C CN 100380520 C CN100380520 C CN 100380520C CN B031786626 A CNB031786626 A CN B031786626A CN 03178662 A CN03178662 A CN 03178662A CN 100380520 C CN100380520 C CN 100380520C
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China
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mentioned
write
current
voltage
current source
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Expired - Fee Related
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CNB031786626A
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English (en)
Chinese (zh)
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CN1503268A (zh
Inventor
日高秀人
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Renesas Electronics Corp
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Renesas Technology Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Semiconductor Memories (AREA)
  • Hall/Mr Elements (AREA)
CNB031786626A 2002-11-27 2003-07-18 可稳定地进行数据写入的存储装置 Expired - Fee Related CN100380520C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP344445/2002 2002-11-27
JP344445/02 2002-11-27
JP2002344445A JP4266302B2 (ja) 2002-11-27 2002-11-27 不揮発性記憶装置

Publications (2)

Publication Number Publication Date
CN1503268A CN1503268A (zh) 2004-06-09
CN100380520C true CN100380520C (zh) 2008-04-09

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CNB031786626A Expired - Fee Related CN100380520C (zh) 2002-11-27 2003-07-18 可稳定地进行数据写入的存储装置

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US (4) US6898114B2 (enExample)
JP (1) JP4266302B2 (enExample)
CN (1) CN100380520C (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4266302B2 (ja) * 2002-11-27 2009-05-20 株式会社ルネサステクノロジ 不揮発性記憶装置
US20110141802A1 (en) * 2009-12-15 2011-06-16 Grandis, Inc. Method and system for providing a high density memory cell for spin transfer torque random access memory
JP5706635B2 (ja) * 2010-06-24 2015-04-22 ルネサスエレクトロニクス株式会社 半導体装置及びその内部回路の制御方法
JP5214002B2 (ja) * 2011-08-12 2013-06-19 ルネサスエレクトロニクス株式会社 不揮発性記憶装置
US9245926B2 (en) 2012-05-07 2016-01-26 Micron Technology, Inc. Apparatuses and methods including memory access in cross point memory
US8675423B2 (en) 2012-05-07 2014-03-18 Micron Technology, Inc. Apparatuses and methods including supply current in memory
JP2013140667A (ja) * 2013-03-11 2013-07-18 Hitachi Ltd 半導体装置
US9361990B1 (en) * 2014-12-18 2016-06-07 SanDisk Technologies, Inc. Time domain ramp rate control for erase inhibit in flash memory
CN113228179B (zh) 2018-11-30 2022-08-09 合肥睿科微电子有限公司 双精度模拟存储器单元及阵列
US11139025B2 (en) 2020-01-22 2021-10-05 International Business Machines Corporation Multi-level cell threshold voltage operation of one-selector-one-resistor structure included in a crossbar array
US11587635B2 (en) * 2020-09-04 2023-02-21 Micron Technology, Inc. Selective inhibition of memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384730A (en) * 1991-05-31 1995-01-24 Thunderbird Technologies, Inc. Coincident activation of pass transistors in a random access memory
US6212109B1 (en) * 1999-02-13 2001-04-03 Integrated Device Technology, Inc. Dynamic memory array having write data applied to selected bit line sense amplifiers before sensing to write associated selected memory cells
US6314028B1 (en) * 2000-07-07 2001-11-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device capable of stable sensing operation
US6462998B1 (en) * 1999-02-13 2002-10-08 Integrated Device Technology, Inc. Programmable and electrically configurable latch timing circuit

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3705842B2 (ja) * 1994-08-04 2005-10-12 株式会社ルネサステクノロジ 半導体装置
US6462584B1 (en) * 1999-02-13 2002-10-08 Integrated Device Technology, Inc. Generating a tail current for a differential transistor pair using a capacitive device to project a current flowing through a current source device onto a node having a different voltage than the current source device
JP3913952B2 (ja) * 1999-12-28 2007-05-09 株式会社東芝 半導体記憶装置
JP4726290B2 (ja) 2000-10-17 2011-07-20 ルネサスエレクトロニクス株式会社 半導体集積回路
ATE397056T1 (de) * 2001-07-11 2008-06-15 Sfa International Inc Verfahren zur verminderung der rauch- und teilchenemissionen aus flüssige petroleumkraftstoffe brauchenden kompressionsanzündungskolbenkraftmaschinen
JP4570313B2 (ja) * 2001-10-25 2010-10-27 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
JP4208500B2 (ja) * 2002-06-27 2009-01-14 株式会社ルネサステクノロジ 薄膜磁性体記憶装置
US6940777B2 (en) * 2002-10-31 2005-09-06 Renesas Technology Corp. Semiconductor device and semiconductor memory device provided with internal current setting adjustment circuit
JP4365576B2 (ja) * 2002-11-22 2009-11-18 Ｔｄｋ株式会社 磁気メモリデバイスおよび書込電流駆動回路、並びに書込電流駆動方法
JP4266302B2 (ja) * 2002-11-27 2009-05-20 株式会社ルネサステクノロジ 不揮発性記憶装置
JP3857640B2 (ja) * 2002-11-29 2006-12-13 株式会社東芝 半導体記憶装置
JP2004348815A (ja) * 2003-05-20 2004-12-09 Sharp Corp 半導体記憶装置のドライバ回路及び携帯電子機器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384730A (en) * 1991-05-31 1995-01-24 Thunderbird Technologies, Inc. Coincident activation of pass transistors in a random access memory
US6212109B1 (en) * 1999-02-13 2001-04-03 Integrated Device Technology, Inc. Dynamic memory array having write data applied to selected bit line sense amplifiers before sensing to write associated selected memory cells
US6462998B1 (en) * 1999-02-13 2002-10-08 Integrated Device Technology, Inc. Programmable and electrically configurable latch timing circuit
US6314028B1 (en) * 2000-07-07 2001-11-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device capable of stable sensing operation

Also Published As

Publication number Publication date
US7292472B2 (en) 2007-11-06
JP4266302B2 (ja) 2009-05-20
US6947320B2 (en) 2005-09-20
CN1503268A (zh) 2004-06-09
US20040100819A1 (en) 2004-05-27
US7154777B2 (en) 2006-12-26
US6898114B2 (en) 2005-05-24
JP2004178709A (ja) 2004-06-24
US20050276111A1 (en) 2005-12-15
US20050135166A1 (en) 2005-06-23
US20070127288A1 (en) 2007-06-07

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