CN100378949C - 具有钨插塞的金属结构 - Google Patents
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Abstract
本发明是关于一种具有钨插塞的金属结构,在较佳实施例中,较厚的一般介电常数介电质形成于衬底上。钨插塞形成于前述较厚的一般介电常数介电质中。此较厚的一般介电常数介电质为内缩,而较薄的低介电常数介电质则形成于此较厚的一般介电常数介电质上。前述较薄的低介电常数介电质作为粘着层以及蚀刻终止层。较厚的低介电常数介电质是形成于此较薄的低介电常数介电质上。视情况而定,可形成开口贯穿此较厚的低介电常数介电质以暴露出钨插塞。然后,前述开口以铜或铜合金填满。
Description
技术领域
本发明涉及一种集成电路结构,特别是涉及一种集成电路结构的内层介电质的具有钨插塞的金属结构(Inter Level Dielectric;ILD)。
背景技术
本申请案主张优先权为2004年4月6日在美国申请的第60/559,857号临时申请案,其发明名称为“具有钨插塞的稳定金属结构”,在此列为本案的参考文献。
集成电路不断缩微至深次微米领域,根据摩尔定律的历史趋势,在高效能、高密度的集成电路上的电晶体数量可高达数千万。这已迫使上述集成电路以多层高密度金属内连线为特征,而且这些层由内层介电质所分开,其中内层介电质有时亦称之为内金属介电质(Inter-Metal Dielectric;IMD)。与这些金属内连线相关的寄生电容(Parasite Capacitance)已经成为限制上述高效能集成电路的电路速度的一个主要因子。传统的内层介电质(亦为熟知的一般介电常数介电质)一般具有介电常数(亦为熟知的k值)介于约3.8至约8.0之间。然而,一般介电常数(Regular-k)介电质在介电值偏高时会导致高寄生电容。近来,低介电常数(Low-k)介电质,例如化学气相沉积黑钻石(应用材料公司的商标),其介电常数为约3.0,已广泛使用于半导体业,藉以减少金属导线间的寄生电容,因而改善电路效能。二氧化硅(其介电常数介于约3.8至约4.2)一般是用来作低介电常数介电质与一般介电常数介电质的分界线用。
然而,由于低介电常数材料的物性及化性与一般介电常数材料有相当大的差异,因此不能做为第一层介电质。举例而言,低介电常数材料一般具有高漏电电流、低崩溃电压、对覆盖层(Cap)与衬里层(Liner)粘着差,同时热稳定性低,因此靠近元件处使用低介电常数材料会降低其效能。
为了解决寄生电容的问题,常常使用由两层组成的复合结构。靠近元件处的一层是利用一般介电常数材料形成,而远离元件处的一层则利用低介电常数材料形成。如此有效降低寄生电容。不过,却又引起新的问题。在至少包含一般介电常数介电质的金属结构中,一般使用钨(包括导体衬里层/阻挡层,例如氮化钛)作为接触插塞,而较厚的低介电常数介电质、以及介于较厚的一般介电常数介电质与较厚的低介电常数介电质之间的粘着就不稳固。这会导致薄膜层离(FilmDelamination)并造成晶片良率低落。
由此可见,上述现有的具有钨插塞的金属结构在结构与使用上,显然仍存在有不便与缺陷,而亟待加以进一步改进。为了解决具有钨插塞的金属结构存在的问题,相关厂商莫不费尽心思来谋求解决之道,但长久以来一直未见适用的设计被发展完成,而一般产品又没有适切的结构能够解决上述问题,此显然是相关业者急欲解决的问题。
有鉴于上述现有的具有钨插塞的金属结构存在的缺陷,本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识,并配合学理的运用,积极加以研究创新,以期创设一种新型结构的具有钨插塞的金属结构,能够改进一般现有的具有钨插塞的金属结构,使其更具有实用性。经过不断的研究、设计,并经反复试作样品及改进后,终于创设出确具实用价值的本发明。
发明内容
本发明的目的在于,克服现有的具有钨插塞的金属结构存在的缺陷,而提供一种新的具有钨插塞的金属结构,所要解决的技术问题是使其本发明的目的的一就是揭露一种具有钨插塞的金属结构。本发明一较佳实施例是使较厚的一般介电常数介电质内缩,然后在较厚的一般介电常数介电质与较厚的低介电常数介电质之间形成较薄的低介电常数介电质,以加强较厚的一般介电常数介电质与较厚的低介电常数介电质之间的粘着,从而更加适于实用。
本发明的另一目的在于,提供一种具有钨插塞的金属结构,所要解决的技术问题是使其上述较薄的低介电常数介电质改善较厚的一般介电常数介电质与较厚的低介电常数介电质之间的粘着。内缩距离愈大,较厚的一般介电常数介电质与较厚的低介电常数介电质之间的粘着就愈佳,除了与较厚的一般介电常数介电质接触外,内缩更使得较厚的低介电常数介电质接触衬里层/阻挡层(Liner/Barrier)的侧壁表面且进一步加强粘着,从而更加适于实用。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种具有钨插塞的金属结构,其至少包含:一第一介电质,该第一介电质具有一上表面;一第二介电质位于该第一介电质上;低介电常数的一第三介电质位于该第二介电质上;一钨插塞位于该第一介电质、该第二介电质以及该第三介电质中,其中该钨插塞具有一顶面以及一底面,且其中在该钨插塞的该顶面与该第一介电质的该上表面之间的一垂直距离是介于约100埃()至约1000埃之间;以及一导电区电连接于该钨插塞的该底面。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的具有钨插塞的金属结构,其中所述的具有钨插塞的金属结构,其特征在于至少包含一硅衬底,其中该第一介电质是形成于该硅衬底上。
前述的具有钨插塞的金属结构,其中所述的导电区至少包含一材料,且该材料是选自于由掺杂硅、金属硅化物、硅锗及上述的组合所组成的一族群。
前述的具有钨插塞的金属结构,其中所述的第一介电质的一介电常数(k值)是介于3.3至4.3之间,且该第三介电质的一介电常数是低于3.2。
前述的具有钨插塞的金属结构,其中所述的钨插塞的一宽度少于1300埃。
前述的具有钨插塞的金属结构,其中所述的钨插塞的该顶面与该第一介电质的该上表面之间的该垂直距离是介于150埃至350埃之间。
前述的具有钨插塞的金属结构,其中所述的钨插塞的该顶面与该第一介电质的该上表面之间的该垂直距离是介于350埃至500埃之间。
前述的具有钨插塞的金属结构,其中所述的钨插塞的该顶面与该第一介电质的该上表面之间的该垂直距离是介于500埃至1000埃之间。
前述的具有钨插塞的金属结构,其中所述的第二介电质的一介电常数是小于5。
前述的具有钨插塞的金属结构,其中所述的第二介电质的一厚度是小于600埃。
前述的具有钨插塞的金属结构,其中所述的第二介电质的一材料至少包含硅或碳或上述二者。
前述的具有钨插塞的金属结构,其中所述的钨插塞的该顶面与该第二介电质的该上表面之间的一垂直距离是介于100埃至500埃之间。
前述的具有钨插塞的金属结构,其中所述的第三介电质是经由一旋涂(Spin-On)法形成的一有机低介电常数材料。
前述的具有钨插塞的金属结构,其更至少包含一内连线设于该第三介电质中,且其中该内连线封闭至少部分的该钨插塞的该顶面。
前述的具有钨插塞的金属结构,其更至少包含一阻挡层,其中该阻挡层封闭该内连线。
前述的具有钨插塞的金属结构,其中所述的钨插塞是由钨形成,且该内连线是由铜或铜合金形成。
前述的具有钨插塞的金属结构,其中所述的内连线的一宽度是小于1300埃。
本发明与现有技术相比具有明显的优点和有益效果。由以上技术方案可知,为了达到前述发明目的,本发明的主要技术内容如下:
本发明提出一种具有钨插塞的金属结构,在较佳实施例中,较厚的一般介电常数介电质是形成于衬底上。钨插塞是形成于高电常数介电质中。较厚的一般介电常数介电质是内缩,而较薄的低介电常数介电质则形成于此较厚的一般介电常数介电质上。前述较薄的低介电常数介电质作为粘着层以及蚀刻终止层。较厚的低介电常数介电质是形成于此较薄的低介电常数介电质上。视情况而定,形成开口贯穿此较厚的低介电常数介电质以暴露出钨插塞。然后,前述开口以铜或铜合金填满。
借由上述技术方案,本发明具有钨插塞的金属结构至少具有下列优点:
本发明的优点之一在于使较厚的一般介电常数介电质内缩,然后在较厚的一般介电常数介电质与较厚的低介电常数介电质之间形成较薄的低介电常数介电质,以加强较厚的一般介电常数介电质与较厚的低介电常数介电质之间的粘着,从而更加适于实用。
其次,本发明之另一优点在于使其上述较薄的低介电常数介电质改善较厚的一般介电常数介电质与较厚的低介电常数介电质之间的粘着。内缩距离愈大,较厚的一般介电常数介电质与较厚的低介电常数介电质之间的粘着就愈佳,除了与较厚的一般介电常数介电质接触外,内缩更使得较厚的低介电常数介电质接触衬里层/阻挡层的侧壁表面且进一步加强粘着,从而更加适于实用。
综上所述,本发明特殊结构的具有钨插塞的金属结构,其具有上述诸多的优点及实用价值,并在同类产品中未见有类似的结构设计公开发表或使用而确属创新,其不论在产品结构或功能上皆有较大的改进,在技术上有较大的进步,并产生了好用及实用的效果,且较现有的具有钨插塞的金属结构具有增进的多项功效,从而更加适于实用,而具有产业的广泛利用价值,诚为一新颖、进步、实用的新设计。
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,而可依照说明书的内容予以实施,并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂,以下特举较佳实施例,并配合附图,详细说明如下。
附图说明
图1至图9是本发明一较佳集成电路结构制程的中间阶段的剖面图。
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例,对依据本发明提出的具有钨插塞的金属结构其具体实施方式、结构、特征及其功效,详细说明如后。
请参阅图1至图9所示,图1说明导电区4以及衬底2。在一较佳实施例中,导电区4可为源极/汲极,而此源极/汲极是以磊晶成长的材料形成于衬底2所形成的凹陷(Recess)中。在另一实施例中,导电区4可为源极/汲极,而此源极/汲极是利用习知磊晶技术而磊晶沉积于衬底2上。在其他实施例中,导电区4可为闸极结构(图未绘示),其中该闸极是形成于衬底2上。
导电区4亦可包括在源极/汲极或复晶硅闸极(Gate Poly)上形成金属硅化物(Silicide)。金属硅化物改善下方区域与后续步骤形成的金属接触插塞之间的接触。当了解的是,可藉由许多用于集成电路制造的材料而形成导电区4。举例而言,导电区4可为金属导线或复合金属导线,是用来连接另一层的集成电路。又,当了解的是,衬底2仅为说明针对导电区4的诸多环境之一。衬底2可为硅衬底或其他材料,例如硅锗(SiGe)、整体半导体、多层半导体、绝缘层上硅(Silicon-On-Insulator;SOI)、绝缘层上硅锗(SiGeOI)或绝缘层上锗(GeOI)。
接下来,请参阅图2所示,较厚的一般介电常数内层介电质(Inter LevelDielectric;ILD)6是沉积于衬底2以及导电区4上。如习知技术所示,内层介电质6隔离元件以及后续步骤形成于上方的金属导线。在整个本发明较佳实施例的叙述中,较厚的一般介电常数内层介电质6亦为第一介电质6。第一介电质6以一般介电常数介电质为较佳,且第一介电质6的介电常数(k值)是介于约3.3至约4.3的间,而以约4.0为更佳。在一较佳实施例中,第一介电质6为磷硅玻璃(Phosphosilicate Glass;PSG),其介电常数为约4.0。在其他实施例中,第一介电质6为氮化硅或氧化硅,可利用例如电浆加强式化学气相沉积(Plasma-Enhanced Chemical Vapor Deposition;PECVD)、高密度电浆化学气相沉积(High Density Plasma CVD;HDP)、低压化学气相沉积(Low Pressure CVD;LPCVD)、次大气压化学气相沉积(Sub-Atmosphere CVD;SACVD)、或其他习知沉积技术进行沉积。第一介电质6形成的厚度以约2000埃至约8000埃为较佳,而以约5000埃为更佳。值得注意的是,由于介电常数低于约3.8的低介电常数材料的物性及化性明显不同于一般介电常数材料,因此,靠近元件的第一介电质6一般并不使用介电常数低于约3.8的低介电常数材料。举例而言,低介电常数材料一般具有漏电电流高、崩溃电压低、对覆盖层与衬里层粘着差,同时热稳定性低,因此靠近元件处使用低介电常数材料会降低其效能。
亦如图3所示,光阻8形成于第一介电质6上且经图案化。接着,在第一介电质6内形成开口10。开口10的形成为习知技术所熟知。然后,利用光阻剥除制程完全去除光阻8。
图4说明沿着侧壁及底部而形成阻挡层11(亦为熟知的衬里层)于接触开口10内。阻挡层11以由氮化钛(Titanium Nitride;TiN)形成为较佳。亦可使用其他材料例如氮化钽(TaN)及氮化钛硅(TiSiN)。氮化钛为有效的阻挡层,是用于避免接触金属移入第一介电质6中。氮化钛亦可作为粘着层以增进钨插塞对第一介电质6的粘着。一般而言,阻挡层11是由电浆加强式化学气相沉积(PECVD)所形成。亦可由物理气相沉积(Physical Vapor Deposition;PVD)所形成。阻挡层11的厚度以介于约50埃至约300埃为较佳,且以介于100埃至150埃为更佳。
剩余部分的接触开口10是由接触插塞12填满,而如图4所示。在较佳实施例中,接触插塞12的材料是利用化学气相沉积由六氟化钨(Hexafluoride;WF6)沉积钨。在其他实施例中,接触开口10可由铝或其他材料例如铜及铜合金填满。形成上述材料的方法已为习知技术所熟知。
图5说明第一介电质6为内缩。凹陷13以利用化学机械研磨(ChemicalMechanica 1Polishing;CMP)、电浆蚀刻或湿蚀刻进行为较佳。当了解的是内缩的垂直距离h影响第一介电质6与后续形成的低介电常数介电质之间粘着。由于较大的内缩垂直距离所提供与低介电常数介电质接触的表面就愈多,因此内缩的垂直距离愈大,粘着就越佳。此外,较大的垂直距离会更加提高锚定效应(Anchoring Effect)。凹陷13的较佳垂直距离h,即由接触插塞12的顶面至第一介电质6的上表面,是约100埃至约1000埃之间。较佳者是介于约150埃至约350埃、以及约350埃至约500埃之间,而更佳者是介于约500埃至约1000埃。
图6说明较薄的第二介电质18形成于第一介电质6及接触插塞12上。第二介电质18为中介层(Intermediate Layer),是具有较佳粘着力以结合将第一介电质6与第三介电质二者,其中第三介电质是形成于第二介电质18上,以便于改善第一介电质6与第三介电质之间的粘着。第二介电质18亦可于后续步骤中作为蚀刻终止层。第二介电质18的厚度以少于约600埃为较佳,藉此减少电容以进一步改善电阻/电容延迟时间(RC Delay Time)。介于接触插塞12的上表面至第二介电质18的上表面的垂直距离d2(如第6图所示)以介于约100埃至约500埃为较佳。
第二介电质18预设对于低介电常数的第三介电质的粘着良好,且第二介电质18的介电常数高于第三介电质的介电常数以作为良好的蚀刻终止层。第二介电质18亦预设其厚度少于约600埃以减少电容而进一步改善电阻/电容延迟时间。第二介电质18的介电常数以低于约5为较佳。在一较佳实施例中,至少包含硅及碳的材料,例如介电常数约4的碳化硅(SiC)或碳掺杂的氧化硅,是用于作为介于磷硅玻璃(介电常数约4.2)与化学气相沉积黑钻石(介电常数约3.0)之间的粘着层及蚀刻终止层。
第三介电质20是形成于第二介电质18上,如图7的所示。第三介电质20的厚度以介于约1500埃至约5000埃之间为较佳,且以约2500埃为更佳。在一较佳实施例中,第三介电质20为介电常数约3.0的黑钻石。在其他实施例中,亦可使用由旋涂(Spin-On)法形成的有机低介电常数介电质,例如氢氧硅碳(SiCOH),而且亦可使用甲基-倍半氧硅烷(Methyl-Silsesquioxane;MSQ)。第三介电质20的介电常数以低于约3.2为较佳。较佳的方法为化学气相沉积,不过亦可使用其他已知方法例如旋涂。
在一较佳实施例中,形成开口22贯穿第三介电质20及第二介电质18以暴露出接触插塞12,而如图8所示。一般而言,开口22的形状为沟渠,其中沟渠中沉积低阻抗金属以作为内连线。开口22以比接触插塞12宽为较佳,其较佳宽度W22为小于约1300埃。开口22底部以低于第二介电质18的上表面为较佳。利用至少包含氟的气体化学进行电浆蚀刻而形成开口22为较佳。
在开口22中形成阻挡层23以避免后续步骤中所形成的铜扩散。阻挡层23以由氮化钽形成者为较佳。
然后,开口22内填满导体材料而形成内连线24,如图9所示。在一较佳实施例中,开口22内利用电化学电镀或化学气相沉积以填满低阻抗金属例如铜或铜合金。在其他实施例中,开口22内可填铝或铝合金。铜或铜合金形成的内连线24以由电化学电镀或无电电镀(Electroless Plating)技术形成为较佳。
上述论及较佳实施例的有利特征之一在于藉由内缩第一介电质,以改善较厚的一般介电常数介电质与较厚的低介电常数介电质之间的粘着。大体而言,内缩的垂直距离愈大,较厚的一般介电常数介电质与较厚的低介电常数介电质之间的粘着就愈佳,所形成的金属结构就愈稳定。实际内缩的垂直距离与第一介电质以及第三介电质的厚度有关,熟习此项技艺者无须过度实验即可找出适当的数值。
纵然以上已详述本发明及其优点,在不脱离本发明后附的申请专利范围所界定的精神和范围内,当可作各种的更动、替换及润饰。再者,虽然本发明已如上揭露数个较佳的制程、机构、制造、物的组成、手段、方法及步骤的实施例,然其并非用以限定本发明申请书的范围。任何熟习此技艺者,在不脱离本发明的精神和范围内,当可作各种的更动与润饰,因此后附的申请专利范围意指包括本发明的制程、机构、制造、物的组成、手段、方法及步骤等范围。
Claims (17)
1.一种具有钨插塞的金属结构,其特征在于其至少包含:
一第一介电质,该第一介电质具有一上表面;
一第二介电质位于该第一介电质上;
低介电常数的一第三介电质位于该第二介电质上;
—钨插塞位于该第一介电质、该第二介电质以及该第三介电质中,其中该钨插塞具有一顶面以及一底面,且其中在该钨插塞的该顶面与该第一介电质的该上表面之间的一垂直距离是介于100埃至1000埃之间;以及
一导电区电连接于该钨插塞的该底面。
2.根据权利要求1所述的具有钨插塞的金属结构,其特征在于至少包含一硅衬底,其中该第一介电质是形成于该硅衬底上。
3.根据权利要求1所述的具有钨插塞的金属结构,其特征在于其中所述的导电区至少包含一材料,且该材料是选自于由掺杂硅、金属硅化物、硅锗及上述的组合所组成的一族群。
4.根据权利要求1所述的具有钨插塞的金属结构,其特征在于其中所述的第一介电质的一介电常数是介于3.3至4.3之间,且该第三介电质的一介电常数是低于3.2。
5.根据权利要求4所述的具有钨插塞的金属结构,其特征在于其中所述的钨插塞的一宽度少于1300埃。
6.根据权利要求1所述的具有钨插塞的金属结构,其特征在于其中所述的钨插塞的该顶面与该第一介电质的该上表面之间的该垂直距离是介于150埃至350埃之间。
7.根据权利要求1所述的具有钨插塞的金属结构,其特征在于其中所述的钨插塞的该顶面与该第一介电质的该上表面之间的该垂直距离是介于350埃至500埃之间。
8.根据权利要求1所述的具有钨插塞的金属结构,其特征在于其中所述的钨插塞的该顶面与该第一介电质的该上表面之间的该垂直距离是介于500埃至1000埃之间。
9.根据权利要求1所述的具有钨插塞的金属结构,其特征在于其中所述的第二介电质的一介电常数是小于5。
10.根据权利要求1所述的具有钨插塞的金属结构,其特征在于其中所述的第二介电质的一厚度是小于600埃。
11.根据权利要求1所述的具有钨插塞的金属结构,其特征在于其中所述的第二介电质的一材料至少包含硅或碳。
12.根据权利要求11所述的具有钨插塞的金属结构,其特征在于其中所述的钨插塞的该顶面与该第二介电质的该上表面之间的一垂直距离是介于100埃至500埃之间。
13.根据权利要求1所述的具有钨插塞的金属结构,其特征在于其中所述的第三介电质是经由一旋涂法形成的一有机低介电常数材料。
14.根据权利要求1所述的具有钨插塞的金属结构,其特征在于更至少包含一内连线设于该第三介电质中,且其中该内连线封闭至少部分的该钨插塞的该顶面。
15.根据权利要求14所述的具有钨插塞的金属结构,其特征在于更至少包含一阻挡层,其中该阻挡层封闭该内连线。
16.根据权利要求14所述的具有钨插塞的金属结构,其特征在于其中所述的钨插塞是由钨形成,且该内连线是由铜或铜合金形成。
17.根据权利要求16所述的具有钨插塞的金属结构,其特征在于其中所述的内连线的一宽度是小于1300埃。
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US6867433B2 (en) * | 2003-04-30 | 2005-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
US20050012087A1 (en) * | 2003-07-15 | 2005-01-20 | Yi-Ming Sheu | Self-aligned MOSFET having an oxide region below the channel |
US7078742B2 (en) | 2003-07-25 | 2006-07-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained-channel semiconductor structure and method of fabricating the same |
US6936881B2 (en) | 2003-07-25 | 2005-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitor that includes high permittivity capacitor dielectric |
US7112495B2 (en) | 2003-08-15 | 2006-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
US7071052B2 (en) * | 2003-08-18 | 2006-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Resistor with reduced leakage |
US7888201B2 (en) | 2003-11-04 | 2011-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors |
KR100539257B1 (ko) * | 2004-04-07 | 2005-12-27 | 삼성전자주식회사 | 패턴 형성을 위한 반도체 구조 및 패턴 형성 방법 |
US7170174B2 (en) * | 2004-08-24 | 2007-01-30 | Micron Technology, Inc. | Contact structure and contact liner process |
US9202758B1 (en) * | 2005-04-19 | 2015-12-01 | Globalfoundries Inc. | Method for manufacturing a contact for a semiconductor component and related structure |
US8558278B2 (en) | 2007-01-16 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained transistor with optimized drive current and method of forming |
US8286114B2 (en) * | 2007-04-18 | 2012-10-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3-dimensional device design layout |
US8237201B2 (en) | 2007-05-30 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout methods of integrated circuits having unit MOS devices |
US7943961B2 (en) | 2008-03-13 | 2011-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain bars in stressed layers of MOS devices |
US7863176B2 (en) * | 2008-05-13 | 2011-01-04 | Micron Technology, Inc. | Low-resistance interconnects and methods of making same |
US7808051B2 (en) | 2008-09-29 | 2010-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Standard cell without OD space effect in Y-direction |
US8193089B2 (en) * | 2009-07-13 | 2012-06-05 | Seagate Technology Llc | Conductive via plug formation |
US8283202B2 (en) | 2009-08-28 | 2012-10-09 | International Business Machines Corporation | Single mask adder phase change memory element |
US8283650B2 (en) * | 2009-08-28 | 2012-10-09 | International Business Machines Corporation | Flat lower bottom electrode for phase change memory cell |
US8012790B2 (en) * | 2009-08-28 | 2011-09-06 | International Business Machines Corporation | Chemical mechanical polishing stop layer for fully amorphous phase change memory pore cell |
US8129268B2 (en) * | 2009-11-16 | 2012-03-06 | International Business Machines Corporation | Self-aligned lower bottom electrode |
US7943420B1 (en) * | 2009-11-25 | 2011-05-17 | International Business Machines Corporation | Single mask adder phase change memory element |
US8088660B1 (en) * | 2010-12-15 | 2012-01-03 | Infineon Technologies Austria Ag | Method for producing a plug in a semiconductor body |
US20130299993A1 (en) * | 2012-05-11 | 2013-11-14 | Hsin-Yu Chen | Interconnection of semiconductor device and fabrication method thereof |
US9627250B2 (en) * | 2013-03-12 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for back end of line semiconductor device processing |
US9780025B2 (en) | 2014-12-30 | 2017-10-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnection structure and manufacturing method thereof |
US9576903B2 (en) * | 2015-07-16 | 2017-02-21 | Macronix International Co., Ltd. | Structure with conductive plug and method of forming the same |
TWI578440B (zh) * | 2015-07-16 | 2017-04-11 | 旺宏電子股份有限公司 | 導體插塞及其製造方法 |
KR102503941B1 (ko) | 2017-12-07 | 2023-02-24 | 삼성전자주식회사 | 반도체 장치 |
US10943983B2 (en) | 2018-10-29 | 2021-03-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuits having protruding interconnect conductors |
KR20210065514A (ko) * | 2019-11-27 | 2021-06-04 | 삼성전자주식회사 | 집적 회로 반도체 소자의 상호 접속 구조체 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5470788A (en) * | 1994-02-28 | 1995-11-28 | International Business Machines Corporation | Method of making self-aligned, lateral diffusion barrier in metal lines to eliminate electromigration |
JPH09321137A (ja) * | 1996-05-24 | 1997-12-12 | Nec Corp | 半導体装置およびその製造方法 |
US5723362A (en) * | 1995-07-21 | 1998-03-03 | Sony Corporation | Method of forming interconnection |
CN1233846A (zh) * | 1998-04-29 | 1999-11-03 | 世大积体电路股份有限公司 | 半导体元件避免钨插塞损失阻挡层的制造方法 |
JP2002050689A (ja) * | 2000-08-07 | 2002-02-15 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
CN1453844A (zh) * | 2002-04-23 | 2003-11-05 | 旺宏电子股份有限公司 | 具有间隙的铁电电容 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0997833A (ja) * | 1995-07-22 | 1997-04-08 | Ricoh Co Ltd | 半導体装置とその製造方法 |
US6593653B2 (en) * | 1999-09-30 | 2003-07-15 | Novellus Systems, Inc. | Low leakage current silicon carbonitride prepared using methane, ammonia and silane for copper diffusion barrier, etchstop and passivation applications |
US6815329B2 (en) * | 2000-02-08 | 2004-11-09 | International Business Machines Corporation | Multilayer interconnect structure containing air gaps and method for making |
US6548901B1 (en) * | 2000-06-15 | 2003-04-15 | International Business Machines Corporation | Cu/low-k BEOL with nonconcurrent hybrid dielectric interface |
US6677679B1 (en) * | 2001-02-06 | 2004-01-13 | Advanced Micro Devices, Inc. | Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers |
US6713874B1 (en) * | 2001-03-27 | 2004-03-30 | Advanced Micro Devices, Inc. | Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-layer dielectrics |
US6555467B2 (en) * | 2001-09-28 | 2003-04-29 | Sharp Laboratories Of America, Inc. | Method of making air gaps copper interconnect |
US6917108B2 (en) * | 2002-11-14 | 2005-07-12 | International Business Machines Corporation | Reliable low-k interconnect structure with hybrid dielectric |
-
2004
- 2004-08-17 US US10/919,875 patent/US7224068B2/en active Active
- 2004-11-15 TW TW093134988A patent/TWI247408B/zh active
- 2004-12-06 CN CNB2004100969312A patent/CN100378949C/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5470788A (en) * | 1994-02-28 | 1995-11-28 | International Business Machines Corporation | Method of making self-aligned, lateral diffusion barrier in metal lines to eliminate electromigration |
US5723362A (en) * | 1995-07-21 | 1998-03-03 | Sony Corporation | Method of forming interconnection |
JPH09321137A (ja) * | 1996-05-24 | 1997-12-12 | Nec Corp | 半導体装置およびその製造方法 |
CN1233846A (zh) * | 1998-04-29 | 1999-11-03 | 世大积体电路股份有限公司 | 半导体元件避免钨插塞损失阻挡层的制造方法 |
JP2002050689A (ja) * | 2000-08-07 | 2002-02-15 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
CN1453844A (zh) * | 2002-04-23 | 2003-11-05 | 旺宏电子股份有限公司 | 具有间隙的铁电电容 |
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US20050224986A1 (en) | 2005-10-13 |
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US7224068B2 (en) | 2007-05-29 |
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