CN1233846A - 半导体元件避免钨插塞损失阻挡层的制造方法 - Google Patents
半导体元件避免钨插塞损失阻挡层的制造方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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Abstract
一种半导体元件减少钨损失阻挡层的制造方法,所述制造方法至少包括:提供具有一介电层的一元件,至少包括一高高宽比接触窗开口;以化学气相沉积法沉积一氮化钛共形膜;以物理气相沉积法沉积一氮化钛膜;以及以化学气相沉积法沉积一金属钨,至少填入所述高高宽比接触窗开口。
Description
本发明涉及一种半导体元件中形成钨插塞的制造方法,特别是涉及一种从硅基底分离钨插基的氮化钛阻挡层的制造方法。
半导体元器件已广泛地得到使用,各种元件与设备已成为生活中不可或缺的。这些元件的制备是在一基础的硅晶圆基底,经由一系列的制作过程,包括选择性蚀刻与薄膜的沉积,在晶圆上形成极小的结构,从而可以实现电路设计的功能。
由硅晶圆制造半导体元件的过程,有时在内介电层(interlayerdielectrics)中需要形成一具有高的高宽比(aspect ratio)的接触窗开口(contact hole)以填入金属钨。然而,有许多的理由显示出,钨插塞与介电层直接接触是不适当的。因此,在钨插塞与介电层之间通常以一“阻挡层(barrier layer)”或“阻挡膜(barrier film)”隔离。然而,现有的形成阻挡层的方法存在不足,会导致“插塞损失(plugloss)”与具有缺陷的元件。如图1所示,其描述现有技术,在一介电层中具有一高高宽比开口10,并且例如以物理气相沉积法(PVD)涂覆(coat)一氮化钛膜12,而PVD氮化钛未能符合开口的形状而涂覆,也就是未能覆盖具有高高宽比开口的全部表面。更精确地说,在开口底部16与上部前端18覆盖有PVD氮化钛,而PVD氮化钛未能覆盖开口底部末端14。若在开口填进钨,钨与介电层S将有直接接触。因此,阻挡层的形成以传统技术取代,例如以化学气相沉积法(CVD)形成,如图2A所示,CVD制作过程在具有高的高宽比开口20中形成一共形层(conformal layer)22,开口可填满钨以形成插塞24,例如以化学气相沉积或其它技术进行,如图2B所示。之后,钨层的干蚀刻无法避免而导致“插基损失”,亦即在蚀刻制作工艺中,钨24a的上部将遭移除,如图2C所示,结果造成一具有缺陷的元件。
在半导体元件制作工艺中形成钨插塞的制造方法具有一需求,亦即大体上需维持完整的插塞并使插塞损失减至最低。同时,此方法相对地需要较为经济且简易,以整合标准半导体制造技术。
有鉴于此,本发明的主要目的在于提供一种降低钨插塞损失的半导体工艺制造方法。本发明的方法,具有一高高宽比表面外观的介电层,如一开口,在其上提供至少包括两层膜的一阻挡层。在本制造方法的第一步骤,以化学气相沉积法沉积具有一共形膜的氮化钛层,另一步骤,另一氮化钛膜以物理气相沉积法形成。之后,再以传统制作工艺沉积钨,如化学气相沉积法,以填入具有高高宽比的表面外观。
在移除过多的钨方面,例如以干蚀刻回蚀刻制作工艺,钨插塞基本上仍完整无缺,而任何钨插塞损失与现有技术相比均很微小。于是,本发明藉由在CVD氮化钛膜形成后,额外进行物理气相沉积形成一氯化钛膜,而充分地减少钨插塞损失,因此可降低形成缺陷半导体元件的风险。
为使本发明的上述和其他目的、特征和优点能更明显易懂,下文特举一优选实施例,并配合附图作详细说明。附图中;
图1是显示一种现有PVD氯化钛膜应用在具有一高高宽比表面外观,如一接触窗开口的一剖面图;
图2A与图2C是显示一种以化学气相沉积法形成共形氯化钛膜后的高高宽比表面外观,与将其填满钨插塞的剖面图,以及经干蚀刻形成钨插塞损失的剖面图;以及
图3A至图3D是显示根据本发明优选实施例的制造流程剖面图,在以化学气相沉积法形成一共形氯化钛膜后,再以物理气相沉积法形成一氮化钛膜,以及进行一干蚀刻去除过多的钨。
本发明涉及在半导体制作过程中,以硅为半导体元件基底的一种减少钨插塞损失的制造方法。如上所述,在具有高高宽比的接触窗开口,一般而言,硅基底与钨需以一阻挡层分离。在本发明中,一阻挡层以此项理由存在并不特别恰当,在优选的元件操作中,阻挡层的存在相信是需要的。
根据本发明,减少钨插塞损失的一优选的阻挡层至少包括两层膜,其包括,在一具有高高宽比表面外观中,以化学气相沉积法沉积一氮化钛的共形膜,以及以物理气相沉积法形成的另一氮化钛膜。后者的PVD氯化钛膜不会完全覆盖具有高高宽比表面外观的基底,事实上,其不会覆盖表面外观的较低未端。接着形成钨插塞,沉积足够的钨插塞,使其至少填满具有高的高宽比的表面外观。再以任何已知的方法移除过多的钨,例如干蚀刻回蚀制作工艺。
本发明以所附的图3A至图3D可以得到更好的了解,作为本发明原理的说明,其并非用以限制本发明的范围。
图3A至图3D显示在一硅基底S上具有一高高宽比的表面外观30。一般而言,一具有高高宽比的一高宽比(h/d)约为2-15,特别是3-15左右。
如图3A所示,根据本发明,在具有高高宽比表面外观30上,以化学气相沉积法形成一氮化钛共形膜32,并延伸至内介电层S表面上,而优选厚度约为50-200埃。接着,另一氮化钛层34,优选厚度约为100-1000埃,以传统的物理气相沉积法形成。膜34通常具有较差的“阶梯覆盖性(stepcoverage)”,其中通常并不需要提供高高宽比表面外观的共形覆盖,如图3B所示。因此,可以预期的在开口或沟槽的内表面部位并不会被膜所覆盖。
根据上述所提,一“阻挡层”因而形成,此时,在开口沉积钨以形成一插塞36,如图3C所示。钨插塞36通常以化学气相沉积法形成,填入具有高高宽比的外观,而沉积制作工艺进行的结果通常还有多余的钨延伸至介电层S的周围表面。
为了制作一具有功能的元件,通常需要移除过多的钨,仅在高高宽比外观30中维持钨插塞36,如图3D所示。因此,过多的钨以传统干蚀刻法回蚀。当以干蚀刻法回蚀进行时,过多的钨将被移除,而高高宽比外观30中的钨插塞36基本上不会改变,即使有一些钨损失,与现有技术比也是微小的,故元件不会因钨损失而在电性能上有所缺陷。本发明所实行的方法,基本上可以忽略钨插塞损失,因此可以克服现有技术的缺点。
虽然本发明已结合一优选实施例揭露如上,但是其并非用以限定本发明,本领域的技术人员在不脱离本发明的精神和范围内,可作出各种更动与润饰,因此本发明的保护范围应当由后附的权利要求界定。
Claims (10)
1.一种半导体元件减少钨损失阻挡层的制造方法,所述制造方法至少包括:
提供具有一介电层的一元件,至少包括一高高宽比接触窗开口;
以化学气相沉积法沉积一氮化钛共形膜;
以物理气相沉积法沉积一氮化钛膜;以及
以化学气相沉积法沉积一金属钨,至少填入所述高高宽比接触窗开口。
2.如权利要求1所述的制造方法,其中,所述氮化钛共形膜厚度约为50-200埃。
3.如权利要求1所述的制造方法,其中,所述氮化钛膜厚度约为100-1000埃。
4.如权利要求1所述的制造方法,其中,所述接触窗的高宽比约为2-15。
5.一种半导体元件减少钨损失阻挡层的制造方法,所述制造方法至少包括:
提供具有一介电层的一元件,至少包括一高高宽比接触窗开口;
以化学气相沉积法沉积一氮化钛共形膜;
以物理气相沉积法沉积一氯化钛膜;
以化学气相沉积法沉积一金属钨,至少填入所述高高宽比接触窗开口;以及
去除过多的所述金属钨,维持所述接触窗填满钨。
6.如权利要求5所述的制造方法,其中,所述氮化钛共形膜厚度约为50-200埃。
7.如权利要求5所述的制造方法,其中,所述氯化钛膜厚度约为1001000埃。
8.如权利要求5所述的制造方法,其中,所述接触窗的高宽比约为2-15。
9.一种半导体元件减少钨损失阻挡层的制造方法,所述制造方法至少包括:
提供具有一介电层的一元件,至少包括一高高宽比接触窗开口;
以化学气相沉积法沉积一氮化钛共形膜,所述氮化钛共形膜厚度约为50200埃;
以物理气相沉积法沉积一氮化钛膜,所述氮化钛膜厚度约为100-1000埃;以及
以化学气相沉积法沉积一金属钨,至少填入所述高高宽比接触窗开口。
10.如权利要求9所述的制造方法,还包括,从所述高高宽比表面外观的所述介电层表面移除过多的所述金属钨,以维持所述表面外观可填满所述金属钨。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US069,711 | 1998-04-29 | ||
US09/069,711 US6022800A (en) | 1998-04-29 | 1998-04-29 | Method of forming barrier layer for tungsten plugs in interlayer dielectrics |
US069711 | 1998-04-29 |
Publications (2)
Publication Number | Publication Date |
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CN1233846A true CN1233846A (zh) | 1999-11-03 |
CN1125481C CN1125481C (zh) | 2003-10-22 |
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CN98115641A Expired - Lifetime CN1125481C (zh) | 1998-04-29 | 1998-07-03 | 半导体元件避免钨插塞损失阻挡层的制造方法 |
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US (1) | US6022800A (zh) |
CN (1) | CN1125481C (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100378949C (zh) * | 2004-04-06 | 2008-04-02 | 台湾积体电路制造股份有限公司 | 具有钨插塞的金属结构 |
CN101552224B (zh) * | 2008-04-03 | 2010-11-10 | 和舰科技(苏州)有限公司 | 一种微通孔钨损失的解决方法 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000041235A1 (en) | 1999-01-08 | 2000-07-13 | Applied Materials, Inc. | Method of depositing a copper seed layer which promotes improved feature surface coverage |
JP3459372B2 (ja) * | 1999-03-18 | 2003-10-20 | 株式会社神戸製鋼所 | 配線膜の形成方法 |
US6174795B1 (en) * | 1999-03-31 | 2001-01-16 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for preventing tungsten contact plug loss after a backside pressure fault |
US6218298B1 (en) * | 1999-05-19 | 2001-04-17 | Infineon Technologies North America Corp. | Tungsten-filled deep trenches |
US6380628B2 (en) * | 1999-08-18 | 2002-04-30 | International Business Machines Corporation | Microstructure liner having improved adhesion |
US7071563B2 (en) | 2001-09-28 | 2006-07-04 | Agere Systems, Inc. | Barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer |
US6661097B1 (en) | 2002-11-01 | 2003-12-09 | International Business Machines Corporation | Ti liner for copper interconnect with low-k dielectric |
KR20060079461A (ko) * | 2004-12-31 | 2006-07-06 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속배선 형성방법 |
US7407875B2 (en) * | 2006-09-06 | 2008-08-05 | International Business Machines Corporation | Low resistance contact structure and fabrication thereof |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS624170A (ja) * | 1985-06-28 | 1987-01-10 | Central Glass Co Ltd | 板状体の起し装置 |
US5162262A (en) * | 1989-03-14 | 1992-11-10 | Mitsubishi Denki Kabushiki Kaisha | Multi-layered interconnection structure for a semiconductor device and manufactured method thereof |
JP2537413B2 (ja) * | 1989-03-14 | 1996-09-25 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US5472912A (en) * | 1989-11-30 | 1995-12-05 | Sgs-Thomson Microelectronics, Inc. | Method of making an integrated circuit structure by using a non-conductive plug |
US5614756A (en) * | 1990-04-12 | 1997-03-25 | Actel Corporation | Metal-to-metal antifuse with conductive |
US5300813A (en) * | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
US5342652A (en) * | 1992-06-15 | 1994-08-30 | Materials Research Corporation | Method of nucleating tungsten on titanium nitride by CVD without silane |
KR970001883B1 (ko) * | 1992-12-30 | 1997-02-18 | 삼성전자 주식회사 | 반도체장치 및 그 제조방법 |
JPH07268622A (ja) * | 1994-03-01 | 1995-10-17 | Applied Sci & Technol Inc | マイクロ波プラズマ付着源 |
AU1745695A (en) * | 1994-06-03 | 1996-01-04 | Materials Research Corporation | A method of nitridization of titanium thin films |
US5418180A (en) * | 1994-06-14 | 1995-05-23 | Micron Semiconductor, Inc. | Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon |
JPH08107087A (ja) * | 1994-10-06 | 1996-04-23 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JPH08170174A (ja) * | 1994-12-14 | 1996-07-02 | Nec Corp | TiN膜の形成方法 |
JPH08181212A (ja) * | 1994-12-26 | 1996-07-12 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US5545592A (en) * | 1995-02-24 | 1996-08-13 | Advanced Micro Devices, Inc. | Nitrogen treatment for metal-silicide contact |
US5610106A (en) * | 1995-03-10 | 1997-03-11 | Sony Corporation | Plasma enhanced chemical vapor deposition of titanium nitride using ammonia |
US5567483A (en) * | 1995-06-05 | 1996-10-22 | Sony Corporation | Process for plasma enhanced anneal of titanium nitride |
JPH0936228A (ja) * | 1995-07-21 | 1997-02-07 | Sony Corp | 配線形成方法 |
KR100220935B1 (ko) * | 1995-12-15 | 1999-09-15 | 김영환 | 메탈 콘택 형성방법 |
US5654233A (en) * | 1996-04-08 | 1997-08-05 | Taiwan Semiconductor Manufacturing Company Ltd | Step coverage enhancement process for sub half micron contact/via |
US5833817A (en) * | 1996-04-22 | 1998-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for improving conformity and contact bottom coverage of sputtered titanium nitride barrier layers |
US5688718A (en) * | 1997-02-03 | 1997-11-18 | Taiwan Semiconductor Manufacturing Company Ltd | Method of CVD TiN barrier layer integration |
-
1998
- 1998-04-29 US US09/069,711 patent/US6022800A/en not_active Expired - Fee Related
- 1998-07-03 CN CN98115641A patent/CN1125481C/zh not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100378949C (zh) * | 2004-04-06 | 2008-04-02 | 台湾积体电路制造股份有限公司 | 具有钨插塞的金属结构 |
CN101552224B (zh) * | 2008-04-03 | 2010-11-10 | 和舰科技(苏州)有限公司 | 一种微通孔钨损失的解决方法 |
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US6022800A (en) | 2000-02-08 |
CN1125481C (zh) | 2003-10-22 |
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