CN1110083C - 半导体器件的制造方法 - Google Patents
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Abstract
一种半导体器件的制造方法包括:在半导体基片上依次形成铝膜、阻挡金属膜和中间绝缘层;在中间绝缘层的整个表面上形成PVD-Al膜,并在其上腐蚀开出通路孔使阻挡金属膜的部分上表面暴露;以PVD-Al膜表面上自然形成的氧化物膜作为掩膜,用选择CVD法将通路孔填满金属以形成通路销;去除氧化物膜,用CVD-Al膜整个覆盖PVD-Al膜和通路销的表面。
Description
技术领域
本发明涉及一种半导体器件的制造方法,特别是一种在多层半导体器件的制造工艺中,制备引线金属膜,与金属膜相连接的通路销,或连接各元件的电极与金属膜的连接销的制造方法。
背景技术
近年来像LSI等半导体器件在大规模、密度、和运算速度等方面已经有了很大的进展,其趋势是将各个元件和金属连线在一块半导体基片上垂直地相互叠加起来形成一个多层结构。在这种多层半导体器件中,为了使位于下层的分立元件如三极管、二极管工作,需要将这些分立元件的电极与上层的金属引线连接在一起。为了这个目的就要在用于隔绝上下层的中间绝缘层上开孔(称为连接孔),然后在孔中填进金属材料以形成金属销(称为连接销),通过这种方法使不同层的各种元件的电极与金属连线相互连接起来。
进一步讲,在多层半导体器件中,需要将下层的金属连线与上层的连线连接在一起,这样就要在中间绝缘层上开孔(称为通路孔),然后在孔中填进金属材料以形成金属销(称为通路塞),通过这种方法使下层与上层的金属连线相互连接起来。
近来随着半导体器件在规模化、密度和运算速度方面的进展,进一步要求减小连接孔和通路孔的尺寸;然而同时在另一方面,由于在半导体基片上形成电容器的结构复杂性和使用化学机械抛光(CMP)方法整平中间绝缘层等原因,又使中间绝缘层趋于加厚。结果,在一个4M bit的MRAM上,连接孔和通路孔的形状比大约为2;而在一个258M bit的MRAM上,这些孔的形状比为4或更大,这里的形状比指孔的直径(水平方向)与深度(垂直方向)之比。这种形状比的增加,要求在连接孔和通路孔中通过好的分步覆盖使之填充以形成连接销或通路销。
为了满足这样的要求,R.Fiordalice等提出了一种题为“一种低温CVDAl销和0.25μm金属化相互连接工艺”的方法,发表在1996年VLSI技术年会的论文集第42页。
上述方法以所公布的图被列于附图3(a)~3(c),在此作进一步的描述。
首先,在硅(Si)的半导体基片1上形成一层二氧化硅(SiO2)作为中间层的绝缘膜2,在其上通过保护膜、曝光、腐蚀、剥离保护膜等步骤以露出连接孔3,如附图3(a)所示。为使附图3(a)和(b)简化清晰,在半导体基片1的表面和内部都没有画出元件;实际上在基片1上会形成许多诸如晶体管等元件,而在其上再形成中间层的绝缘膜2。
然后用如溅射等物理气相沉积的方法置备一层钛(Ti)阻挡金属膜(图中未示),在其上用PVD方法置备如图3(b)所示的Al膜(以下称PVD-Al膜4)。这层阻挡膜的作用是为了增加PVD-Al膜4和绝缘膜2之间的厚度,并且阻止在后续的化学气相沉积VCD过程中,由于原材料气体反应引起的相互扩散而造成的连接破坏,其用在化学气相沉积(CVD)中,并与半导体基片1形成下述的连接销6。
接下来用CVD方法在PVD-Al膜4的整个表面上形成一层铝膜(以下称CVD-Al膜5),如图3(c)所示,此时保持设备处于真空状态,CVD-Al膜5就会外延生长在PVD-Al膜4的上面,从而在连接孔3中填满了Al形成了连接销6。
在上述传统的方法中,在形成PVD-Al膜4时,会沉积到连接孔3的开口3(a)的上面,从而减小了连接孔3的尺寸(如图3(b)所示)。这一现象被称为“凸伸”,图中PVD-Al膜4上的相关部分就称为凸伸4a。
当形成CVD-Al膜5的时候,由于这个凸伸4a的存在,在Al完全填满连接孔3之前,连接孔3的开口3a就被CVD-Al膜5所封闭,如附图3(c)所示,这样就会在连接孔3中出现孔隙7。
孔隙7的出现会减小连接销6的横截面积使之增加通过连接销6的电流密度,从而会引起热致电迁移和连线的断开。电迁移是指金属原子沿连线中电子流的方向移动的现象;在移动造成金属原子缺位的地方容易发生断线,而金属原子沉积在邻近其它连线的位置又容易发生短路。
发明内容
对于上述传统方法所存在的问题,本发明的目的是要提供一种制造半导体器件的方法,使铝等金属能够完全地没有任何孔隙地填充满连接孔或通路孔。
本发明的第一点是为达到上述目的而提出的一种制造工艺,用于制造使用通路销经过中间绝缘层来连接上下各层的金属连线的多层半导体器件,其工艺步骤如下:第一步在半导体基片上形成下层金属连线;第二步在基片的整个表面上形成中间绝缘层;第三步用PVD(物理气相沉积)法在中间绝缘层的整个表面上形成第一金属膜(包括Al);第四步腐蚀第一金属膜和中间绝缘层,在要形成通路销的位置开孔,使之暴露出下层金属连线;第五步以一个在第一金属膜的表面上自然形成的氧化物膜作为掩膜,使用选择CVD(化学气相沉积)法在孔中填充金属(包括铝),从而形成通路销;第六步通过腐蚀局部地去除上述自然形成的氧化物膜;第七步使用CVD法在第一金属膜和通路销的整个表面上形成第二金属膜(包括铝)。
本发明的第二点是为达到上述目的也可以使用另一种制造工艺,用于制造使用连接销经过中间绝缘层来连接不同层的金属连线的多层半导体器件,从而使各个分立的构成元件的电极连接起来的多层半导体器件,其工艺步骤如下:第一步在半导体基片上形成下层金属连线;第二步在基片的整个表面上形成中间绝缘层;第三步用PVD(物理气相沉积)法在中间绝缘层的整个表面上形成第一金属膜,包括Al;第四步腐蚀第一金属膜和中间绝缘层,在要形成通路销的位置开孔,使之暴露出下层金属连线;第五步以一个在第一金属膜的表面上自然形成的氧化物膜作为掩膜,使用选择CVD(化学气相沉积)法在孔中填充金属(包括铝),从而形成连接销;第六步通过腐蚀局部地去除上述自然形成的氧化物膜;第七步使用CVD法在第一金属膜和连接销的整个表面上形成第二金属膜(包括铝)。
前面所述的方法中的第一个步骤包括在下层金属连线的至少一个表面上或在电极的至少一个表面上形成一层阻挡金属膜。
上述阻挡金属膜可以是单独的钨或钛膜、钨的氧化物或钛的氧化物膜、或上述膜的叠加膜。
前述方法中的第三个步骤包括在下述设备条件下直流溅射形成1000埃厚的铝膜:基片的温度为100℃,Ar气体的流速为50~300sccm(标准立方厘米每分钟),Ar气的压力为1.333~13.33m帕斯卡,直流功率为5~30kW。
前述方法中的第五个步骤包括用氢气作为输运气体引入设备中使之起泡,其它工艺条件如下:基片的温度为100℃~270℃,设备内的压力为0.1333~13.33帕斯卡,气体的流速为50~2000sccm(标准立方厘米每分钟)。
前述方法中的第七个步骤包括用氢气作为输运气体引入设备中使之起泡,其它工艺条件如下:基片的温度为100℃~300℃,设备内的压力为0.1333~39.99帕斯卡,气体的流速为50~2000sccm(标准立方厘米每分钟)。
前述方法中的第五个步骤所用的原材料气体可以是二甲基铝的氢化物,烷基铝和铝的氢化物中的一种。
前述方法中的第七个步骤所用的原材料气体可以是下述的二甲基铝的氢化物,烷基铝和铝的氢化物中的一种。
前述方法中的第六个步骤包括使用氯化物或三氯化硼中的含氯的气体干法蚀刻去除自然的氧化物膜的过程。
前述方法中的第七个步骤是在上述第六个步骤的同一个CVD设备中保持真空所进行的。
使用上述方法可以将金属(包括铝)没有任何孔隙地填满连接孔或通路孔。
进一步说,由于在第一层PVD金属膜之上形成第二层CVD金属膜,具有好的晶格取向和平面度的第二层金属膜就会外延生长在具有好的晶格取向的第一层金属膜之上。
附图说明
本发明的优点和特点将结合附图作进一步描述。
附图1(a)~1(c)是根据实施例来描述一种半导体器件的制造方法的工艺步骤示意图。
附图2(a)~2(b)是继续附图1(a)~1(c)的后续工艺步骤的示意图。
附图3(a)~3(c)是一种半导体器件的传统制造方法的工艺步骤示意图。
具体实施方式
以下通过实施例和附图,对本发明制造半导体器件的方法的原理作进一步详细的描述。
附图1(a)~1(c),2(a)和2(b)是根据实施例来描述一种半导体器件的制造方法的工艺步骤示意图。
如附图1(a)所示,使用常规的晶体管集成电路的方法在硅(Si)半导体基片11的上面和内部形成各种元件(如图中没有出示的晶体管);在其上,将一层二氧化硅(SiO2)绝缘膜12作为第一中间层形成在半导体基片11的整个表面上;接下来在第一中间绝缘层12的一部分上面相继形成铝(Al)膜13和阻挡金属膜14,它们构成了下层的金属引线;然后在第一中间绝缘层12的剩余部分和下层金属引线的上面,形成作为第二中间层的二氧化硅(SiO2)绝缘膜15。阻挡金属膜14是一种厚度为500埃的氮化钛(TiN)和厚度为300埃的钛(Ti)的叠加的膜。同样,也可以在铝(Al)膜13和第一中间绝缘层12之间制备其它材料的阻挡金属膜。进一步说,铝(Al)膜13和阻挡金属膜14可以用PVD法也可以用CVD法制备。
接下来如附图1(b)所示,在第二中间绝缘层15的上面,使用如直流溅射的PVD方法形成一层1000埃厚的PVD-Al膜16,直流溅射的工艺条件为:基片的温度为100℃,Ar气体的流速为50~300sccm(标准立方厘米每分,即标准状态下的流速),Ar气的压力为1.333~13.33m帕斯卡,直流功率为5~30kW。然后把这个半成品从PVD设备中取出暴露在大气中,从而在PVD-Al膜16的表面上自然氧化形成厚度约为1000埃的氧化铝(Al2O3)膜。
这个氧化铝膜是用传统工艺形成的,因此被称为自然的氧化物膜。在半成品上制成通路孔的光刻胶图形后,用常规的光刻方法腐蚀PVD-Al膜16。然后在第二中间绝缘层15上面腐蚀打开一个通路孔17,从而使作为阻挡金属层的氮化钛膜或钛膜的上表面暴露出来,如附图1(c)所示。
接下来如附图2(a)所示,使用选择性的CVD方法仅在阻挡金属层14的上面形成铝的通路销18。这种选择性CVD所使用的原材料气体是二甲基铝的氢化物(DMAH) (CH3)2AlH,氢气作为运输气体以50~2000sccm的流速加到原材料液体之中并引入到设备里,设备中的工艺条件是基片的温度为100℃~270℃,内部的压力为0.1333~13.33帕斯卡。结果就在分立的通路孔17底部的阻挡金属膜14的上面,形成了没有任何孔隙的通路销18。为什么通路销18会选择性形成,其原因大概是这层氧化铝膜即自然形成的氧化物膜对于选择性生长是惰性的,因此就成为了掩膜。
再下来的工艺是用干法蚀刻去除PVD-Al膜16表面上的氧化铝层,这里使用的气体是如氯气(Cl2)和三氯化硼(BCl3)的氯化物气体,然后继续在同一设备中保持真空,使用CVD法在PVD-Al膜16的整个表面上形成一层CVD-Al膜19,从而使CVD-Al膜19外延生长在PVD-Al膜16的上面。
干法蚀刻的典型方法是反应离子腐蚀(RIE)。在CVD工艺中,将氢气以50~2000sccm的流速通入到液态的原材料二甲基氢化铝之中,所产生的起泡的材料被引入CVD设备中,其它工艺条件为基片的温度是100℃~300℃,内部的压力为0.1333-39.99帕斯卡。
根据上述的制造方法,由于自然形成的氧化物膜对于铝的选择性生长是惰性的,从而起到了掩膜作用,因此就能够在通路孔17底部的阻挡金属膜14的上面形成了没有任何孔隙的通路销18。
对于此实例来说,当使用CVD法在自然形成的氧化物膜被去除后的表面上制备CVD-Al膜19时,由于此时的表面是使用PVD法(特别是溅射法)制备的PVD-Al膜16,其取向沿着好的晶体排列的晶格面,这样在其上外延生长的CVD-Al膜19也会沿着晶格面作为表面取向。结果所形成的CVD-Al膜19就会具有好的晶格排列取向和好的平面度。这是因为即使上层薄膜的生长速率依赖于下层薄膜的晶格取向,在这里也完全有可能生成一层具有好的晶格取向的表面平整的薄膜。
在接下来的工艺步骤中,光刻工艺中可以做到准确的对正。
如前所述,由于PVD-Al膜16和CVD-Al膜19的取向是以晶格面作为排列表面,它们对于电迁移都有阻挡作用。这是因为通常讲,当薄膜是沿着晶格面取向时对于电迁移的阻挡作用是非常大的。
如上所述,使用本发明的制造半导体器件的方法,可以将金属(包括铝)完全地没有任何孔隙地填满连接孔或通路孔。
由于第二层VCD金属膜沉积在第一层PVD金属膜之上,前者就会在具有好的晶格取向的第一层PVD金属膜表面上外延生长出具有好的晶格取向和好的平面度的薄膜来。
作为结果半导体器件的产出和可靠性都会得到提高。
当然,本发明并不完全局限于上述的实施例,可以在不违背本发明的主导思想的前提下作适当的改进和变化。
例如:在本实施例中使用选择CVD法和CVD法形成通路销18和CVD-Al膜19时,所使用的原材料并不局限于二甲基氢化铝,还可以使用烷基铝,如三异丁基铝(C4H9)3Al,也可以使用胺基的铝的氢化物,如(CH3)3NAlH3,(CH3)3NH3AlH3N(CH3)3,(CH3)2(C2H5)NAlH3。
再例如:在本实施例中阻挡金属膜14并不局限于使用氮化钛膜与钛膜的叠加,还可以使用单独的高熔点金属如钨(W)和钛(Ti)及其化合物,也可以选择这些膜的叠加,只要考虑它们的阻抗值或者说对于铝膜的作用程度。
进一步说,本发明并不局限于用来形成通路销18,稍加变化也可以用于形成连接销,同样可以得到相同的结果。
最后,本申请要求一并考虑日本专利申请号No平成9-288292,1997年10月21日,具有优先权。
Claims (20)
1、一种用于制造使用通路销经过中间绝缘层来连接不同层的金属连线的多层半导体器件的工艺方法,其特征在于这种方法有如下工艺步骤:
第一步在半导体基片上形成下层金属连线;
第二步在基片的整个表面上形成中间绝缘层;
第三步用物理气相沉积法在中间绝缘层的整个表面上形成包含铝的第一金属膜;
第四步腐蚀第一金属膜和中间绝缘层,在要形成通路销的位置开孔,使之暴露出下层金属连线;
第五步以在第一金属膜的表面上自然形成的氧化物膜作为掩膜,使用选择化学气相沉积法在孔中填充包含铝的金属,从而形成通路销;
第六步通过腐蚀局部地去除上述自然形成的氧化物膜;
第七步使用化学气相沉积法在第一金属膜和通路销的整个表面上形成包含铝的第二金属膜。
2、如权利要求1所述的方法,其特征还在于该方法中的第一个步骤包括至少在下层金属连线的上表面上形成一层阻挡金属膜。
3、如权利要求2所述的方法,其特征还在于上述阻挡金属膜可以是单独的钨或钛膜、钨的氧化物或钛的氧化物膜、或上述膜的叠加膜。
4、如权利要求1所述的方法,其特征还在于该方法中的第三个步骤包括在下述设备条件下直流溅射形成1000埃厚的铝膜:基片的温度为100℃,Ar气体的流速为50~300sccm,Ar气的压力为1.333~13.33帕斯卡,直流功率为5~30kW。
5、如权利要求1所述的方法,其特征还在于该方法中的第五个步骤包括用氢气作为输运气体引入设备中使之起泡,工艺条件如下:基片的温度为100℃~270℃,设备内的压力为0.1333~13.33×103帕斯卡,气体的流速为50~2000sccm。
6、如权利要求1所述的方法,其特征还在于该方法中的第七个步骤包括用氢气作为输运气体引入设备中使之起泡,工艺条件如下:基片的温度为100℃~300℃,设备内的压力为0.1333~39.99×103帕斯卡,气体的流速为50~2000sccm。
7、如权利要求1所述的方法,其特征还在于该方法中的第五个步骤所用的原材料气体可以是下述的二甲基铝的氢化物,烷基铝和铝的氢化物中的一种。
8、如权利要求1所述的方法,其特征还在于该方法中的第七个步骤所用的原材料气体可以是二甲基铝的氢化物,烷基铝和铝的氢化物中的一种。
9、如权利要求1所述的方法,其特征还在于该方法中的第六个步骤包括使用氯化物或三氯化硼中的含氯的气体干法蚀刻,使之去除自然形成的氧化物膜。
10、如权利要求1所述的方法,其特征还在于该方法中的第七个步骤是在上述第六个步骤的同一个化学气相沉积设备中保持真空所进行的。
11、一种用于制造使用连接销经过中间绝缘层来连接不同层的金属连线的从而使各个分立的构成元件的电极连接起来的多层半导体器件的工艺方法,其特征在于这种方法有如下工艺步骤:
第一步在半导体基片上形成下层金属连线;
第二步在基片的整个表面上形成中间绝缘层;
第三步用物理气相沉积法在中间绝缘层的整个表面上形成包含铝的第一金属膜;
第四步腐蚀第一金属膜和中间绝缘层,在要形成连接销的位置开孔,使之暴露出下层金属连线;
第五步以一个在第一金属膜的表面上自然形成的氧化物膜作为掩膜,使用选择化学气相沉积法在孔中填充包含铝的金属,从而形成连接销;
第六步通过腐蚀局部地去除自然形成的氧化物膜;
第七步使用化学气相沉积法在第一金属膜和连接销的整个表面上形成包含铝的第二金属膜。
12、如权利要求11所述的方法,其特征还在于该方法中的第一个步骤包括至少在下层金属连线的上表面上形成一层阻挡金属膜。
13、如权利要求12所述的方法,其特征还在于上述阻挡金属膜可以是单独的钨或钛膜、钨的氧化物或钛的氧化物膜、或上述膜的叠加膜。
14、如权利要求11所述的方法,其特征还在于该方法中的第三个步骤包括在下述设备条件下直流溅射形成1000埃厚的铝膜:基片的温度为100℃,Ar气体的流速为50~300sccm,Ar气的压力为1.333~13.33帕斯卡,直流功率为5~30kW。
15、如权利要求11所述的方法,其特征还在于该方法中的第五个步骤包括用氢气作为输运气体引入设备中使之起泡,工艺条件如下:基片的温度为100℃~270℃,设备内的压力为0.1333~13.33×103帕斯卡,气体的流速为50~2000sccm。
16、如权利要求11所述的方法,其特征还在于该方法中的第七个步骤包括用氢气作为输运气体引入设备中使之起泡,工艺条件如下:基片的温度为100℃~300℃,设备内的压力为0.1333~39.99×103帕斯卡,气体的流速为50~2000sccm。
17、如权利要求11所述的方法,其特征还在于该方法中的第五个步骤所用的原材料气体可以是二甲基铝的氢化物,烷基铝和铝的氢化物中的一种。
18、如权利要求11所述的方法,其特征还在于该方法中的第七个步骤所用的原材料气体可以是下述的二甲基铝的氢化物,烷基铝和铝的氢化物中的一种。
19、如权利要求11所述的方法,其特征还在于该方法中的第六个步骤包括使用氯化物或三氯化硼中的含氯的气体干法蚀刻,使之去除自然形成的氧化物膜。
20、如权利要求11所述的方法,其特征还在于该方法中的第七个步骤是在上述第六个步骤的同一个化学气相沉积设备中保持真空所进行的。
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KR20020004539A (ko) * | 2000-07-06 | 2002-01-16 | 박종섭 | 수소확산을 방지할 수 있는 강유전체 메모리 소자 제조 방법 |
US6458416B1 (en) * | 2000-07-19 | 2002-10-01 | Micron Technology, Inc. | Deposition methods |
US7192888B1 (en) * | 2000-08-21 | 2007-03-20 | Micron Technology, Inc. | Low selectivity deposition methods |
US7094690B1 (en) | 2000-08-31 | 2006-08-22 | Micron Technology, Inc. | Deposition methods and apparatuses providing surface activation |
US7192827B2 (en) * | 2001-01-05 | 2007-03-20 | Micron Technology, Inc. | Methods of forming capacitor structures |
US7368014B2 (en) * | 2001-08-09 | 2008-05-06 | Micron Technology, Inc. | Variable temperature deposition methods |
KR100798270B1 (ko) * | 2002-07-30 | 2008-01-24 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
CN103165483B (zh) * | 2013-02-20 | 2015-08-19 | 上海华力微电子有限公司 | 一种减少铝衬垫表面缺陷的方法 |
CN103280411A (zh) * | 2013-05-23 | 2013-09-04 | 上海华力微电子有限公司 | 铝衬垫形成方法 |
CN107622974A (zh) * | 2017-08-28 | 2018-01-23 | 武汉华星光电半导体显示技术有限公司 | Tft基板的制作方法及tft显示装置的制作方法 |
Family Cites Families (1)
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US5976970A (en) * | 1996-03-29 | 1999-11-02 | International Business Machines Corporation | Method of making and laterally filling key hole structure for ultra fine pitch conductor lines |
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1997
- 1997-10-21 JP JP9288292A patent/JP3050187B2/ja not_active Expired - Lifetime
-
1998
- 1998-10-20 US US09/175,932 patent/US6083832A/en not_active Expired - Fee Related
- 1998-10-21 CN CN98120670A patent/CN1110083C/zh not_active Expired - Fee Related
- 1998-10-21 KR KR1019980044089A patent/KR100278490B1/ko not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN104733310A (zh) * | 2013-12-18 | 2015-06-24 | 中芯国际集成电路制造(北京)有限公司 | 鳍式场效应管的形成方法 |
CN104733310B (zh) * | 2013-12-18 | 2017-11-03 | 中芯国际集成电路制造(北京)有限公司 | 鳍式场效应管的形成方法 |
Also Published As
Publication number | Publication date |
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KR100278490B1 (ko) | 2001-02-01 |
KR19990037262A (ko) | 1999-05-25 |
JP3050187B2 (ja) | 2000-06-12 |
JPH11121619A (ja) | 1999-04-30 |
US6083832A (en) | 2000-07-04 |
CN1215227A (zh) | 1999-04-28 |
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