TWI247408B - Stable metal structure with tungsten plug - Google Patents

Stable metal structure with tungsten plug Download PDF

Info

Publication number
TWI247408B
TWI247408B TW093134988A TW93134988A TWI247408B TW I247408 B TWI247408 B TW I247408B TW 093134988 A TW093134988 A TW 093134988A TW 93134988 A TW93134988 A TW 93134988A TW I247408 B TWI247408 B TW I247408B
Authority
TW
Taiwan
Prior art keywords
dielectric
integrated circuit
circuit structure
angstroms
manufacturing
Prior art date
Application number
TW093134988A
Other languages
English (en)
Other versions
TW200534458A (en
Inventor
Horng-Huei Tseng
Syun-Ming Jang
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW200534458A publication Critical patent/TW200534458A/zh
Application granted granted Critical
Publication of TWI247408B publication Critical patent/TWI247408B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

1247408 九、發明說明 本申請案主張優先權為2004年4月6日在美國申請之 第60/559,857號臨時申請案，其發明名稱為“具有鎢插塞 之穩定金屬結構”，在此列為本案之參考文獻。 【發明所屬之技術領域】 本發明係有關於一種積體電路結構，特別是有關於一種 積體電路結構之内層介電質（lnter LeVel Dielectric ; ILD)。 【先前技術】 積體電路不斷縮微至深次微米領域，根據摩爾定律之 歷史趨勢’在高效能、高密度之積體電路上的電晶體數量 可同達數千萬。這已迫使上述積體電路以多層高密度金屬 内連線為特徵，而且這些層由内層介電質所分開，其中内 層’丨電質有時亦稱之為内金屬介電質（Inter_Metal Dielectric ; IMD)。與這些金屬内連線相關之寄生電容 (Parasite Coacitance)已經成為限制上述高效能積體電路之 .電路速度的一個主要因子。傳統之内層介電質（亦為熟知的 一般介電常數介電質）一般具有介電常數（亦為熟知的k值） 介於約3.8至約8.0之間。然而，一般介電常數（Regular_k) 介電質在介電值偏高時會導致高寄生電容。近來，低介電 常數（Low-k)介電質，例如化學氣相沉積黑鑽石（應用材料公 司之商標）’其介電常數為約3_〇，已廣泛使用於半導體業， 藉以減少金屬導線間的寄生電容，因而改善電路效能。二 1247408 氧切（其介電常數介於約3.8至約 電常數介電質與一般介電常翁八 叙係用來作低介 然而，由於低介電常之分界線用。 常數材料有相當大的差異，因.广丨生及化性與一般介電 舉例而言，低介電常數材料：：：為第-層介電質。 電麼、對覆蓋層(Cap)與襯裡層二er)=:電流：低崩潰 性低，因此靠近元件處使用低介電溆- ，同時熱穩定 為了解決寄生電容的問題，常 h，會降低其效能。 合結構。靠近元件處之—層係利用由兩層組成之複 成，而遠離元件處之-層則利用低介 :數材枓形 此有效降低寄生電容。不過，卻又 ，成。如 包含-般介電常數介電質之金屬結構中，題用在= 阻障層，例如氮化鈦)作為接觸插：，而較St 數介電質、以及介於較厚之一般介電常數介電質 =之低介電常數介電質之間的黏著就不穩固。這會導 4媒層離（Film Delaminati〇n)並造成晶片良率低落。 【發明内容】 本發明的目的之一就是揭露一種具有鎢插塞之穩定金 屬結構。本發明一較佳實施例係使較厚之一般介電常數介電 :内縮’然後在較厚之一般介電常數介電質與較厚之低介電 常數介電質之間形成較薄之低介電常數介 之-般介電常數介電質與較厚之低介電常數介電質之間的予 黏者。 1247408 上述較薄之低介電常數介電皙故M ± φ ^ _ 电貝改善較厚之一般介電常 數介電質與較厚之低介電常數介雷皙 电為之間的黏著。内縮距離 愈大，杈厚之一般介電常數介電質盘 傲a日日 貝一 #又厚之低介電常數介電 質之間的黏著就愈佳’除了與較厚之 /予 < —般介電常數介雷質接 觸外，内縮更使得較厚之低介電常數八數"電負接 暗μ /τ · 數；丨電質接觸襯裡層/阻 障層（UneiVBarrier)之側壁表面且進一 — 少加強黏著。 在較佳實施例中，較厚之一般介雷 甘^ *^丨電$數介電質係形成於 基材上。鎢插塞係形成於高電常數介電質中。較厚之一般介 電常數介電質係内縮，而較薄之低介電常數介電質則形成於 此較厚之-般介電常數介電質上。前述較薄之低介電常數介 電質作為黏著層以及㈣終止層。較厚之低介電常數介電質 係形成於此較薄之低介電常數介電質上。視情況而定，形成 穿此較厚之·低介電常數介電質以暴露出嫣插塞。然 後’前述開口以銅或銅合金填滿。 【實施方式】 以下係詳細討論製造及使用本發明之較佳實施例。然 而，當了解的是本發明提供許多可應用之發明概念，而這些 考X月概心可具體實施於種種特定内容。所論及之特定實施例 僅以特疋方式說明本發明之製造及使用，並非用以限定本發 明之範圍。 第1圖至第9圖說明本發明之數個較佳實施例。第1 圖說明導電區4以及基材2。在一較佳實施例中，導電區4 可為源極/沒極，而此源極/汲極係以磊晶成長之材料形成於 1247408 基材2所形成之凹陷（Recess)中。在另一實施例中，導電區 4可為源極/汲極，而此源極/汲極係利用習知磊晶技術而磊 晶沉積於基材2上。在其他實施例中，導電區4可為閉極結 構（圖未繪示），其中此閘極係形成於基材2上。 導電區4亦可包括在源極/汲極或複晶矽閘極 P〇iy)上形成金屬石夕化物（Silicide)。金屬矽化物改善下方區 域與後續步驟形成的金屬接觸插塞之間的接觸。當了解的 是，可藉由許多用於積體電路製造的材料而形成導電區4。 舉例而言，導電區4可為金屬導線或複合金屬導線，係用來 連接另-層之積體電路。又，當了解的是，基材2僅為說明 針對導電區4的諸多環境之―。基材2可為♦基材或其他材 料’例如錢（SiGe)、㈣半導體、多層半導體、絕緣層上 矽（s山con-0n_Insulator; s〇I)、絕緣層上石夕錯⑻以⑴）或絕 緣層上鍺（GeOI)。 接下來’如第2圖所示，較厚之一般介電常數内層介電 ^ (Inter Level Dielectric ; ILD)6係沉積於基材2以及導電 :4上。如習知技術所示，内層介電質6隔離元件以及後續 二:形成於上方的金屬導線。在整個本發明較佳實施例之敛 迤'，較厚之一般介電常數内層介電質6亦為第一介電質 6。第-介電質6以一般介電常數介電質為較佳，且第一介 電質6之介電常數作值)係介於約33至約43之間，而以 J .0為更佳。在一較佳實施例中，第一介電質6為磷矽玻 ，（Ph〇sphosilicate Glass ; pSG)，其介電常數為約 * 〇。在 ”他實施例中’第-介電質6為氮化石夕或氧化石夕，可利用例 1247408 如電漿加強式化學氣相沉積（Plasma-Enhanced Chemical Vapor Deposition ; PECVD)、高密度電漿化學氣相沉積（mgh Density Plasma CVD ; HDP)、低壓化學氣相沉積（L〇w Pressure CVD ; LPCVD)、次大氣壓化學氣相沉積 (Sub-Atmosphere CVD ; SACVD)、或其他習知沉積技術進 行沉積。第一介電質6形成之厚度以約2〇〇〇埃至約8〇〇〇 埃為較佳，而以約5000埃為更佳。值得注意的是，由於介 電常數低於約3_8之低介電常數材料之物性及化性明顯不 同於一般介電常數材料，因此，靠近元件之第一介電質6 一般並不使用介電常數低於約3.8之低介電常數材料。舉例 而言’低介電常數材，料一般具有㈣電流高、崩潰電麼低、 對覆蓋層與襯裡層黏著差，同時熱敎性低，因此靠近元件 處使用低介電常數材料會降低其效能。 亦如第3圖所示，光阻8形成於第—介電以上且經圖 ::接著’在第一介電質6内形成開口 ι〇。開口 W之形 2習知技術所熟知。然後，利用光阻剝除製程完全去除光 阻8 0 第4圖5兒明沿者側壁及底部而形成阻障層"（亦為 里層）於接觸開口 10内。阻障層U以由氮化鈦㈤an麵 (蝴ΓΛΝ)形成為較佳。亦可使用其他材料例如氮化組 smrTisiN)i化鈦為有效的阻障層，係用於 以增進鶴插塞對第—介電；質66中:氮化鈦亦可作為黏著層 11係由電浆加強式化學氣相=黏一般而言’阻障層 、化予巩相况積（PECVD)所形成。亦可由
I 1247408 物理氣相沉積（Physical Vapor Deposition ; PVD)所形成。阻 障層11之厚度以介於約5〇埃至約3〇〇埃為較佳，且以介於 100埃至150埃為更佳。 剩餘部分之接觸開口 10係由接觸插塞12填滿，而如第 4圖所不。在較佳實施例中，接觸插塞12之材料係利用化 ，氣相沉積由六氟化鎢（Hexaflu〇ride ; WF6)沉積鎢。在其他 實施例中，接觸開口 1〇可由鋁或其他材料例如銅及銅合金 填滿。形成上述材料之方法已為習知技術所熟知。 * 、第5圖說明第一介電質6為内縮。凹陷丨3以利用化學 機械研磨（Chemical Mechanical Polishing ; CMP)、電漿蝕刻 或/”、、蝕刻進行為較佳。當了解的是内縮之垂1直距離h影響第 、；|電質6與後續形成之低介電常數介電質之間的黏著。由 於車乂大之内縮垂直距離所提供與低介電常數介電質接觸之 表面就愈多，因此内縮之垂直距離愈大，黏著就越佳。此外， ^大之垂直距離會更加提高錨定效應（Anchoring Effect)。凹 陷13之較佳垂直距離h，即由接觸插塞12之頂端至第一介 =質6之上表面，係約1〇〇埃至約1〇〇〇埃之間。較佳者係 ;1於約150埃至約350埃、以及約350埃至約500埃之間， 而更佳者係介於約500埃至約1〇〇〇埃。 第6圖說明較薄之第二介電質18形成於第一介電質6 及接觸插塞12上。第二介電質18為中介層⑽ermediate 係具有較佳黏著力以結合將第一介電質6與第三介 電貝一者’其中第三介電質係形成於第二介電質18上，以 更於改善第一介電質6與第三介電質之間的黏著。第二介電 1247408 質18亦可於後續步驟中作為蝕刻終止層。第二介電質1 8 之厚度以少於約600埃為較佳，藉此減少電容以進一步改善 電阻/電谷延遲時間（RC Delay Time)。介於接觸插塞12之上 表面至第二介電質18之上表面之垂直距離d2(如第6圖所示） 以介於約1〇〇埃至約500埃為較佳。 第二介電質18預設對於低介電常數之第三介電質的黏 著良好’且第二介電質18之介電常數高於第三介電質之介 電常數以作為良好之蝕刻終止層。第二介電質18亦預設其 厚度：>、於約600埃以減少電容而進一步改善電阻/電容延遲 牯間。第二介電質1 8之介電常數以低於約5為較佳。在一 較佳實施例中，至少包含矽及碳之材料，例如介電常數約4 之奴化矽（SiC)或碳摻雜之氧化矽，係用於作為介於磷矽玻 璃（介電常數約4·2)與化學氣相沉積黑鑽石（介電常數約3 〇) 之間的黏著層及蝕刻終止層。 第三介電質20係形成於第二介電質18上，如第7圖之 所不。第二介電質20之厚度以介於約15〇〇埃至約5〇〇〇埃 之間為較佳，且以約2500埃為更佳。在一較，佳實施例中， 第二介電質20為介電常數約3·〇之黑鑽石。在其他實施例 中二亦可使用由旋塗（Spin_0n)法形成之有機低介電常數介 貝例如氫氧矽石厌（SiCOH)，而且亦可使用甲基-倍半氧矽 烧（Methyl-Si心squi〇x_ ;⑽⑺。第三介電質之介電常 :以低於約3.2為較佳。較佳之方法為化學氣相沉積，不過 亦可使用其他已知方法例如旋塗。 在一較佳實施例中，形成開口 22貫穿第三介電質2〇 11 1247408 及第電質18以暴露出接觸插塞12，而如第8圖所示。 η開口 22之形狀為溝渠，其中溝渠中沉積低阻抗 金屬以作為内連線。開口 22以比接觸插塞^ 2寬為較佳，其 較佳寬度w22為小於約130〇埃。開口 22底部以低於第二介 電質1 8之上表面為較佳。条丨 利用至少包含氟之氣體化學進行 電漿Ί虫刻而形成開口 2 2為較佳。 在開口 22中形成阻障層23以避免後續步驟中所形成之 銅擴散。阻障層23以由氮化㈣成者為較佳。 然後’開口 22内填滿導體材料而形成内連線24，如第 9圖之所示。在-較佳實施例中’開口 22内利用電化學電 鍍或化學氣相沉積以填滿低阻抗金屬例如銅或銅合金。在其 他實施例中，開口 22内可埴鈕十加入a J異鋁或鋁合金。銅或銅合金形成 之内連線24以由電化學雷 电％予電鍍或無電電鍍（Electr〇less
Plating)技術形成者為較佳。 上述論及較佳實施例的右各丨杜抛 彳j的有利特徵之一在於藉由内縮第 一介電質，以改善較厚之一船公带a〜人 如；丨電吊數介電質與較厚之低介 電常數介電質之間的黏著。大體^ _ 穴體而s，内縮之垂直距離愈 大，較厚之一般介電常數介雷皙盥t 电買與較厚之低介電常數介電質 之間的黏著就愈佳，所形成之全凰从城^ 1 、 Κ金屬結構就愈穩定。實際内縮 之垂直距離與第一介電質以及篦-人兩供 及第二介電質之厚度有關，熟習 此項技藝者無須過度實驗即可找出冑當的數值。 縱然以上已詳述本發明及I復 月及其優點，在不脫離本發明後附 之申請專利範圍所界定之精神和r 爪作和軏圍内，當可作各種之更
動、替換及潤飾。再者，雖然本發H +發明已如上揭露數個較佳之 12 1247408 製程[機構、製造、物之組成、手段、方法及步驟之實施例， 然其並非用以限定本發明令請書之範圍。任何孰習此技藝 者，在不脫離本發明之精神和範圍内，當可作各種之更動斑 :部’因此後附之申請專利範圍意指包 構、製造、物之組成、手段、方法及步驟等範圍，枝 【圖式簡單說明】 為了更完整了解本發明及其優點， 隨附之圖示，其中： 』多上口兒明書並配合 第1圖至第9圖係繪示根據本發一 劁鉬—丄 孕父佳積體電路結構 1 %之中間階段的剖面圖。 汾、口稱 主要元件符號說明】 2 :基材 6:内層介電質（第一 10 :開口 12 :接觸插塞 18 :第二介電質 22 :開口 24 :内連線 d2 :垂直距離 4 :導電區 介電質）8 :光阻 11 :陴障層 13 :凹陷 20 :第三介電質 2 3 :阻障層 h :垂直距離 W22 :寬度
13

Claims (1)

1247408 十、申請專利範圍
的一垂直距離係介於約100埃（A)至約1〇〇〇埃之間；以及 該第二介電質以及該第 •頂端以及一底端，且其 介電負之该上表面之間 一導電區電性連接於該導體插塞之該底端。 2·如申請專利範圍第1項所述之積體電路結構，更至 少包含一矽基材，其中該第一介電質係形成於該矽基材上。 3·如申請專利範圍第丨項所述之積體電路結構，其中 該導電區至少包含-材料，且該材料係選自於實質上由捧雜 矽、金屬矽化物、矽鍺及上述之組合所組成之一族群。 _ 4.如申清專利範圍第1項所述之積體電路結構，其中 該第一介電質之一介電常數化值）係介於約3 3至約43之 間，且該第三介電質之一介電常數係低於約3.2。 5.如申請專利範圍第4項所述之積體電路結構，其中 1247408 該導體插塞之一寬度少於約13 00埃。 6·如申請專利範圍第1項所述之積體電路結構，其中 在該導體插塞之該頂端與該第一介電質之該上表面之間的 該垂直距離係介於約150埃至約350埃之間。
7.如申請專利範圍第1項所述之積體電路結構，其中 在該導體插塞之該頂端與該第一介電質之該上表面之間的 該垂直距離係介於約350埃至約500埃之間。 8.如申請專利範圍第1項所述之積體電路結構，其中 在該導體插塞之該頂端與該第一介電質之該上表面之間的 該垂直距離係介於約500埃至約1000埃之間。 9. 如申請專利範圍第1項所述之積體電路結構，其中 該第二介電質之一介電常數係小於約5。 10. 如申請專利範圍第1項所述之積體電路結構，其中 該第二介電質之一厚度係小於約600埃。 11. 如申請專利範圍第1項所述之積體電路結構，其中 該第二介電質之一材料至少包含矽或碳或上述二者。 12. 如申請專利範圍第11項所述之積體電路結構，其 15 1247408 形成-導體插塞於該開口中，其中該導體㈣具有―頂 端以及一底端； ' 使4第）1電貝之5亥上表面内縮，其中在該導體插塞之 該頂端與該第-介電質之該上表面之間的一垂直距離係介 於約100埃至約1000埃之間； 形成-第二介電質於該第一介電質以及該導體插塞 上；以及 形成一第三介電質於該第二介電質上。 19·如申明專利範圍第丨8項所述之積體電路結構之製 造方法，其中該導體插塞之一底端電性連接於一導電區，其 中該導電區由一材料所組成，且該材料係選自於實質上由摻 雜矽、金屬矽化物、矽鍺及上述之組合所組成之一族群/ ^ 2〇_如申請專利範圍第18項所述之積體電路結構之製 造方法，其中該第一介電質之一介電常數係介於約3·3至約 4.3之間，且該第三介電質之一介電常數係低於約32。 ^ 2 1 ·如申请專利範圍第1 8項所述之積體電路結構之製 迨方法，其中該開口之一寬度少於約1300埃。 ^ 22·如申明專利範圍第1 8項所述之積體電路結構之製 造方法，其中在該導體插塞之該頂端與該第一介電質之該^ 表面之間的該垂直距離係介於約15〇埃至約35〇埃之間Χ。 17 1247408 止23.如申晴專利範圍第18項所述之積體電路結構之製 造方法，其中在該導體插塞之該頂端與該第一介電質之該上 表面之間的該垂直距離係介於約35〇埃至約5〇〇埃之間。 、24· W請專利範圍帛18㉟所述之積冑電路結構之製 造方法，其中在該導體插塞之該頂端與該第一介電質之爷上 表面之間的該垂直距離係介於約5〇〇埃至約1〇〇〇埃之=。 ：- ' . 5.如申明專利範圍第18項所述之積體電路結構之製 造方法，其中使該第一介電質内縮之方法係選自於由化學機 械研磨（Chennai Meehanieai pQlish ; CMp)、絲刻以及渴 蝕刻組成之一族群。 、26. >申請專利範圍帛項所述之積體電路結構之製 造方法’其中該第二介電質之-介電常數係小於約5。 7 ·如申明專利範圍第1 8項所述之積體電路結構之製 泣方法’其中該第二介電質之一厚度係小於約6〇〇埃。 28.如申明專利範圍第丨8項所述之積體電路結構之製 造方法，其中該第二介電質之—材料至少包切或碳或上述 18 1247408 29·如申請專利範圍第18項所述之積體電路結構之製 造方法，其中在該導體插塞之該頂端與該第二介電質之該上 表面之間的一垂直距離係介於約丨〇〇埃至約5〇〇埃之間。 3〇·如申請專利範圍第18項所述之積體電路結構之製 造方法，其中該第三介電質係經由一旋塗法形成之一有機低 介電常數材料。 一 3 1 ·如申請專利範圍第1 8項所述之積體電路結構之製 造方法，更至少包含形成一内連線於該第一介電質、該第二 介電質以及該第三介電質中，且其中該内連線封閉至少部分 之該導體插塞之該頂端。 3 2 ·如申睛專利範圍第3 1項所述之積體電路結構之製 造方法，其中在形成該内連線之步驟前，更至少包含形成一 阻障層之步驟。 33.如申請專利範圍第3 1項所述之積體電路結構之製 造方法，其中該導體插塞係由鎢形成，且該内連線係由銅或 銅合金形成。 34·如申請專利範圍第3 1項所述之積體電路結構之製 造方法，其中該内連線之一寬度係小於約13〇〇埃。
TW093134988A 2004-04-06 2004-11-15 Stable metal structure with tungsten plug TWI247408B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US55985704P 2004-04-06 2004-04-06
US10/919,875 US7224068B2 (en) 2004-04-06 2004-08-17 Stable metal structure with tungsten plug

Publications (2)

Publication Number Publication Date
TW200534458A TW200534458A (en) 2005-10-16
TWI247408B true TWI247408B (en) 2006-01-11

Family

ID=35059781

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093134988A TWI247408B (en) 2004-04-06 2004-11-15 Stable metal structure with tungsten plug

Country Status (3)

Country Link
US (1) US7224068B2 (zh)
CN (1) CN100378949C (zh)
TW (1) TWI247408B (zh)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6867433B2 (en) * 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US20050012087A1 (en) * 2003-07-15 2005-01-20 Yi-Ming Sheu Self-aligned MOSFET having an oxide region below the channel
US7078742B2 (en) 2003-07-25 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel semiconductor structure and method of fabricating the same
US6936881B2 (en) 2003-07-25 2005-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor that includes high permittivity capacitor dielectric
US7112495B2 (en) 2003-08-15 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
US7071052B2 (en) * 2003-08-18 2006-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Resistor with reduced leakage
US7888201B2 (en) 2003-11-04 2011-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
KR100539257B1 (ko) * 2004-04-07 2005-12-27 삼성전자주식회사 패턴 형성을 위한 반도체 구조 및 패턴 형성 방법
US7170174B2 (en) * 2004-08-24 2007-01-30 Micron Technology, Inc. Contact structure and contact liner process
US9202758B1 (en) * 2005-04-19 2015-12-01 Globalfoundries Inc. Method for manufacturing a contact for a semiconductor component and related structure
US8558278B2 (en) 2007-01-16 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with optimized drive current and method of forming
US7898037B2 (en) * 2007-04-18 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Contact scheme for MOSFETs
US8237201B2 (en) 2007-05-30 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Layout methods of integrated circuits having unit MOS devices
US7943961B2 (en) 2008-03-13 2011-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strain bars in stressed layers of MOS devices
US7863176B2 (en) * 2008-05-13 2011-01-04 Micron Technology, Inc. Low-resistance interconnects and methods of making same
US7808051B2 (en) 2008-09-29 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell without OD space effect in Y-direction
US8193089B2 (en) * 2009-07-13 2012-06-05 Seagate Technology Llc Conductive via plug formation
US8012790B2 (en) * 2009-08-28 2011-09-06 International Business Machines Corporation Chemical mechanical polishing stop layer for fully amorphous phase change memory pore cell
US8283650B2 (en) * 2009-08-28 2012-10-09 International Business Machines Corporation Flat lower bottom electrode for phase change memory cell
US8283202B2 (en) 2009-08-28 2012-10-09 International Business Machines Corporation Single mask adder phase change memory element
US8129268B2 (en) * 2009-11-16 2012-03-06 International Business Machines Corporation Self-aligned lower bottom electrode
US7943420B1 (en) * 2009-11-25 2011-05-17 International Business Machines Corporation Single mask adder phase change memory element
US8088660B1 (en) * 2010-12-15 2012-01-03 Infineon Technologies Austria Ag Method for producing a plug in a semiconductor body
US20130299993A1 (en) * 2012-05-11 2013-11-14 Hsin-Yu Chen Interconnection of semiconductor device and fabrication method thereof
US9627250B2 (en) * 2013-03-12 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for back end of line semiconductor device processing
US9780025B2 (en) 2014-12-30 2017-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure and manufacturing method thereof
TWI578440B (zh) * 2015-07-16 2017-04-11 旺宏電子股份有限公司 導體插塞及其製造方法
US9576903B2 (en) * 2015-07-16 2017-02-21 Macronix International Co., Ltd. Structure with conductive plug and method of forming the same
KR102503941B1 (ko) 2017-12-07 2023-02-24 삼성전자주식회사 반도체 장치
US10943983B2 (en) * 2018-10-29 2021-03-09 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuits having protruding interconnect conductors
KR20210065514A (ko) * 2019-11-27 2021-06-04 삼성전자주식회사 집적 회로 반도체 소자의 상호 접속 구조체

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5470788A (en) * 1994-02-28 1995-11-28 International Business Machines Corporation Method of making self-aligned, lateral diffusion barrier in metal lines to eliminate electromigration
JPH0936228A (ja) * 1995-07-21 1997-02-07 Sony Corp 配線形成方法
JPH0997833A (ja) * 1995-07-22 1997-04-08 Ricoh Co Ltd 半導体装置とその製造方法
JPH09321137A (ja) * 1996-05-24 1997-12-12 Nec Corp 半導体装置およびその製造方法
US6022800A (en) * 1998-04-29 2000-02-08 Worldwide Semiconductor Manufacturing Corporation Method of forming barrier layer for tungsten plugs in interlayer dielectrics
US6593653B2 (en) * 1999-09-30 2003-07-15 Novellus Systems, Inc. Low leakage current silicon carbonitride prepared using methane, ammonia and silane for copper diffusion barrier, etchstop and passivation applications
US6815329B2 (en) * 2000-02-08 2004-11-09 International Business Machines Corporation Multilayer interconnect structure containing air gaps and method for making
US6548901B1 (en) * 2000-06-15 2003-04-15 International Business Machines Corporation Cu/low-k BEOL with nonconcurrent hybrid dielectric interface
JP5036096B2 (ja) * 2000-08-07 2012-09-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6677679B1 (en) * 2001-02-06 2004-01-13 Advanced Micro Devices, Inc. Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers
US6713874B1 (en) * 2001-03-27 2004-03-30 Advanced Micro Devices, Inc. Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-layer dielectrics
US6555467B2 (en) * 2001-09-28 2003-04-29 Sharp Laboratories Of America, Inc. Method of making air gaps copper interconnect
CN1453844A (zh) * 2002-04-23 2003-11-05 旺宏电子股份有限公司 具有间隙的铁电电容
US6917108B2 (en) * 2002-11-14 2005-07-12 International Business Machines Corporation Reliable low-k interconnect structure with hybrid dielectric

Also Published As

Publication number Publication date
CN100378949C (zh) 2008-04-02
TW200534458A (en) 2005-10-16
US20050224986A1 (en) 2005-10-13
US7224068B2 (en) 2007-05-29
CN1681104A (zh) 2005-10-12

Similar Documents

Publication Publication Date Title
TWI247408B (en) Stable metal structure with tungsten plug
US8178437B2 (en) Barrier material and process for Cu interconnect
TWI222170B (en) Interconnect structures containing stress adjustment cap layer
US20210313174A1 (en) Interconnect System with Improved Low-K Dielectrics
CN101847616B (zh) 用于硅通孔的阻挡件
JP4224434B2 (ja) 半導体装置及びその製造方法
TWI228790B (en) Integrated circuit and fabrication method thereof and electrical device
US20060194430A1 (en) Metal interconnect structure and method
JP2001313371A (ja) 金属キャパシタおよびその形成方法
TW200837881A (en) Hybrid interconnect structure for performance improvement and reliability enhancement
CN1591856A (zh) 内联机结构及其制造方法
TW201036109A (en) Method for forming thin film resistor and terminal bond pad simultaneously
JP2002141417A (ja) 並列キャパシタの積層構造と製造方法
TW201013840A (en) Structure and process for conductive contact integration
US10770395B2 (en) Silicon carbide and silicon nitride interconnects
JP2002343859A (ja) 配線間の接続構造及びその製造方法
US6483142B1 (en) Dual damascene structure having capacitors
US6391713B1 (en) Method for forming a dual damascene structure having capacitors
US20090115019A1 (en) Semiconductor device having air gap and method for manufacturing the same
TWI253143B (en) Method for forming metal wiring in semiconductor device
JP2005033164A (ja) 半導体素子の銅配線形成方法
TW201123346A (en) Interconnect structure having air gap and manufacturing method thereof
TWI227047B (en) Tungsten-copper interconnect and method for fabricating the same
KR100973277B1 (ko) 반도체 소자의 금속배선 및 그 형성방법
TW200428530A (en) Semiconductor device and method of fabricating the same