201123346 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種内連線結構及其製作方法’尤指一 種具有空氣間隙（air gap)之内連線結構及其製作方法。 【先前技術】 隨著半導體製程的進步’半導體元件的尺寸與内連線結 構的線宽(line width)也隨之逐漸變小’並使得積體電路 (integrated circuit，1C)的密度不斷地提高。然而，上述線寬 縮小的結果，係造成金屬導線間的線阻值（line resistance， R)與寄生電容(parasitic capacitance，C)變大，繼而導致電阻BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interconnect structure and a method of fabricating the same, and more particularly to an interconnect structure having an air gap and a method of fabricating the same. [Prior Art] With the advancement of the semiconductor process, the size of the semiconductor element and the line width of the interconnect structure are gradually reduced, and the density of the integrated circuit (1C) is continuously increased. . However, as a result of the above-mentioned line width reduction, the line resistance (R) and the parasitic capacitance (C) between the metal wires become large, which in turn causes resistance.
電容延遲效應（resistance-capacitance time delay，RC delay)°RC延遲效應導致ic運算速度減慢、降低IC的效能， 隨著半導體製程的線寬降到0.15微米（micrometer，μιη)以 下，甚至0.13微米以下時，RC延遲效應對IC運作效能的影 響係更為明顯。 由於RC延遲效應可以線阻值與寄生電容的相乘積表 達，因此習知技術改善RC延遲效應的方法係以使用電阻值 較低的金屬材料作為金屬導線降低線阻值；或以降低金屬導 線間的寄生電容為二個主要的方向。而寄生電容值係與介電 層之介電常數呈線性相關，即介電層的介電常數愈低，形成 201123346 於介電層中的寄生電容也就相對的愈低。此外除了降低寄生 電容與RC延遲效應之外，低介電常數介電材料更可降低耗 電量，因此對於超大型積體電路(ultralargescale integration，ULSI)的設計而言，低介電常數介電材料的採用 係可最佳化内連線結構的整體效能。 在習知技術中，一般係以氧化矽（Si〇2)作為介電材料，雖 然氧化矽具有相對較高的介電常數值(3.9〜4·5)，但由於氧化 石夕具有良好的熱穩定性(thermal stability)與化學穩定性 (chemical stability)，並且容易藉由一般的氧化物蝕刻製程形 成具有高深寬比(aspect ratio)的溝渠(trench)與介層洞（via)， 因此仍被廣泛地採用。然而，隨著元件尺寸縮小與Ic密度 增高’傳統的氧化矽材料漸漸地無法滿足目前内連線製程的 需求，因此新的低介電常數材料，如以氧化矽為基礎，添加 鼠石反亂專元素的材料，如含氮碎酸鹽（hydrogen 81以8911丨(^&1^，118(5)(介電常數為2.8〜3.1)、曱基石夕酸鹽 (11^1^131^891^〇\&1^，1^(5)(介電常數為2.6〜2.8)、氟矽 玻璃（fluorosilicate glass，FSG)(介電係數約為 3.5)、 hybrid-organic-siloxane-polymer (HOSP)(介電常數約為 2.5)、其他材料如氣凝膠(aerogel)、聚醯亞胺（p〇iyimide，ρι>、 FLARE™、FPI、PAE-2、PAE-3 或 LOSP 等，在近年來已被 陸續提出並用於内連線製程。這些低介電常數材料雖具有介 於2.5〜3.5之間的低介電常數’仍有熱穩定性與可靠性 201123346 般 (renability)不足等缺點，因此目前尚無法妥善地整合於 1C常用的製程。 除上述材料外，現今更有以空氣㈣作為金屬連線間介電 材料的方法：由於空氣的理想介電常數接近1，因此製作旦 =氣_⑽_的内連線結構’亦為—降低金屬導線間 2電容的有效方法之…此外除了可降低寄生電容，利用 4間隙作為介電材料更具有低導熱等優點，因此目前已有 古夕利用工氣間隙提供金屬連線間絕緣之技術為業界所 7製作金屬連線間空氣間隙的方法莫不脫形成介電材料 步成:該二!材料屬中形成金屬層、與移除該介電材料層而 :成4_4步驟。然而’習知空氣間隙的製作方法除了 ==於複雜難以整合之外，尚有—些可靠度問題，如金 ==軸的支禮，甚至有無法量產等問題。因屬 法。⑴乃纟_作具有空氣間隙之内連線結構之方 【發明内容】 因此’本㈣之—目的係在於提供— 内連線結構及其製作方h 乱間隙之 根據本發明所提供之 氣間隙之内連線6士槿… 係k供一種具有空 構之製作方法，該方法首先提供-基底， 201123346 且該基底上形成有-介電層。隨後於該介電層内形成複數個 金屬層’並於該等金屬層與該介電層上形成—覆蓋層 _0。接下來圖案化該覆蓋層形成複數個間隙開/，暴 出該等金屬層之間的部分該介電層；隨後透過該等間隙開口 移除該介電層，而於該等金屬層之間形成複數個空氣間隙。 最後於該第-覆蓋層表面形成—第二覆蓋層，且該第二覆 層係封閉該等空氣間隙。 根據本發明所提供之申請專利，另提供—種且有* 氣間隙之内連線結構之製作方法，該方法首先提供二基底工， 且該基底包含複數個接觸插塞。隨後於該基底上形成一第一 介電層，於該第-介電層⑽成複數個電性連接於該等接觸 插塞之第-金屬層，並於料第—金騎與該第—介電層上 形成一第-覆蓋層。接下來圖案化該第—覆蓋層，以暴露出 鲁=等第-金屬層之_部分該第—介電層，隨後移除該第一 介電層，於該第一金屬層之間形成複數個第一空氣間隙。最 後於該第一復蓋層表面形成一第二覆蓋層，且該第二復蓋層 係封閉該等第一空氣間隙。 曰 姓根據本發明所提供之申料謂，另提供—種内連線 結構，包含有一定義有至少一焊墊區與一非焊墊區之基底， 以及至少一金屬内連線層。而該金屬内連線層則包含有複數 個設置於該焊墊區與該非焊墊區内之該基底上的金屬内連 201123346 線、複數個設置於該非焊墊區内之該等金屬内連線之間的空 氣間隙、錢髓個設置於料㈣内之料金屬㈣線之 間的第-介電層。該等空氣間隙係電性隔離該非嬋塾區内之 該等金屬内連線；而該等第—介電層係、電性隔離該焊塾區内 之該等金屬内連線。 根據本發明所提供之中請專利範圍，更提供—種内連線 結構’包含有一定義有至少一電路區與一環繞該電路區之晶 粒封環(diesealring)區之基底、以及至少一金屬内連線層。 該金屬内連線層包含有複數個設置於該電路區内之金屬内 連線、複數個設置於該晶粒封環區内之第一介電層、以及複 數個设置於該電路區内之該等金屬内連線之間的空氣間 隙，該等空氣間隙係電性隔離該電路區内之該等金屬内連 線。 綜上所述，本發明所提供之具有空氣間隙之内連線結構 及其製作方法，係為一可與現行半導體製程高度整合之方 法’且藉由在需要承受較大應力之處所設置的介電層所提供 之機械支樓，可在降低金屬内連線之間寄生電容的同時，仍 維持之内連線結構整體之可靠度。 【實施方式】 請參閱第1圖至第9圖，第1圖至第9圖係本發明所提 201123346 供之具有空氣間隙之内連線結構之製作方法之一第一較佳 實施例之示意圖。如第1圖所示’本第一較佳實施例首先提 供一基底100，基底100内係設置有一主動電路102 ’而主 動電路102則如熟習該技藝之人士所知’由複數個金氧半導 體（metal-oxide-semiconductor，MOS)電晶體 104 所構成’且 由複數個淺溝隔離（shallow trench isolation ’ STI) 106提供電 性隔離。基底100亦包含一層間介電（interlayer-dielectric， ILD)層110,且ILD層110内設置有複數個接觸插塞（contact plug) 112。用以電性隔離接觸插塞112的ILD層110通常包 含侧碟石夕玻璃（boro-phospho-silicateglass ’ BPSG)、填石夕玻 璃（phosphor-silicate glass，PSG)或四乙氧基石夕烧 (tetra-ethyl-ortho-silicate ’ TEOS)等介電材料；而接觸插塞 112則與MOS電晶體104的摻雜區域1〇8或閘極電性接觸。 請繼續參閱第1圖。接下來於基底1〇〇上形成一覆蓋層 200與一介電層202，覆蓋層200可包含氮化矽（sinc〇n nitride’ SiN)、碳化矽（silicon carbide，SiC)、氮氧化石夕（siiicon 等；而介電層202係於後續製程中作為一犧牲層，因此可包 含習知常用之氧化矽材料。接下來，進行一微影製程，於介 電層202上形成一圖案化硬遮罩，例如光阻（圖未示）。由 於微影製程之各細部步驟與使用的光阻等硬遮罩材料係為 該技藝中具有通常知識者所熟知，且非本發明之技術特徵， 201123346 故於此不詳加贅述。 請仍然參閱第1圖。接下來，進行一蝕刻製程，透過光 阻蝕刻介電層202，而於介電層202内形成複數個開口，在 本第一較佳實施例中，開口係為單鑲嵌技術之溝渠開口 (trench opening) 206，然不限於此。在形成溝渠開口 206後， 係於溝渠開口 206内先形成一阻障層（barrier layer) 208，阻 障層208可包含氮化鈦(titanium nitride，TiN)、氧化鈦（layer and tantalum，TiO)、氮化组(tantalum nitride，TaN)或氣化鶴 (tungsten nitride，WN)等。阻障層208可防止後續形成的金 屬層之金屬離子擴散進入介電層202中，並且提供介電層 202與金屬材料之間之附著性。 請參閱第2圆。在形成阻障層208之後，係藉由一般金 屬沈積製程於介電層202上形成一填滿溝渠開口 206的金屬 層210’而金屬層210可包含銅、鎢、鋁或上述金屬之合金。 接下來進一步以平坦化製程，如化學機械研磨（chemical mechanical polishing，CMP)方法移除多餘的金屬與阻障層 208 ’而使金屬層210與介電層202形成一約略平坦的表面。 此時，與接觸插塞112電性連接的金屬層210係作為一單鑲 嵌結構之金屬内連線；而介電層202則作為一金屬層間介電 (inter-metal dielectric，IMD)層。隨後’係於介電層 202 上形 成一覆蓋層220，完成金屬内連線層之製作。而覆蓋層220 201123346 亦可包含SiN、SiC、SION或SIOC等。 請參閱第3圖至第6圖，其中第3圖係為本第一較佳實 施例之一上視圖，第4圖為第3圖中沿Α·Α，切線之剖面圖、 第5圖為第3圖中沿Β-Β，切線之剖面圖、第6圖則為第3 圖中沿c-c’切線之剖面圖。接下來，於覆蓋層22〇上形成另 -光阻層（圖未示）’並進行一微影製程圖案化覆蓋層22〇。 如前所述，由於微影製程之各步驟與光阻層之材料皆為該技 術領域中具通常知識者所知，故於此亦不另加贅述。如第3 圖所示，在微影製程後，覆蓋層22()係圖案化而形成複數個 間隙開口 222,用以暴露出金屬層21〇之間的部分介電層2〇2 與金屬層210。為清楚表現間隙開口 222、介電層2〇2與金 屬層210的相對關係，第3圖中被覆蓋 係以虛線表示》在第3圖中，間_ 222係跨 金屬線210 ’而如第3圖所示，暴露出多條金屬線以及 。又置於5玄荨金屬線21 〇之間的介電層202。 清同時參閱第4圖至第6圖。為簡略說明，第5圖中僅 繪不部分基底1〇〇與覆蓋層以上之膜層，然熟習該項技 藝之人士應可根據前述說明與第4圖輕易思及第5圖應有之 完整結構。由第4圖至第6圖可知，間隙開口 222細:成於 任兩條以上的金屬層210之間；另請參考第4圖與第6圖不 同4位之切線所呈現之比較：值得注意的是，間隙開口 222 201123346 之也成並非（全移除兩條相鄰金屬層⑽之間的覆蓋層 22〇’而是於兩條以上相鄰金屬層210之間形成二個以上不 居π的i φ積開口 ’因此間隙開口 222以外的部分仍由覆蓋 曰220元全覆蓋。另外，該等相鄰金屬層，之間的間隙開 _ 222之數里係可根據製程要求調整，而不限於第3圖所給 示者。 曰 明參閱第7圆。在微影製程後，係進行一蝕刻製程，透 過間隙開口 222移除兩相鄰金屬層210之間的介電層202 , 並如止於覆蓋層220，而形成複數個空氣間隙224。上述蝕 刻製程較佳為一不傷及金屬層210與阻障層208的濕蝕刻製 程，但不限於此。另外值得注意的是，在蝕刻製程中係藉 由上述不連續的間隙開口 222將兩條相鄰金屬層21〇之間的 介電層210完全去除。詳細地說，在蝕刻製程中，蝕刻劑係 由兩條相鄰金屬層210之間不連續的間隙開口 222進入並蝕 刻介電層202，使得兩條相鄰金屬層210之間的帶狀(strip) 介電層202被完全移除’而形成空氣間隙224。故此一被触 穿且連通的介電層202，即空氣間隙224，係為一形成於上 述相鄰之二金屬層210之間的長條狀鏤空結構（示於第9 圖）。 請參閱第8圖與第9圖。接下來，於覆蓋層220表面另 形成一覆蓋層230，覆蓋層230係封閉各相鄰金屬層21〇之 201123346 間的空亂間隙224，且亦包含SiN、SiC、SION或SIOC。至 此，係完成具有空氣間隙之内連線結構1〇a之製作。 、社本第較佳實施例所提供之製作具有空氣間隙之内 連、水構的方法，係透過在覆蓋層22〇中形成的間隙開口 22^移除作為犧牲層的介電層加。值得注意的是，如第3 口 ”第圆所不’由於在圖案化覆蓋層22〇時形成的間隙開 • 面積甚小’因此在沈積覆蓋層230以封閉空氣間隙224 可避免覆蓋層230的材料大量進入、並充填空氣間隙224 。=低。口質的縫隙(seam)。因此在形成覆蓋層⑽後，仍 可獲知，1電常數約略等於1的空氣間隙224，用以電性隔 離相鄰的金屬層21〇。 月 > 閱第ίο圖至第圖’第10圖至第13圖係本發明 所提供之具有空氣間隙之内連線結構之製作方法之一第-•較佳實施例之示意圖。請注意本第二較佳實施例主要^示 、種雙鎮嵌製程’但其所教導之方法亦可制於各式金屬内 連線製私。％參閱第1Q圖。本第二較佳實施例所教導之方 法，係提供如第-較佳實施例之基底1〇〇，但不限於此。依 照上，第-較佳實施例所揭露之步驟，係於基底1〇〇上形成 由工氣間隙224提供電性隔離的金屬層21〇，作為内連線結 # i〇b之卜金屬内連線層（M1)。由於上述步驟與元件係同 於第-較佳實施例’故該等相同的元件係沿用第—較佳實施 13 201123346 例之元件符號說明；而相同之步驟亦於此省略不再贅述。接 下來，於覆蓋層23G上依序形成介電層·_停止層 (etch stop layer) 302與另—介電層3〇4。介電層3〇4係於後 續製程中作為-犧牲層，因此其包含一般常用的氧化石夕材 料，介電層綱則不限與介電層304包含相同或不同的材 料。接下來’係於介電層3〇〇與介電層3〇4之内分別形成複 數個開口 3H)與複數個開α 312。在本較佳實施例中，開口 31 〇係作為介層洞開口（via 〇pening);而開口 3 i 2則作為一溝 渠開口。介層洞開口 31〇與溝渠開口 312之製作可概分為先 製作介層洞(via first)或先製作溝渠(trench 等方法，而該 等方法乃為熟習雙鑲嵌製程之人士所知，故於此係不再贅 述。而在形成介層洞開口 310與溝渠開口 312後，係於該等 開口内形成-阻障層314，其可包含TiN、Ti〇、㈣或wn 請參閱第η圖。隨後於阻障層314上形成一填滿介層洞 開口 310與溝渠開口 312金屬層，金屬層可包含銅、鎢、紹 或上述金屬之合金。接下來再藉由—CMp方法移除多餘的 金屬材料與阻障層314等膜層，而使金屬層與介電層304形 成/約略平坦的表面。此時，位於介層洞開口 31()内之金屬 層係作為>_雙鑲嵌結構之介層洞插塞(咖卩㈣32〇 ;而位於 溝渠開口 312内之金屬層則作為該雙鑲嵌結構之金屬内連線 層322。而介電層細、_停止们⑽與介電層綱則作 201123346 為一 IMD層。隨後，係於介電層304上形成一覆蓋層330， 完成第二層金屬内連線層（M2)之製作。而覆蓋層330亦可包 含 SiN、SiC、SION 或 SIOC 等。 請參閱第12圖。接下來進行一微影製程，圖案化覆蓋層 330而形成複數個不連續的小面積間隙開口 332，用以不連 續地暴露出相鄰金屬層322之間部分的介電層304。該微影 製程與第一較佳實施例所揭露之微影製程相同，係將間隙開 口 332形成於兩條相鄰的金屬内連線層322之間；或跨越多 條金屬内連線層322。但間隙開口 332的形成並非完全移除 兩條相鄰金屬内連線層322之間的覆蓋層330，而是於任兩 條相鄰金屬層322之間形成二個以上不連續的小面積開口。 另外，間隙開口 332之數量係可根據製程要求調整。 請參閱第13圖。在微影製程後，係進行一蝕刻製程，如 • 前所述透過不連續的間隙開口 332將兩條相鄰金屬層322之 間的介電層304完全去除，並停止於蝕刻停止層302。上述 蝕刻製程較佳為一不傷及金屬層210與阻障層208的濕蝕刻 製程，但亦不限於此。在蝕刻製程中，兩條相鄰金屬層322 之間的帶狀介電層304係被蝕穿，而形成空氣間隙334。最 後，係於覆蓋層330上再形成一覆蓋層340，其可包含SiN、 SiC、SION或SIOC等，用以封閉空氣間隙334。值得注意 的是，第13圖中兩條相鄰的金屬内連線層322之間的介電 15 201123346 層304係於餘刻製程中移除，因此上述相鄰之二金屬内連線 層;322 =間㈣氣間隙22賴係為一長條狀的社结構， 間隙334之長條狀結構特徵約略與第9圖相同，因 此熟I該項技藝之人士可參酌第9圖而輕易思及。至此，完 成具有空氣間隙334之内連線結構1〇b之製作。孰= 3 = = 士應知金屬内連線層_22之膜層數㈣可 實施例所繪示。 本第幸又佳實_與第：_ 由上述第-較佳實施例與第二較佳實施例可知，本發明 之製作具有空氣間隙之内連線結構的方法，係藉由在 曰220/330中形成間隙開〇 222/332移除作為犧牲層的 介電層202/304。且进从 且由於在圖案化覆蓋層220/330時形成的 間隙開口加⑽面積甚小，因此在沈積覆蓋層2則和以 封閉空氣間隙224/334時，可避免覆蓋層的材料大量進入空 氣間隙224/334而形点供口暂从糾、 ^成低ασ負的縫隙。因此在形成覆蓋層 230/340後’仍可獲得一介電常數約略等於i的空氣間隊 224/334’用以作為相鄰金屬内連線層2·22間—穩定的低 寄生電容隔離結構。此外，由於作為犧牲層的介電層綱 係以習知常用、且易於#由—般的氧化物㈣製程之氧化石夕 材料’因此本發明所提供之方法更可高度整合於現有之單鐵 嵌結構製程或雙鑲嵌結構製程。 201123346 此外，根據本發明所提供之方法，空氣間隙224/334係形 成於間距較小的金屬内連線層210/322間，以降低寄生電 容。接觸洞插塞320則仍由包含習知低介電常數的介電層 300提供電性隔離，而介電層300、覆蓋層200/302、覆蓋層 220/340亦用以提供一機械強度(mechanical strength)，支樓 内連線結構10a/10b。 • 接下來請參閱第14圖，第14圖係為本發明所提供之一 内連線結構之第三較佳實施例之之剖面示意圖。如第14圖 所示’本第三較佳實施例所提供之内連線結構l〇c包含一基 底500 ’基底500包含一主動電路、複數個與主動電路電性 連接之接觸插塞、以及一提供接觸插塞電性隔離之ILD層。 上述膜層與元件係同於第一較佳實施例與第二較佳實施例 所述者’故熟習該技藝之人士係可參閱前述說明及圖式輕易 得知。值得注意的是，基底500係定義有至少一焊墊區510 ®與一非焊塾區520。 内連線結構l〇c包含至少一金屬内連線層]、 M2......Mn-1、Mn，而各金屬内連線層Μι、M2......Mn.! ' Μη 更包含複數個分別設置於焊墊區510與非焊墊區512内之基 底500上的金屬内連線512、522，與複數個分別設置於焊墊 區510與非辉墊區512内之基底500上的介層洞插塞514、 524 °在最上層金屬内連線層Mn上，則設置有一轉接焊墊 17 201123346 550。值得注意的是，金屬内連線層μ、％…·Mn i、Mn亦 包3複數個工氣間隙54〇，設置於非焊塾區52〇a的金屬内 連線522之間，用以電性隔離非焊塾區520内之各金屬内連 線5 22 °㈣間隙5 4 G係根據上述第-較佳實施例或第二較 佳實施例賴露之方法所形成。更重要的是，本較佳實施例 所提供之金4内連線層％、M2·.·._Mn,>Mn 層530 °又置於烊墊區510内的金屬内連線512之間，電性 1¾離焊塾(1 51〇内之各金屬内連線512以及各介層洞插塞 514 、 524 。 簡單地說|第二較佳實施例所提供之内連線結構W 中凡是》又置於焊墊㊣51〇内之金屬内連線512冑由介電層 530電f4隔離’而在非焊塾區52()内之金屬内連線皆由 根據前述第-較佳實施例與第二較佳實施例所形成之空氣 間隙540提供電性隔離。由於焊墊區51〇在後續進行打線焊 接(bonding)時，必需承受在轉接焊墊55〇上所施加的機械應 力（mechanical stress)’因此在焊墊區51〇内係藉由介電層53〇 提供足夠的機械強度，以支撐内連線結構1〇c，避免IC受到 機械應力而損壞。而在非焊墊區52〇内則藉由空氣間隙54〇 的a又置降低RC延遲效應。此外在介電層53〇可提供足夠支 撐的刖提下，本第二較佳實施例所提供之内連線結構1〇c甚 至可為焊塾a又於主動電路正上方（bonding over active circuit，BOAC)之内連線結構，以使轉接焊墊正下方的晶片 201123346 區域得以佈設主動電路或特定元件，俾使晶片體積得以進一 步縮小。 接下來請參閱第15圖，第15圖係為本發明所提供之一 内連線結構之第四較佳實施例之剖面示意圖。如第15圖所 示，本第四較佳實施例所提供之内連線結構1〇d包含一基底 600，基底600包含一主動電路、複數個與主動電路電性連 鲁接之接觸插塞、以及一提供接觸插塞電性隔離之ILE)層。上 述膜層與元件亦同於第一較佳實施例與第二較佳實施例所 述者，故於此不再贅述。值得注意的是，基底6〇〇係定義有 至少一晶粒封環區610與一電路區620，且晶粒封環區61〇 係環繞電路區620。 内連線結構10d更包含至少一金屬内連線層、 M2......Μη_ι、Mn，而各金屬内連線層Μι、m2......、Mn 籲更包含複數個分別設置於晶粒封環區610與電路區620内之 基底600上的金屬内連線612、622,與複數個分別設置於晶 粒封環區610與電路區620内之基底600上的介層洞插塞 614、624。值付注意的是，晶粒封環區61 〇内的金屬内連線 612與介層洞插塞614係可作為一晶粒封環65〇或裂縫(crack) 阻擋結構。晶粒封環650之設置係可避免在晶圓切割時或者 晶圓切割時，在低介電常數的介電材料之間的界面形成界面 脫層（interface delamination)現象或者晶片裂縫(chip cracking) 201123346 影響到1C晶片的可靠度。金屬内連線層Μι、M2......Μη.ι、Resistivity-capacitance time delay (RC delay) ° RC delay effect causes the ic operation speed to slow down and reduce the performance of the IC. As the line width of the semiconductor process falls below 0.15 micron (micrometer, μιη), even 0.13 micron. In the following, the effect of the RC delay effect on the operational efficiency of the IC is more pronounced. Since the RC delay effect can be expressed by the product of the line resistance and the parasitic capacitance, the conventional technique for improving the RC delay effect is to use a metal material having a lower resistance value as a metal wire to lower the line resistance; or to lower the metal wire. The parasitic capacitance between them is in two main directions. The parasitic capacitance value is linearly related to the dielectric constant of the dielectric layer, that is, the lower the dielectric constant of the dielectric layer, the lower the parasitic capacitance formed in the dielectric layer of 201123346. In addition to reducing parasitic capacitance and RC delay effects, low-k dielectric materials can reduce power consumption, so for ultra-large integrated integration (ULSI) designs, low-k dielectrics The use of materials optimizes the overall performance of the interconnect structure. In the prior art, yttrium oxide (Si〇2) is generally used as a dielectric material, and although yttrium oxide has a relatively high dielectric constant value (3.9 to 4. 5), it has good heat due to oxidized oxidized stone. Thermal stability and chemical stability, and it is easy to form trenches and vias with high aspect ratio by a general oxide etching process, so Widely adopted. However, as component size shrinks and Ic density increases, 'conventional yttria materials are gradually unable to meet the needs of current interconnect processes, so new low dielectric constant materials, such as yttrium oxide, add rat stone rebellion. Special element materials, such as nitrogen-containing sulphate (hydrogen 81 to 8911 丨 (^ & 1 ^, 118 (5) (dielectric constant 2.8 ~ 3.1), thiol oxalate (11 ^ 1 ^ 131 ^ 891^〇\&1^,1^(5) (dielectric constant 2.6~2.8), fluorosilicate glass (FSG) (dielectric coefficient: about 3.5), hybrid-organic-siloxane-polymer ( HOSP) (dielectric constant is about 2.5), other materials such as aerogel, polyimine (p〇iyimide, ρι >, FLARETM, FPI, PAE-2, PAE-3 or LOSP, etc. In recent years, it has been proposed and used in the interconnect process. These low dielectric constant materials have a low dielectric constant between 2.5 and 3.5. There are still shortcomings such as thermal stability and reliability of 201123346. Therefore, it is not yet properly integrated into the common process of 1C. In addition to the above materials, air (4) is now used as a metal connection. Inter-dielectric material method: Since the ideal dielectric constant of air is close to 1, the fabrication of the interconnect structure of denier_gas_(10)_ is also an effective method for reducing the 2-capacitance between metal wires... in addition to reducing parasitics Capacitor, using 4 gaps as a dielectric material has the advantages of low thermal conductivity. Therefore, there is a technology for providing insulation between metal wires in the industry using the gap of the working gas gap. The dielectric material is stepped into: the second material is formed in the metal layer, and the dielectric material layer is removed: 4 to 4 steps. However, the conventional air gap is produced in addition to the == complex and difficult to integrate, There are some reliability problems, such as the support of the gold == axis, and even the problem of mass production. Because of the law. (1) Nai _ as the inner connection structure with air gap [invention] So (d) - the purpose is to provide - the interconnection structure and the manufacturer of the gap between the gaps provided by the present invention, the inner gap of the gap 6 槿 供 k for a method of manufacturing a hollow structure, the method first mention a substrate, 201123346, and a dielectric layer is formed on the substrate. Then a plurality of metal layers are formed in the dielectric layer and a cladding layer _0 is formed on the metal layers and the dielectric layer. Forming a plurality of gap openings/, exposing a portion of the dielectric layer between the metal layers; subsequently removing the dielectric layer through the gap openings, and forming a plurality of layers between the metal layers An air gap is formed. Finally, a second cover layer is formed on the surface of the first cover layer, and the second cover layer closes the air gaps. According to the patent application provided by the present invention, there is further provided a method of fabricating an interconnect structure having a gas gap, the method first providing a second substrate, and the substrate comprises a plurality of contact plugs. Forming a first dielectric layer on the substrate, wherein the first dielectric layer (10) is electrically connected to the first metal layer of the contact plugs, and is in the first place - the golden ride and the first A first cap layer is formed on the dielectric layer. Next, the first cap layer is patterned to expose a portion of the first dielectric layer of the Ru-e-metal layer, and then the first dielectric layer is removed, and a plurality of layers are formed between the first metal layers First air gap. A second cover layer is formed on the surface of the first cover layer, and the second cover layer closes the first air gaps. According to the application of the present invention, there is provided an interconnect structure comprising a substrate defining at least one pad region and a non-pad region, and at least one metal interconnect layer. The metal interconnect layer includes a plurality of metal interconnects 201123346 lines disposed on the substrate in the pad region and the non-pad region, and a plurality of the metal interconnects disposed in the non-pad region. The air gap between the wires and the first dielectric layer between the wires of the metal (four) wires disposed in the material (4). The air gaps electrically isolate the metal interconnects in the non-defective region; and the first dielectric layers electrically isolate the metal interconnects within the solder fillet region. According to the scope of the invention as claimed in the present invention, an interconnect structure includes a substrate defining at least one circuit region and a dieding ring region surrounding the circuit region, and at least one metal Inner wiring layer. The metal interconnect layer includes a plurality of metal interconnects disposed in the circuit region, a plurality of first dielectric layers disposed in the die seal region, and a plurality of disposed in the circuit region An air gap between the metal interconnects that electrically isolates the metal interconnects within the circuit region. In summary, the present invention provides an interconnect structure having an air gap and a method of fabricating the same, which is a method that can be highly integrated with current semiconductor processes and is provided by where it is required to withstand large stresses. The mechanical support provided by the electrical layer can reduce the parasitic capacitance between the metal interconnects while maintaining the overall reliability of the interconnect structure. [Embodiment] Please refer to FIG. 1 to FIG. 9 , and FIG. 1 to FIG. 9 are schematic diagrams showing a first preferred embodiment of a method for fabricating an interconnect structure having an air gap according to the present invention. . As shown in Fig. 1, the first preferred embodiment first provides a substrate 100 having an active circuit 102' disposed therein, and the active circuit 102 is known to those skilled in the art from a plurality of MOS semiconductors. The metal-oxide-semiconductor (MOS) transistor 104 constitutes 'and is electrically isolated by a plurality of shallow trench isolation 'STI' 106. The substrate 100 also includes an interlayer-dielectric (ILD) layer 110, and a plurality of contact plugs 112 are disposed in the ILD layer 110. The ILD layer 110 for electrically isolating the contact plugs 112 typically comprises a boro-phospho-silicate glass 'BPSG, a phosphor-silicate glass (PSG) or a tetraethoxy zebra ( A dielectric material such as tetra-ethyl-ortho-silicate 'TEOS); and the contact plug 112 is in electrical contact with the doped region 1〇8 or the gate of the MOS transistor 104. Please continue to see Figure 1. Next, a capping layer 200 and a dielectric layer 202 are formed on the substrate 1 , and the capping layer 200 may include sinc〇n nitride'SiN, silicon carbide (SiC), and nitrogen oxynitride. (siiicon, etc.; and the dielectric layer 202 is used as a sacrificial layer in a subsequent process, and thus may comprise a conventionally used ruthenium oxide material. Next, a lithography process is performed to form a patterned hard layer on the dielectric layer 202. a mask, such as a photoresist (not shown). The hard mask materials such as the various steps of the lithography process and the photoresist used are well known to those of ordinary skill in the art and are not technical features of the present invention. 201123346 is not described here in detail. Please refer to Fig. 1. Next, an etching process is performed to etch the dielectric layer 202 through the photoresist to form a plurality of openings in the dielectric layer 202. In the embodiment, the opening is a trench opening 206 of a single damascene technique, but is not limited thereto. After the trench opening 206 is formed, a barrier layer 208 is formed in the trench opening 206. Barrier layer 208 can include Titanium nitride (TiN), layer and tantalum (TiO), tantalum nitride (TaN) or tungsten nitride (WN), etc. The barrier layer 208 prevents subsequent formation. The metal ions of the metal layer diffuse into the dielectric layer 202 and provide adhesion between the dielectric layer 202 and the metal material. Please refer to the second circle. After forming the barrier layer 208, the general metal deposition process is performed. A metal layer 210' filling the trench opening 206 is formed on the dielectric layer 202. The metal layer 210 may comprise copper, tungsten, aluminum or an alloy of the above metals. Further, a planarization process such as chemical mechanical polishing is performed. The CMP) method removes the excess metal and barrier layer 208' to form the metal layer 210 and the dielectric layer 202 to form an approximately flat surface. At this time, the metal layer 210 electrically connected to the contact plug 112 serves as a The metal interconnection of the single damascene structure; and the dielectric layer 202 acts as an inter-metal dielectric (IMD) layer. Subsequently, a cladding layer 220 is formed on the dielectric layer 202 to complete the metal interconnection. line The cover layer 220 201123346 may also include SiN, SiC, SION or SIOC, etc. Please refer to FIG. 3 to FIG. 6 , wherein FIG. 3 is a top view of the first preferred embodiment, the fourth view The figure is the cross-sectional view of the tangent line along the Α·Α in Fig. 3, the cross-sectional view of the tangent line along the Β-Β in the third figure, and the cross-sectional view of the tangent line in the third figure, and the sixth figure is the tangent line along the c-c' in the third figure. Sectional view. Next, a further photoresist layer (not shown) is formed on the cap layer 22 and a lithography process patterned cap layer 22 is formed. As described above, since the steps of the lithography process and the materials of the photoresist layer are known to those of ordinary skill in the art, no further details are provided herein. As shown in FIG. 3, after the lithography process, the cap layer 22() is patterned to form a plurality of gap openings 222 for exposing a portion of the dielectric layer 2〇2 and the metal layer between the metal layers 21〇. 210. In order to clearly show the relative relationship between the gap opening 222, the dielectric layer 2〇2 and the metal layer 210, the coverage in FIG. 3 is indicated by a broken line. In FIG. 3, the inter- 222 is a cross-metal line 210'. As shown in Figure 3, multiple wires are exposed as well. Also placed in the dielectric layer 202 between the 5 Xuanqi metal wires 21 〇. See also Figures 4 through 6 at the same time. For the sake of brevity, only the part of the substrate 1〇〇 and the film above the cover layer are drawn in Figure 5, but those skilled in the art should be able to follow the above description and Figure 4 to easily consider the completeness of Figure 5. structure. 4 to 6 shows that the gap opening 222 is thin: between any two or more metal layers 210; please also refer to the comparison of the four different tangent lines in Fig. 4 and Fig. 6: The gap opening 222 201123346 is also not (completely removing the cover layer 22 〇 between two adjacent metal layers (10), but forming two or more π between two or more adjacent metal layers 210. The i φ product opening 'so the portion other than the gap opening 222 is still covered by the covering 曰 220 yuan. In addition, the gap between the adjacent metal layers, _ 222 can be adjusted according to the process requirements, and not It is limited to the one given in Fig. 3. Referring to the seventh circle, after the lithography process, an etching process is performed to remove the dielectric layer 202 between the two adjacent metal layers 210 through the gap opening 222, and The sealing layer 220 is formed to form a plurality of air gaps 224. The etching process is preferably a wet etching process that does not damage the metal layer 210 and the barrier layer 208, but is not limited thereto. In the process, two of the discontinuous gap openings 222 are used to The dielectric layer 210 between the adjacent metal layers 21 is completely removed. In detail, in the etching process, the etchant enters and etches the dielectric layer from the discontinuous gap opening 222 between the two adjacent metal layers 210. 202, such that the strip dielectric layer 202 between two adjacent metal layers 210 is completely removed' to form an air gap 224. Thus, the dielectric layer 202 that is penetrated and connected, that is, the air gap 224 Is a long hollow structure formed between the adjacent two metal layers 210 (shown in Fig. 9). Please refer to Fig. 8 and Fig. 9. Next, another surface is formed on the surface of the cover layer 220. A cover layer 230, the cover layer 230 is used to close the air gap 224 between the adjacent metal layers 21, 201123346, and also includes SiN, SiC, SION or SIOC. Up to now, the inner wiring structure with air gap is completed. Manufacture of 〇a. The method of fabricating an interconnected, water-structured air gap provided by the preferred embodiment of the present invention removes the intervening layer as a sacrificial layer through a gap opening 22^ formed in the cover layer 22〇. Electric layer plus. It is worth noting that, as for the third Since the gap opening area formed when patterning the cover layer 22 is very small, the deposition of the cover layer 230 to close the air gap 224 can prevent the material of the cover layer 230 from entering a large amount and filling the air gap 224. = Low. Therefore, after the formation of the cover layer (10), it is still known that an air gap 224 having an electrical constant of approximately equal to 1 is used to electrically isolate the adjacent metal layer 21〇. Month> FIG. 10 to FIG. 13 are schematic views of a preferred embodiment of a method for fabricating an interconnect structure having an air gap according to the present invention. Please note that the second preferred embodiment is mainly for the purpose of a double-well process, but the method taught therein can also be made in various metal interconnections. % See Figure 1Q. The method taught by the second preferred embodiment provides the substrate 1 of the first preferred embodiment, but is not limited thereto. According to the steps disclosed in the above-mentioned preferred embodiment, a metal layer 21 is provided on the substrate 1 to provide electrical isolation by the gas gap 224, as an internal connection of the metal junction # i〇b Connection layer (M1). Since the above steps and components are the same as those of the first preferred embodiment, the same components are described with reference to the components of the first preferred embodiment 13 201123346; the same steps are omitted here. Next, a dielectric layer _ stop stop layer 302 and another dielectric layer 3 〇 4 are sequentially formed on the cap layer 23G. The dielectric layer 3〇4 is used as a sacrificial layer in the subsequent process, and thus it contains a commonly used oxide oxide material, and the dielectric layer is not limited to the same or different materials as the dielectric layer 304. Next, a plurality of openings 3H) and a plurality of openings α 312 are formed in the dielectric layer 3A and the dielectric layer 3〇4, respectively. In the preferred embodiment, the opening 31 is used as a via opening; and the opening 3 i 2 serves as a trench opening. The fabrication of the via opening 31〇 and the trench opening 312 can be broadly divided into a first via or a trench, and the methods are known to those skilled in the dual damascene process. No further details are provided herein. After the via opening 310 and the trench opening 312 are formed, a barrier layer 314 is formed in the openings, which may include TiN, Ti〇, (4) or wn. Then, a metal layer filling the via opening 310 and the trench opening 312 is formed on the barrier layer 314, and the metal layer may comprise an alloy of copper, tungsten, or the above metal. Then the CMp method is used to remove the excess layer. The metal material and the barrier layer 314 and the like form a metal layer and the dielectric layer 304 to form a surface which is approximately flat. At this time, the metal layer located in the via opening 31 () acts as a > The dielectric via plug of the structure (Curry (4) 32 〇; and the metal layer located in the trench opening 312 serves as the metal interconnect layer 322 of the dual damascene structure. The dielectric layer is fine, _ stop (10) and dielectric layer The outline is 201123346 as an IMD layer. Subsequently, a layer is formed on the dielectric layer 304. The cover layer 330 completes the fabrication of the second metal interconnect layer (M2), and the cover layer 330 may also include SiN, SiC, SION or SIOC, etc. Please refer to Fig. 12. Next, a lithography process, pattern The cover layer 330 is formed to form a plurality of discontinuous small-area gap openings 332 for discontinuously exposing portions of the dielectric layer 304 between the adjacent metal layers 322. The lithography process is the same as the first preferred embodiment. The disclosed lithography process is the same, forming a gap opening 332 between two adjacent metal interconnect layers 322; or spanning a plurality of metal interconnect layers 322. However, the gap opening 332 is not completely removed. The cover layer 330 between the adjacent metal interconnect layers 322 forms two or more discontinuous small-area openings between any two adjacent metal layers 322. In addition, the number of gap openings 332 can be The process requirements are adjusted. Please refer to Fig. 13. After the lithography process, an etching process is performed, as described above, through the discontinuous gap opening 332 to completely separate the dielectric layer 304 between the two adjacent metal layers 322. Remove and stop at the etch stop 302. The etching process is preferably a wet etching process that does not damage the metal layer 210 and the barrier layer 208, but is not limited thereto. In the etching process, the strip dielectric between two adjacent metal layers 322 The layer 304 is etched through to form an air gap 334. Finally, a cover layer 340 is formed on the cover layer 330, which may include SiN, SiC, SION or SIOC, etc., to close the air gap 334. Yes, the dielectric 15 between the two adjacent metal interconnect layers 322 in Figure 13 is removed from the process of the engraving process, so the adjacent two metal interconnect layers; 322 = (4) The air gap 22 is a long strip of social structure. The long strip structure of the gap 334 is about the same as that of the figure 9. Therefore, those skilled in the art can easily think about it according to Fig. 9. Thus, the production of the interconnect structure 1b having the air gap 334 is completed.孰 = 3 = = The number of layers of the metal interconnect layer _22 (4) should be as shown in the examples. The present invention is based on the above-described preferred embodiment and the second preferred embodiment. The method for fabricating an interconnect structure having an air gap according to the present invention is at 曰220/ A gap opening 222/332 is formed in 330 to remove the dielectric layer 202/304 as a sacrificial layer. Moreover, since the gap opening plus (10) area formed when patterning the cover layer 220/330 is very small, when the cover layer 2 is deposited and the air gap 224/334 is closed, the material of the cover layer can be prevented from entering the air in a large amount. The gap 224/334 and the shape point of the mouth temporarily correct, ^ into a gap of low ασ negative. Therefore, after forming the cap layer 230/340, it is still possible to obtain an air inter-team 224/334' having a dielectric constant approximately equal to i as a stable low-parasitic capacitance isolation structure between adjacent metal interconnect layers 2·22. . In addition, since the dielectric layer as a sacrificial layer is a conventionally used and easy to use oxide oxide process of the oxide (four) process, the method provided by the present invention can be highly integrated into the existing single iron. Embedded process or dual damascene process. In addition, in accordance with the method provided by the present invention, air gaps 224/334 are formed between the metal interconnect layers 210/322 having a smaller pitch to reduce parasitic capacitance. The contact plug 320 is still electrically isolated by a dielectric layer 300 comprising a conventional low dielectric constant, and the dielectric layer 300, the cover layer 200/302, and the cover layer 220/340 are also used to provide a mechanical strength ( Mechanical strength), the connection structure 10a/10b in the branch building. • Referring now to Figure 14, there is shown a cross-sectional view of a third preferred embodiment of the interconnect structure of the present invention. As shown in FIG. 14 , the internal wiring structure 10c of the third preferred embodiment includes a substrate 500. The substrate 500 includes an active circuit, a plurality of contact plugs electrically connected to the active circuit, and An ILD layer that provides electrical isolation of the contact plug. The above-mentioned layers and components are similar to those of the first preferred embodiment and the second preferred embodiment, and those skilled in the art can easily refer to the foregoing description and drawings. It should be noted that the substrate 500 defines at least one pad region 510 ® and a non-weld pad region 520 . The interconnect structure l〇c includes at least one metal interconnect layer], M2...Mn-1, Mn, and each metal interconnect layer Μι, M2...Mn.! ' Μη further includes a plurality of metal interconnects 512, 522 respectively disposed on the substrate 500 in the pad region 510 and the non-pad region 512, and a plurality of metal interconnects 512 and 522 respectively disposed in the pad region 510 and the non-bush region 512. A via plug 514, 524 ° on the substrate 500 is disposed on the uppermost metal interconnect layer Mn, and an via pad 17 201123346 550 is disposed. It is worth noting that the metal interconnect layer μ, %...Mn, Mn also includes a plurality of work gaps 54〇, disposed between the metal interconnects 522 of the non-welded regions 52〇a, for Each of the metal interconnects in the electrically isolated non-weld pad region 520 is formed by a method according to the above-described first preferred embodiment or second preferred embodiment. More importantly, the gold 4 interconnect layer %, M2·.·._Mn, > Mn layer 530 ° provided in the preferred embodiment is again placed between the metal interconnects 512 in the pad region 510. , electrically conductive 塾 (each metal interconnect 512 within 1 51 以及 and each of the via plugs 514, 524. Simply put | the second preferred embodiment provides the interconnect structure W The metal interconnect 512, which is placed in the positive 51〇 of the pad, is electrically isolated by the dielectric layer 530, and the metal interconnects in the non-welded region 52() are all according to the above-described preferred embodiment. The air gap 540 formed by the example and the second preferred embodiment provides electrical isolation. Since the pad region 51 is subjected to subsequent bonding, it must withstand the mechanical stress applied on the adapter pad 55A. (Mechanical stress) 'Therefore, in the pad region 51, the dielectric layer 53 is provided with sufficient mechanical strength to support the interconnect structure 1〇c to prevent the IC from being damaged by mechanical stress. In the region 52, the RC delay effect is reduced by the a-space of the air gap 54. In addition, the dielectric layer 53 provides sufficient support for the RC delay. The interconnect structure 1〇c provided by the second preferred embodiment may even be a soldering a and a bonding over active circuit (BOAC) within the wiring structure, so that the adapter pads are positive. The underlying wafer 201123346 area can be arranged with active circuits or specific components to further reduce the volume of the wafer. Next, please refer to Fig. 15, which is a fourth preferred embodiment of the interconnect structure provided by the present invention. As shown in FIG. 15, the interconnect structure 1〇d provided in the fourth preferred embodiment includes a substrate 600. The substrate 600 includes an active circuit, and a plurality of active circuits are electrically connected. The contact plug is connected, and an ILE) layer is provided for electrically isolating the contact plug. The above-mentioned film layers and components are also the same as those of the first preferred embodiment and the second preferred embodiment, and thus will not be described again. It should be noted that the substrate 6 is defined by at least one die seal region 610 and a circuit region 620, and the die seal region 61 is surrounded by the circuit region 620. The interconnect structure 10d further includes at least one metal interconnect layer, M2...Μη_ι, Mn, and each metal interconnect layer Μι, m2, ..., Mn has a plurality of separate Metal interconnects 612, 622 disposed on substrate 600 in die ring region 610 and circuit region 620, and a plurality of vias disposed on substrate 600 in die ring region 610 and circuit region 620, respectively. Hole plugs 614, 624. It is noted that the metal interconnects 612 and via plugs 614 within the die seal region 61 can serve as a die seal 65 or a crack barrier. The die seal ring 650 is configured to avoid interface delamination or chip cracking at the interface between low dielectric constant dielectric materials during wafer dicing or wafer dicing. 201123346 affects the reliability of 1C wafers. Metal interconnect layer Μι, M2...Μη.ι,
Mn亦包含複數個空氣間隙640 ’設置於電路區620内之金屬 内連線622之間，用以電性隔離電路區620内之各金屬内連 線622。更重要的是，本較佳實施例所提供之金屬内連線層 Μ!、M2......My、Mn更包含一介電層630，設置於電路區 620内之介層洞插塞624之間，電性隔離電路區620内之介 層洞插塞624，此外，介電層630更設置於晶粒封環區610 内，且環繞晶粒封環區610。 簡單地說，本第四較佳實施例所提供之内連線結構10d 中，電路區620内之金屬内連線622係由根據前述第一較佳 實施例與第二較佳實施例所形成之空氣間隙640提供電性隔 離，故可降低其寄生電容。而介電層630係設置於晶粒封環 區610内，以及電路區620内的介層涧插塞622之間以提供 電性隔離。由於晶粒封環區610在1C製程完成之後所進行 的切割製程中必需承受機械式切割所產生的應力，因此在晶 粒封環區610内係藉由介電層630輔以晶粒封環650之設置 提供足夠的機械強度，以支撐内連線結構l〇d，避免1C於切 割時承受的機械應力造成界面脫層或著裂縫，而影響到1C 晶片。 綜上所述’本發明所提供之具有空氣間隙之内連線結構 及其製作方法’係為一可與現行半導體製程高度整合之方 201123346 法，且藉由在需要承受較大應力之處，例如焊墊區與晶粒封 環區，所設置的介電層所提供之機械支撐，可在降低金屬内 連線之間寄生電容的同時，仍維持之内連線結構之整體可靠 度。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第9圖係本發明所提供之具有空氣間隙之内連 線結構之製作方法之一第一較佳實施例之示意圖。 第10圖至第13圖係本發明所提供之具有空氣間隙之内 連線結構之製作方法之一第二較佳實施例之示意圖。 第14圖係本發明所提供之一内連線結構之第三較佳實施 例之剖面示意圖。 第15圖係本發明所提供之一内連線結構之第四較佳實施 例之剖面示意圖。 【主要元件符號說明】 10a、 10b、10c、10d 内連線結構 100 基底 102 主動電路 104 MOS電晶體 106 淺溝隔離 108 摻雜區域 110 層間介電層 21 201123346 112 接觸插塞 200 覆蓋層 202 介電層 206 溝渠開口 208 阻障層 210 金屬層 220 覆蓋層 222 間隙開口 224 空氣間隙 230 覆蓋層 300 介電層 302 触刻停止層 304 介電層 310 介層洞開口 312 溝渠開口 314 阻障層 320 接觸洞插塞 322 金屬内連線層 330 覆蓋層 332 間隙開口 334 空氣間隙 340 覆蓋層 500 基底 Μ! ' 、Μη 金屬内連線層 510 焊墊區 520 非焊墊區 512 ' 522 金屬内連線 514 ' 524 介層洞插塞 530 介電層 540 空氣間隙 550 轉接焊墊 600 基底 Μ!、Μ2·.·Μη_ι ' Μη 金屬内連線層 610 晶粒封環區 620 電路區 612 ' 622 金屬内連線 614 、 624 介層洞插塞 630 介電層 640 空氣間隙 650 晶粒封環 22Mn also includes a plurality of air gaps 640' disposed between metal interconnects 622 in circuit region 620 for electrically isolating metal interconnects 622 within circuit region 620. More importantly, the metal interconnect layer Μ!, M2, ..., My Mn provided by the preferred embodiment further includes a dielectric layer 630, and the via hole is disposed in the circuit region 620. Between the plugs 624, the via plugs 624 are electrically isolated in the circuit region 620. Further, the dielectric layer 630 is disposed in the die seal region 610 and surrounds the die seal region 610. Briefly, in the interconnect structure 10d provided in the fourth preferred embodiment, the metal interconnect 622 in the circuit region 620 is formed by the first preferred embodiment and the second preferred embodiment. The air gap 640 provides electrical isolation, thereby reducing its parasitic capacitance. Dielectric layer 630 is disposed within die seal region 610 and between via plugs 622 in circuit region 620 to provide electrical isolation. Since the grain seal ring region 610 must undergo the stress generated by the mechanical cutting during the cutting process performed after the 1C process is completed, the die seal region 610 is supplemented by the die seal ring by the dielectric layer 630. The 650 setting provides sufficient mechanical strength to support the interconnect structure l〇d, avoiding the mechanical stresses experienced by the 1C during delamination, causing delamination or cracking of the interface, affecting the 1C wafer. In summary, the 'internal connection structure with air gap provided by the present invention and its manufacturing method' is a method that can be highly integrated with the current semiconductor process, and by the method of 201123346, where it is required to withstand large stresses, For example, the pad region and the die ring region, the mechanical support provided by the dielectric layer can reduce the parasitic capacitance between the metal interconnects while maintaining the overall reliability of the interconnect structure. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the patent scope of the present invention are intended to be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 through 9 are schematic views showing a first preferred embodiment of a method for fabricating an inner wiring structure having an air gap provided by the present invention. 10 to 13 are schematic views showing a second preferred embodiment of a method for fabricating an interconnect structure having an air gap according to the present invention. Figure 14 is a cross-sectional view showing a third preferred embodiment of an interconnect structure of the present invention. Figure 15 is a cross-sectional view showing a fourth preferred embodiment of the interconnect structure of the present invention. [Main component symbol description] 10a, 10b, 10c, 10d interconnect structure 100 substrate 102 active circuit 104 MOS transistor 106 shallow trench isolation 108 doped region 110 interlayer dielectric layer 21 201123346 112 contact plug 200 cover layer 202 Electrical layer 206 trench opening 208 barrier layer 210 metal layer 220 cladding layer 222 gap opening 224 air gap 230 cladding layer 300 dielectric layer 302 etch stop layer 304 dielectric layer 310 via opening 312 trench opening 314 barrier layer 320 Contact hole plug 322 metal inner wiring layer 330 cover layer 332 gap opening 334 air gap 340 cover layer 500 substrate Μ! ', Μη metal interconnect layer 510 pad area 520 non-pad area 512 ' 522 metal interconnect 514 ' 524 via plug 530 dielectric layer 540 air gap 550 transfer pad 600 substrate Μ!, Μ 2·.·Μη_ι ' Μη metal interconnect layer 610 die ring area 620 circuit area 612 ' 622 metal Interconnect 614, 624 via plug 630 dielectric layer 640 air gap 650 die seal 22