CN100373607C - 半导体器件及其制造方法以及半导体芯片和电子设备 - Google Patents

半导体器件及其制造方法以及半导体芯片和电子设备 Download PDF

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CN100373607C
CN100373607C CNB2004101000077A CN200410100007A CN100373607C CN 100373607 C CN100373607 C CN 100373607C CN B2004101000077 A CNB2004101000077 A CN B2004101000077A CN 200410100007 A CN200410100007 A CN 200410100007A CN 100373607 C CN100373607 C CN 100373607C
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conductive layer
semiconductor device
projection
semiconductor chip
conductive particles
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CN1645602A (zh
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今井英生
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

一种半导体器件，包括：半导体芯片，该半导体芯片包括衬底、外部连接电极以及凸起，其中该凸起具有第一导电层和被设置在该第一导电层上的第二导电层，并且该第二导电层由铜组成；布线板，其具有焊接区；以及绝缘材料，该绝缘材料中散布有导电微粒，其中该导电微粒在凸起和焊接区之间连接，其中通过已经渗入到第二导电层和焊接区中的导电微粒来建立电连接。

Description

半导体器件及其制造方法以及半导体芯片和电子设备
技术领域
本发明涉及半导体器件、半导体芯片、制造半导体器件的方法，以及电子设备，并尤其涉及适于倒装片安装(flip-chip mounting)技术的半导体芯片。
本发明要求在2003年12月5日提交的日本专利申请No.2003-407386和在2004年10月20日提交的日本专利申请No.2004-305519的优先权，它们在此被引入作为参考。
背景技术
目前，强烈地要求减小移动电子设备，诸如移动电话和笔记本型个人计算机，的尺寸、宽度和重量，以及制造成本。为了满足这种要求，已经考虑在各种电子设备中使用的半导体芯片的高度集成，并且已经研究和开发了各种半导体安装技术。
作为一种用于安装有效的、且能够利用树脂来可靠地模压的半导体芯片的技术，提出了倒装片安装技术，如例如在日本未审查的专利申请、第一公开No.2000-286299中所公开的。在该方法中，由镍和金组成的凸起被设置在半导体芯片上，并且该半导体芯片和布线板通过各向异性的导电树脂层被电连接。
然而，该技术有个问题。为了确保与布线板的良好电连接，各向异性导电树脂层中包含的导电微粒需要渗入到形成被设置在半导体芯片上的凸起的表面的金层中。因而，由于需要形成具有足够厚度的金层，因此不能实现进一步的成本降低。
发明内容
鉴于上述缺点，构思了本发明，本发明的目的是：提供一种高度可靠的半导体器件和半导体芯片，该半导体器件和该半导体芯片能够以较低的成本来制造，并且能够确保良好的电连接；提供一种制造半导体器件的方法；以及提供一种具有该半导体器件的电子设备。
为了解决上述问题，根据本发明的半导体器件包括：半导体芯片，其包括衬底、外部连接电极以及凸起，其中该凸起具有第一导电层和被设置在该第一导电层上的第二导电层，该第一导电层由镍组成，而该第二导电层由铜组成；布线板，其具有焊接区；以及绝缘材料，该绝缘材料中散布有导电微粒，其中导电微粒在凸起和焊接区之间连接，其中通过已经渗入到第二导电层和焊接区的导电微粒来建立电连接。
在上述的半导体器件中，因为导电微粒渗入到第二导电层中的铜中，而不是导电微粒仅仅与第二导电层接触，因此保证了大的接触面积，并且可以提供低电阻电连接。此外，第二导电层和导电微粒之间的电连接变得可以抵抗由温度变化或振动等造成的绝缘材料的膨胀和收缩。从而，能够以较低成本提供具有可靠的电连接的半导体器件。此外，在该半导体器件中，因为导电微粒被安全地夹在凸起的表层中的铜和布线板上的焊接区中间，因此保证了稳定的电连接。因此，能够以较低成本提供具有可靠的电连接的半导体器件。
在上述半导体器件中，第二导电层的厚度优选地被选择成，使得导电微粒渗入该第二导电层的深度足以建立电连接。例如，第二导电层的厚度可以被选择成，使得导电微粒渗入该第二导电层的深度为该导电微粒的微粒尺寸的四分之一或更多。半导体芯片上的凸起和布线板上的焊接区一般具有不规则表面，而非平滑表面。如果导电例子渗入第二导电层的深度小于该导电微粒的微粒尺寸的四分之一，则由于不规则性的分布将造成接触面积较小，将不能建立良好的电连接。相反，如果导电微粒渗入第二导电层的深度为该导电微粒的微粒尺寸的四分之一或更多，则保证了大接触面积，并且减轻了不规则性的效应。因此，可以与布线板上的焊接区建立良好的电连接，并提高了半导体器件的可靠性。
在上述半导体器件中，第二导电层的厚度可以被选择成，使得导电微粒渗入第二导电层的深度为该导电微粒的微粒尺寸的二分之一或更多，以致凸起和焊接区直接接触。因为导电微粒被安全地夹在第二导电层和布线板上的焊接区中间，因此保证了稳定的电连接。因而，可以建立良好的电连接，并且提高了半导体器件的可靠性。
在上述半导体器件中，可以将催化剂布置在第一导电层与第二导电层之间。在某些情况下，其中某种材料组合被用于第一导电层和第二导电层，则不能在该第一导电层与第二导电层之间获得紧密的粘着。在某些情况下，诸如第二导电层脱落的问题可能会出现。当在第一导电层和第二导电层之间设置催化剂时，有可能通过适当地选择催化剂来提高第一导电层和第二导电层之间的粘着。
上述的半导体器件可以进一步包括钝化膜，该钝化膜被形成在衬底上，并且具有在外部连接电极中的开口。第一导电层可以被形成在该开口内，并且该第一导电层的厚度等于或小于该钝化膜的厚度。换句话说，第一导电层可以仅被形成在处于钝化膜中的开口内。如果由硬材料组成的第一导电层也被形成在钝化膜上，则当通过向半导体芯片施加压力来将半导体芯片安装到布线板上时，由于集中在钝化膜上的应力，使得该钝化膜将破裂。相反，如果第一导电层仅被形成在处于钝化膜中的开口内，则只有由铜组成的第二导电层被设置在钝化膜上。因而，当通过向半导体芯片施加压力来将半导体芯片安装到布线板上时，铜的挠性能够帮助减轻强加于钝化膜上的应力。因此，可以防止诸如钝化膜破裂的损坏，并且可以实现高度可靠的半导体芯片。
在上述半导体器件中，第一导电层可以由具有和导电微粒相同的硬度或比导电微粒更高的硬度的材料组成。此外，导电微粒可以包含具有比组成第二导电层的铜更高的硬度的材料组成。在该布置中，因为导电微粒不渗入到第一导电层中，而是渗入到第二导电层中，因此防止了导电微粒完全被埋入凸起中。因此，提高了电连接的可靠性。
本发明针对一种半导体芯片，该半导体芯片包括：衬底；外部连接电极，其被形成在该衬底上；凸起，其电连接到该外部连接电极，并且包括第一导电层和被设置在该第一导电层上的第二导电层，其中该第二导电层由铜组成；以及钝化膜，其具有在该外部连接电极上的开口，其中第一导电层和被设置在该钝化膜中的开口内的外部连接电极的正面接触，并且不接触该钝化膜的正面。
如果由例如镍的硬材料组成第一导电层也被形成在钝化膜上，则当通过向半导体芯片施加压力来将半导体芯片安装到布线板上时，由于集中在钝化膜上的应力，使得该钝化膜将破裂。相反，如果第一导电层仅被形成在处于钝化膜中的开口内，因而该第一导电层不和钝化膜的正面接触，则只有由铜组成的第二导电层被设置在钝化膜上。因而，当通过向半导体芯片施加压力来将半导体芯片安装到布线板上时，铜的挠性能够帮助减轻强加于钝化膜上的应力。因此，可以防止诸如钝化膜破裂的损坏，并且可以实现高度可靠的半导体芯片。
在上述半导体芯片中，可以将催化剂布置在第一导电层和第二导电层之间。该催化剂能够提高第一导电层和第二导电层之间的粘着。例如，可以将钯用作催化剂。
在上述半导体芯片中，被设置在钝化膜中的开口内的外部连接电极的厚度可以是0.2μm或更厚。具有足够厚度的外部连接电极能够减小在粘结期间对位于该外部连接电极下面的衬底的损坏。
在上述半导体芯片中，可以将比第一导电层软的第三导电层设置在第一导电层和第二导电层之间。该第三导电层可以减小在粘结期间对位于外部连接电极下面的衬底的损坏。
本发明针对一种制造半导体器件的方法，该半导体器件包括具有凸起的半导体芯片和具有焊接区的布线板，该凸起包括第一导电层，该方法包括以下步骤：在第一导电层上设置由铜组成的第二导电层，其中该第二导电层形成凸起的一部分；将其中散布有导电微粒的绝缘材料布置在具有第二导电层的凸起和焊接区之间；以及将凸起压在焊接区上，使得导电微粒渗入到第二导电层和该焊接区中，以便在该凸起和该焊接区之间建立电连接。
在通过上述制造方法制造的半导体器件中，因为导电微粒被安全地夹在布线板上的焊接区和凸起的表层中的铜中间，因此可以保持稳定的电连接。因而，根据本发明的制造半导体器件的方法，可以以较低成本提供具有可靠的电连接的半导体芯片。
上述的制造半导体器件的方法可以进一步包括步骤：将催化剂布置在第一导电层和第二导电层之间。可以通过适当地选择催化剂，来提高第一导电层和第二导电层之间的粘着。
在上述的制造半导体器件的方法，第一导电层和第二导电层至少之一可以利用化学沉积来形成。因为有可能利用化学沉积来形成高度变化较小的凸起，因此可以以较低成本提供高度可靠的半导体器件。
根据本发明的电子设备包括上述的、能够以较低成本提供高度可靠电子器件的半导体器件。
附图说明
图1所示为根据本发明第一实施例的半导体芯片的横截面示意图；
图2所示为根据本发明第一实施例的半导体器件的横截面示意图；
图3A至3F为图2中所示的半导体器件的制造步骤的一个例子的横截面示意图；
图4所示为根据本发明第二实施例的半导体芯片的横截面示意图；
图5所示为根据本发明第三实施例的半导体芯片的横截面示意图；以及
图6所示为根据本发明实施例的电子设备的透视图。
具体实施方式
以下将参考附图描述本发明的各实施例。应该注意，这些实施例不限制在权利要求中定义的本发明的范围。同样，并非实施例中的所有元件都是对权利要求中定义的主题所必不可少的。
第一实施例
图2为图解说明了根据第一实施例的半导体器件的横截面示意图。
半导体器件2包括：半导体芯片1；布线板(wiring board)20，其配备有多个焊接区(land)21；以及各向异性的导电树脂层31，其中散布有导电微粒30。
图1为图解说明了根据第一实施例的半导体芯片的横截面示意图。
半导体芯片1包括：多个外部连接电极11，其被设置在由例如硅组成的衬底10的一侧上；以及凸起(bump)40，其具有堆叠在一起的第一导电层13和第二导电层15。第一导电层13由例如镍组成，并且具有从10μm至25μm范围内的厚度，优选地为大约15μm。第二导电层15由铜组成，并具有大约5μm的厚度。外部连接电极11是电连接到已经被形成在衬底10上或衬底10中的集成电路(未显示)的电极，并且由铝或铜组成。
此外，在上面布置有外部连接电极11的衬底10一侧上，形成了由氧化硅组成的钝化膜。在钝化膜中设置开口12a，从而使外部连接电极11的一部分暴露。这样限定开口12a，使得外部连接电极11的中心被暴露。在该情况下，外部连接电极11的边缘被钝化膜的一部分覆盖。换句话说，在上面布置有外部连接电极11的衬底10一侧上，外部连接电极11的至少一部分被暴露，并且该外部连接电极11的其余部分被钝化膜12覆盖。
由例如钯组成的催化剂被布置在第一导电层13与第二导电层15之间。该催化剂有助于增强由镍组成的第一导电层13和由铜组成的第二导电层15之间的粘着，以便提高互连的可靠性。
布线板20可以是，但不限于，由例如聚酰亚胺树脂、聚酯膜等组成的挠性衬底。布线板20可以是刚性衬底，例如玻璃钢板衬底或陶瓷衬底。焊接区21是导电层，该导电层可以由例如铜组成，或者可以由具有比铜更低的电阻率的银组成。
各向异性的导电树脂层31由热固树脂，例如环氧树脂，组成，并且被夹在上面布置有凸起40的半导体芯片1一侧和上面布置有焊接区21的布线板20一侧的中间，以便密封并粘结半导体芯片1和布线板20。导电微粒30由具有比组成第二导电层15的铜更高的硬度的材料，诸如镍，组成。导电微粒30具有从0.2μm至5μm范围内的微粒尺寸，优选地具有大约4μm的微粒尺寸。当在此使用，术语“导电微粒的微粒尺寸”指的是导电微粒的微粒尺寸。
作为凸起40的最外层的第二导电层15与焊接区21接触。夹在第二导电层15和焊接区21中间的导电微粒30渗入第二导电层15和焊接区21。换句话说，当导电微粒30被夹在凸起40和焊接区21中间时，因为镍比铜硬，因此由镍组成的导电微粒30渗入到由铜组成的第二导电层15中，并被第二导电层15俘获。这样选择第二导电层15的厚度，使得导电微粒30渗入到第二导电层15，以建立电连接。导电微粒渗入到第二导电层15的深度被设置为大约5μm，因此渗入深度至少为导电微粒30的微粒尺寸的四分之一或更多，在该实施例中渗入深度为1μm或更大。当在此使用，术语“导电微粒的渗入深度”指的是导电微粒渗入到第二导电层中的平均距离。如果导电微粒30被夹在凸起40和焊接区21中间，同时凸起40和焊接区21直接接触，则有可能使导电微粒30渗入到第二导电层15中，且渗入深度为导电微粒30的微粒尺寸的二分之一或更多，在该实施例该渗入深度中为2μm或更大。因此，凸起40和焊接区21通过导电微粒30电连接。
应该注意，第一导电层13可以由和导电微粒30一样硬的材料组成，乃至可以具有比导电微粒更高的硬度。这样防止导电微粒30完全埋入凸起40中，并且提高了电连接的可靠性。
如下，将说明图2所示的半导体器件2的制造过程。图3A至3F为半导体器件2的制造过程的横截面示意图。在附图中，只显示了与本发明相关的元件。
如图3A所示，设置由硅等组成的衬底10，在该衬底10上已经形成了集成电路(未显示)。衬底10包括多个外部连接电极11。外部连接电极11是电连接到已经被形成在衬底10上的集成电路(未显示)的电极，并且由铝或铜等组成。
接下来，将钝化膜12沉积在上面设置有外部连接电极的衬底10一侧上。钝化膜12由例如这样的薄膜组成，该薄膜由作为衬底10(SiO2或SiN)的材料的氧化硅或氮化硅、聚酰亚胺树脂等组成。
接下来，将说明在每一个外部连接电极11上形成凸起的步骤。如图3B所示，当外部连接电极11由铝组成时，该外部连接电极11受到锌酸盐处理，以电解方式用锌代替表面上的铝，以形成由锌组成的金属涂层(未显示)。然后，将第一导电层13形成在外部连接电极11上。该第一导电层13由例如镍组成，并且可以利用化学沉积来形成。换句话说，把已经受到锌酸盐处理的外部连接电极11浸入化学镀镍溶液中，从而镍被沉淀。第一导电层13的厚度为，例如从大约10μm至大约25μm，选地为大约15μm。在该实施例中，设置蘑菇形凸起，并且在没有使用模板的情况下形成导电层。然而，应该注意，可以使用具有抗蚀层(resist layer)的模板来形成直壁型凸起。
接下来，将催化剂布置在第一导电层13上。例如，该催化剂可以是钯。为了布置钯，可以采用敏化激活方法或催化加速剂方法。
接下来，如图3C所示，形成第二导电层15。第二导电层15由例如铜组成，并且可以利用化学沉积来形成。特别是，把第一导电层13浸入铜电镀液中。位于第一导电层13上的钯起催化剂的作用，铜被沉淀。第二导电层15的厚度优选地为大约5μm。催化剂可以改善第一导电层和第二导电层之间的粘着。
在上述的步骤中，在每一个外部连接电极11上都形成包括第一导电层13和第二导电层15的凸起，并且因此制造半导体芯片1。
接下来，如图3D所示，设置布线板20，并且将多个焊接区21设置在该布线板20的一个表面上。将各向异性的导电树脂层31布置在上面已经布置有焊接区21的布线板20一面上。布线板20可以是，但不限于，由例如聚酰亚胺树脂、聚酯膜等组成的挠性衬底。布线板20可以是刚性衬底，例如玻璃钢板衬底或陶瓷衬底。焊接区21是导电层，该导电层可以由例如铜组成，或者可以由具有比铜更低的电阻率的银组成。
各向异性导电树脂层31由糊状的环氧树脂，例如热固树脂，组成，并且具有粘附特性。利用丝网印刷或分配方法，将各向异性导电树脂层31设置在布线板20上。应该注意，可以通过将树脂膜涂敷在布线板20上，来形成各向异性导电树脂层31。在各向异性导电树脂层31中，散布有多个导电微粒。
然后，如图3E所示，使图3C中所示的半导体芯片1倒置，并将半导体芯片1放置成与配备有各向异性导电树脂层31的布线板20相对。特别是，将凸起40放置成与要与之建立电连接的布线板20上的焊接区21相对，并且借助于各向异性导电树脂层的粘附特性将半导体芯片1临时粘附到各向异性导电树脂层上。把具有增压平面(flatpressurizing surface)的热压工具50加热到各向异性导电树脂层3 1的硬化温度(curing temperature)。当与布线板20平行地放置热压工具50的增压平面时，压力被施加到该增压平面上，从而半导体芯片1被压在布线板20上。
结果，如图3F所示，各向异性导电树脂31被凸起40替代，直到该凸起40接触被设置在布线板20上的焊接区21为止。各向异性导电树脂层31中包含的导电微粒30被夹在作为凸起40的最外层的第二导电层15和焊接区21中间。因为导电微粒30的硬度比由铜组成的第二导电层15的硬度大，因此导电微粒30渗入到第二导电层15。导电微粒30渗入第二导电层15的深度被设置为，至少是导电微粒30的微粒尺寸的四分之一或更多，例如大约1μm的渗入深度。如果导电微粒30被夹在凸起40和焊接区21中间，同时凸起40和焊接区21直接接触，则有可能使导电微粒30渗入到第二导电层15中，并且渗入深度为导电微粒30的微粒尺寸的二分之一或更多，在该实施例该渗入深度中为2μm或更大。同时，导电微粒30渗入到由铜或银组成的焊接区21中。结果，有可能在凸起40和焊接区21之间建立电连接，该电连接具有低接触电阻，且高度可靠，并且能够抵抗由于温度变化或振动造成的膨胀或收缩。
应该注意，在该实施例中，当把半导体芯片1垂直地压在布线板20上，并且施加压力时，可能施加由超声震动产生的微小振动。这使得导电微粒30能够容易地切入由铜组成的第二导电层15和在焊接区21的表面上形成的氧化膜中，确保了更好的电连接。
然后，使各向异性导电树脂层31热硬化(thermo-cured)，同时保持凸起40与焊接区21之间的电连接，以密封并粘结半导体芯片1和布线板20。
如上所述，根据该实施例，因为导电微粒30渗入由铜组成的第二导电层15和布置在布线板20上的焊接区21，因此接触面积增大了，这提供了低电阻电连接。此外，因为导电微粒30被夹在凸起40和布线板20上布置的焊接区21中间，因此互连变得可以抵抗由于温度变化或振动等造成的绝缘材料的膨胀和收缩。因此，可以以较低的成本提供具有良好的电连接的半导体芯片。此外，因为可以利用化学沉积来形成凸起40，因此可以制造高度变化较小的凸起。
第二实施例
接下来，将描述根据本发明的半导体芯片的第二实施例。图4为图解说明了半导体芯片的第二实施例的横截面示意图，该第二实施例与图1所示的第一实施例相对应。第二实施例的半导体芯片3包括凸起40，该凸起40包括第一导电层13和第二导电层15，并且在被布置在由硅组成的衬底10的一侧上的多个外部连接电极11的每一个上都设置凸起40。该第二实施例不同于第一实施例之处在于，第一导电层13被设置在处于钝化膜12中的开口12a内，并且该第一导电层13的厚度等于或小于钝化膜12的厚度。换句话说，只在钝化膜12的开口12a内设置第一导电层13。第一导电层13与钝化膜12的开口12a内的外部连接电极11的正面11F接触，并且不接触钝化膜的正面。在附图中，相同的附图标记表示图1中所示的对应元件，并且将省略对它们的说明。
钝化膜12是由例如氧化硅组成的膜，并且具有从1μm至3μm范围内的厚度，优选地为大约1.5μm厚。第一导电层13由例如镍组成，并且电连接到外路连接电极11。第一导电层13的厚度可以是等于或小于钝化膜12的厚度的任何值。第一导电层13的厚度优选地等于钝化膜的厚度，即大约1.5μm，从而第一导电层13和围绕该第一导电层13的钝化膜12处于同一平面内。
根据该实施例，因为在钝化膜12的正面12F上只形成由铜组成的第二导电层15，因此当通过向半导体芯片3施加压力来把半导体芯片3安装到布线板20上时，施加于钝化膜12上的应力通过铜的挠性而得以减轻。因此，可以防止诸如钝化膜12破裂的损坏，并且可以实现高度可靠的半导体芯片。
此外，在该实施例中，由例如钯组成的催化剂(未显示)被布置在第一导电层13和第二导电层15之间。该催化剂能够增强由镍组成的第一导电层13与由铜组成的第二导电层15之间的粘着。
第三实施例
图5为根据本发明第三实施例的半导体器件的横截面视图。如图5所示，可以将比第一导电层13软的第三导电层13’设置在第一导电层13和第二导电层15之间。在该实施例中，第一导电层13由镍(Ni)组成，第三导电层13’由比镍软的金属金(Au)组成。第三导电层13’可以减小在粘结期间对位于外部连接电极11下面的衬底10的损坏(硅开裂)。由金组成的第三导电层13’可以防止第一导电层13等的氧化。第三导电层13’也充当上述实施例中的催化剂。
在上述的实施例中，被设置在钝化膜12的开口12a内的外部连接电极11的厚度优选地为0.2μm或更厚。因为由铝(Al)组成的外部连接电极11具有足够的厚度，因此可以减小在粘结期间对位于外部连接电极11下面的衬底10的损坏(硅开裂)。
在图6中，便携式电话100被显示为具有根据该实施例的半导体器件的电子设备的例子。图2所示的半导体器件被安装在这种电子设备的外壳中。
电子设备不限于IC卡或便携式电话，并且本发明可应用于各种电子设备。例如，本发明可应用于各种各样的电子设备，包括笔记本型的个人计算机、个人数字助理(PDA)、电子管理器、电子台式计算器、液晶投影仪、打印机等。
虽然以上已经描述和例举了本发明的优选实施例，但是应该理解，这些优选实施例是本发明的例子，而不是限制性的。在不背离本发明的精神或范围的情况下，可以对本发明进行添加、替代和其它的更改。因此，本发明不应被认为是受上述的描述限制，而仅由附加权利要求的范围限定。

Claims (16)

1.一种半导体器件，包括：
半导体芯片，该半导体芯片包括：
衬底；
外部连接电极；以及
凸起，其中该凸起具有第一导电层和被设置在该第一导电层上的第二导电层，该第一导电层由镍组成，而该第二导电层由铜组成；
布线板，其具有焊接区；以及
绝缘材料，该绝缘材料中散布有导电微粒，其中该导电微粒在所述凸起和所述焊接区之间连接，
其中通过已经渗入到第二导电层和焊接区中的导电微粒，来建立电连接。
2.根据权利要求1所述的半导体器件，其中，选择所述第二导电层的厚度，使得导电微粒渗入到该第二导电层中，以建立电连接。
3.根据权利要求1所述的半导体器件，其中，选择所述第二导电层的厚度，使得导电微粒渗入该第二导电层的深度是该导电微粒的微粒尺寸的四分之一或更多。
4.根据权利要求1所述的半导体器件，其中，选择所述第二导电层的厚度，使得导电微粒渗入该第二导电层的深度是该导电微粒的微粒尺寸的二分之一或更多，以致所述凸起和所述焊接区直接接触。
5.根据权利要求1所述的半导体器件，其中，催化剂被布置在所述第一导电层和所述第二导电层之间。
6.根据权利要求1所述的半导体器件，进一步包括钝化膜，该钝化膜被形成在衬底上，并具有在外部连接电极中的开口，其中所述第一导电层被形成在该开口内，并且该第一导电层的厚度等于或小于所述钝化膜的厚度。
7.根据权利要求1所述的半导体器件，其中，所述第一导电层由具有和导电微粒相同的硬度或比导电微粒更高的硬度的材料组成。
8.根据权利要求1所述的半导体器件，其中，所述导电微粒包含具有比组成第二导电层的铜更高的硬度的材料。
9.一种半导体芯片，包括：
衬底；
外部连接电极，其被形成在所述衬底上；
凸起，其电连接到所述外部连接电极，并且包括第一导电层和被设置在该第一导电层上的第二导电层，其中该第二导电层由铜组成；以及
钝化膜，其具有在所述外部连接电极上的开口，
其中所述第一导电层和被设置在该钝化膜中的开口内的外部连接电极的正面接触，并且不和该钝化膜的正面接触。
10.根据权利要求9所述的半导体芯片，其中，催化剂被布置在所述第一导电层和所述第二导电层之间。
11.根据权利要求9所述的半导体芯片，其中，在被设置在钝化膜中的开口内的外部连接电极的厚度为0.2μm或更厚。
12.根据权利要求9所述的半导体芯片，其中，比所述第一导电层软的、由金组成的第三导电层被设置在所述第一导电层和所述第二导电层之间。
13.一种制造半导体器件的方法，该半导体器件包括具有凸起的半导体芯片和具有焊接区的布线板，该凸起包括第一导电层，所述方法包括以下步骤：
在该第一导电层上设置由铜组成的第二导电层，其中该第二导电层形成凸起的一部分；
将其中散布有导电微粒的绝缘材料布置在具有第二导电层的所述凸起和所述焊接区之间；以及
将所述凸起压在所述焊接区上，使得导电微粒渗入到所述第二导电层和所述焊接区中，以便在所述凸起和所述焊接区之间建立电连接。
14.根据权利要求13所述的制造半导体器件的方法，其进一步包括步骤：将催化剂布置在所述第一导电层和所述第二导电层之间。
15.根据权利要求14所述的制造半导体器件的方法，其中所述第一导电层和所述第二导电层至少之一是利用化学沉积形成的。
16.一种包括根据权利要求1所述的半导体器件的电子设备。
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JP2005191541A (ja) 2005-07-14
US20050127504A1 (en) 2005-06-16
US7528487B2 (en) 2009-05-05
TWI248152B (en) 2006-01-21

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