CN100373592C - Pecvd富含硅的氧化物层以减少uv充电 - Google Patents

Pecvd富含硅的氧化物层以减少uv充电 Download PDF

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CN100373592C
CN100373592C CNB2004800199594A CN200480019959A CN100373592C CN 100373592 C CN100373592 C CN 100373592C CN B2004800199594 A CNB2004800199594 A CN B2004800199594A CN 200480019959 A CN200480019959 A CN 200480019959A CN 100373592 C CN100373592 C CN 100373592C
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silicon oxide
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M·V·努
M·T·拉姆斯贝
T·卡迈勒
P·Y·高
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Abstract

在金属化之前，通过PECVD在层间电介质(300)上沉积UV透射减少的富含硅的氧化硅层(500)，因而减小了Vt。实施例包括沉积折射率(R.I.)为1.7至2.0的UV不透明的富含硅的氧化硅层(500)。该富含硅的氧化硅层(SiRO)减小了在制造EEPROM闪存中的UV单元充电问题。

Description

PECVD富含硅的氧化物层以减少UV充电
技术领域
本发明涉及制造具有高可靠性的半导体器件的方法及所获得的半导体器件。本发明特别适用于制造具有减少的UV单元充电的(withreduced UV cell charging)微型化闪存器件。
背景技术
在努力满足对于微型化的持续增加需求方面，遇到各式各样的问题，尤其是在制造诸如闪存器件的非易失性半导体器件时，例如在制造电可擦除可编程只读存储器(EEPROM)器件时，更是如此。继续要求微型化导致制造出的闪存器件所包含的晶体管具有大约0.13微米及以下的栅极宽度以及由大约0.30微米或更小的小间隙所间隔开的栅极结构。依照传统的实践方面，氧化物侧壁间隔物形成在栅极堆叠的侧表面，而第一层间(interlayer)电介质(ILD0)沉积在栅极结构上，填充其间的间隙。
当急速发展微型化时，出现了各种可靠性问题，尤其当EEPROM器件尺寸按比例缩小到深亚微米的范围时更是如此，诸如在生产线的后端处理(back end of line processing)期间的UV充电，诸如尤其是在等离子体处理期间的沉积、金属蚀刻和钝化(passivation)。在此种处理期间产生的UV辐射造成所不希望的闪存器件的UV充电并附带增大了阈电压(Vt)。经过UV充电并表现出增大的Vt的单元极其难以过度编程(over-program)，也较难以过度擦除(over-erase)。若增大了初始的Vt值，则在擦除状态和编程状态之间具有较小的Vt窗口，由此而引发各种可靠性问题和运行速度问题。
因此，需要有改进了可靠性且提高了运行速度的诸如闪存器件的微型化半导体器件，例如EEPROMs，并且需要有效的方法使得能制造这样的器件且减少UV单元充电。
发明内容
本发明的一个优点是提供一种制造半导体器件的方法，尤其是制造闪存半导体器件的方法，其具有改进的可靠性和减少的UV单元充电。
本发明的另一优点是提供一种半导体器件，例如闪存半导体器件，具有改进的可靠性和减少的UV单元充电。
本发明的额外优点和其它特征将在以下说明中指出，而其部分内容对于本领域的技术人员在阅读下文后将变得很清楚，或者可从实践本发明而得到。可实现并获得本发明的优点，并特别在所附的权利要求中指出。
依照本发明，上述优点和其它优点部分地是通过制造半导体器件的方法而实现，该方法包括：在衬底上形成具有栅极结构的晶体管，在该衬底与栅极之间具有栅极介电层；在该晶体管上形成层间电介质；以及在该层间电介质的上表面形成折射率(refractive index,R.I.)大于1.6的富含硅的氧化硅层(silicon-rich silicon oxide layer)，其中所述富含硅的氧化硅层对UV辐射是不透明的且具有
Figure C20048001995900051
至
Figure C20048001995900052
的厚度。
本发明的另一方面是一种半导体器件，包括：具有在衬底上的栅极结构的晶体管，在该衬底与栅极之间具有栅极介电层；在该晶体管上的层间电介质；以及在该层间电介质的上表面上折射率(R.I.)大于1.6的富含硅的氧化硅层，其中所述富含硅的氧化硅层对UV辐射是不透明的且具有
Figure C20048001995900053
至
Figure C20048001995900054
的厚度。
本发明的实施例包括形成富含硅的氧化硅层(SiRO)，R.I．大于1.7，诸如1.7至2.0，而厚度为
Figure C20048001995900055
至
Figure C20048001995900056
。本发明的实施例还包括沉积掺杂硼(B)和磷(P)的硅酸盐玻璃(BPSG)作为层间电介质，平面化BPSG层的上表面，然后在450℃至650℃的提高温度和在115至135sccm的硅烷流速(silane flow rate)-F通过等离子体增强化学气相沉积来沉积富含硅的氧化硅(SiRO)层。本发明的实施例还包括形成栅极结构，该栅极结构包括衬底上的隧道氧化物、隧道氧化物上的浮置栅极电极、浮置栅极上的包括氧化物/氮化物/氧化物(0NO)堆叠的多晶硅间电介质(interpoly dielectric)、和多晶硅间电介质上的控制栅极电极。
由以下详细说明，本发明的其它优点对于本领域的技术人员将变得很清楚，其中本发明的实施例仅仅是示意说明实施本发明的最佳模式。将了解到，能在各种明显的方面修改本发明，而都不偏离本发明。因此，附图和说明在本质上应视为是示意性的，而非限制性的。
附图说明
图1示意了本发明的实施例，其中在包含EEPROM单元的半导体器件中使用了对UV辐射基本上不透明的(opaque)富含硅的氧化硅层。
具体实施方式
本发明通过提供有效的方法使得能制造UV退化减少的半导体器件，而解决了在制造半导体器件中所产生的各种可靠性问题。本发明的实施例包括制造例如EEPROM器件的闪存器件，且单元的UV充电明显减少。
根据进行的实验和研究，发现在诸如沉积、金属蚀刻和钝化、尤其是等离子体处理的生产线后端处理期间所产生的UV辐射充电了单元，因此增大了单元的编程电压。编程电压的这种所不希望的增大减小了擦除状态和编程状态之间的Vt窗口。
本发明通过在层间电介质上，即在ILD0上，沉积对UV辐射基本上不透明的SiRO层，而解决了这种UV单元充电问题。SiRO层一般具有大于1.6的R.I.，诸如大于1.7，例如1.7至2.0。
本发明通过在提高的温度，诸如在450℃至550℃的温度，例如在500℃，以及在100至150 sccm的硅烷流速，诸如在125 sccm的硅烷流速，进行等离子体增强化学气相沉积技术来实现所述目标。此种沉积可当N20流速为165至195 sccm，例如180 sccm，而压力为1.8至2.2托(Torr)，例如2.0托，以及RF功率为110至140瓦特(Watts)，例如125瓦特时进行。间距(晶片和气体从其喷出的喷头之间的距离)可维持在大约625至675密尔(mils.)，例如650密尔。沉积过程可进行3至15秒，而导致沉积了厚度为
Figure C20048001995900071
至
Figure C20048001995900072
，例如的SiRO膜。此种等离子体增强化学气相沉积技术可用来有效地沉积硅含量增加的SiRO层，而使得R.I．升高至大于1.6，诸如大于1.7，例如1.7至2.0；而一般的氧化硅层呈现出1.45至1.46的R.I．。依照本发明使用的SiRO膜提供了比使用传统制造技术所获得的Vt分布更紧密的Vt分布。
图1示意了本发明的实施例，其中在衬底30上形成晶体管。衬底30可包括掺杂的单晶硅或多个井(wells)或外延层(epitaxial layer)。晶体管可包括在其间具有多晶硅间(ONO)电介质的双栅极结构。例如，晶体管可包括隧道氧化物33、浮置栅极电极34、ONO堆叠多晶硅间电介质35、和控制栅极36。金属硅化物层37A形成在栅极电极堆叠的上表面，而金属硅化物层37B形成在源极/漏极区域31、32。诸如氧化硅的介电侧壁间隔物38形成在栅极电极的侧表面上。氮化硅蚀刻终止层39可沉积在栅极结构和氧化硅侧壁间隔物38上。随后，使用等离子体增强化学气相沉积来沉积层间电介质(ILD0)300，诸如BPSG层。然后例如通过化学机械抛光(chemical mechanical polishing，CMP)来进行平面化。
依照本发明的实施例，然后在BPSG层300的上表面上沉积SiRO层500。依照本发明的实施例所沉积的SiRO层表现出大于1.6的R.I.，例如为1.7至2.0，因此阻隔了在生产线的后续后端处理期间所产生的UV辐射到达单元，并避免增大其编程电压。
后续处理包括各向异性蚀刻(anisotropic etching)以形成虚线所示的通过SiRO层500和层间电介质300的接触孔400。SiRO层500的存在防止在此种各向异性蚀刻期间所产生的UV辐射造成不希望的Vt的升高。UV不透明SiRO层500还保护单元不受生产线后续后端处理期间的UV辐射，所述后端处理诸如金属化、沉积和蚀刻操作。此外，单元受到保护而不受UV辐射。
本发明提供改进了可靠性的半导体器件，诸如提高了运行速度且减少了单元因UV辐射而过度编程的EEPROM器件，并提供可实施的方法。依照本发明的实施例，在平面化的BPSG层间电介质上沉积富含硅的氧化硅层，该富含硅的氧化硅层有效地阻隔在后端处理期间所产生的UV辐射到达单元，并避免增大单元的编程电压。
本发明具有制造各种类型的半导体器件的工业可应用性，尤其是在呈现出提高的电路速度和亚微米尺寸的高度集成半导体器件方面，例如，具有高可靠性且设计标准在大约0.12微米或以下。本发明在制造诸如EEPROMs的闪存器件方面具有特殊的工业可应用性，该闪存器件的单元UV充电明显减少。
在上述详细说明中，本发明已参照其特定实施例而作了说明。然而，很明显，可作各种修改和改变，而不会偏离本发明如权利要求中所提出的较广精神和范围。因此，说明书和附图应视为是示意性的而非限制性的。应了解，本发明能使用各种其它组合和环境，并能在此所表述的发明概念的范围内作改变和修改。

Claims (10)

1.一种制造半导体器件的方法，所述方法包括：
形成晶体管，所述晶体管具有在衬底(30)上的栅极结构，且所述衬底(30)和所述栅极结构之间具有栅极介电层；
在所述晶体管上形成层间电介质(300)；以及
在所述层间电介质(300)的上表面上形成折射率大于1.6的富含硅的氧化硅层(500)，
其中所述富含硅的氧化硅层对UV辐射是不透明的且具有400至600的厚度。
2.如权利要求1所述的方法，其中所述富含硅的氧化硅层(500)具有大于1.7的折射率。
3.如权利要求1所述的方法，包括：
沉积一层掺杂硼和磷的硅酸盐玻璃BPSG作为所述层间电介质(300)；
平面化所述BPSG层(300)的上表面；以及
在450℃至650℃的温度通过等离子体增强化学气相沉积来沉积所述富含硅的氧化硅层(500)。
4.如权利要求1所述的方法，包括在100至150sccm的硅烷流速，165至195sccm的N2O流速，110至140瓦特的R.F.功率，625至675密尔的间距，以及1.8至2.2托的压力，经过3至15秒，沉积所述富含硅的氧化硅层(500)，其中，所述间距为所述衬底(30)与喷出所述硅烷和N2O的喷头之间的距离。
5.如权利要求1所述的方法，其中所述栅极结构包括：
在所述衬底(30)上作为所述栅极介电层的隧道氧化物(33)；
在所述隧道氧化物(33)上的浮置栅极电极(34)；
包括在所述浮置栅极电极(34)上的氧化物/氮化物/氧化物ONO堆叠的多晶硅间电介质(35)；以及
在所述多晶硅间电介质(35)上的控制栅极电极(36)，所述方法包括：
在所述栅极结构的侧表面上形成氧化硅侧壁间隔物(38)；
在以上所形成的栅极堆叠的上表面和所述氧化硅侧壁间隔物(38)上形成氮化硅层(39)；以及
之后沉积所述层间电介质。
6.一种半导体器件，包括：
晶体管，所述晶体管具有在衬底(30)上的栅极结构，且所述衬底(30)和所述栅极结构之间具有栅极介电层；以及
富含硅的氧化硅层(500)，所述富含硅的氧化硅层(500)位在形成于所述晶体管上的层间电介质(300)的上表面上且具有大于1.6的折射率，其中所述富含硅的氧化硅层对UV辐射是不透明的且具有400至600的厚度。
7.如权利要求6所述的半导体器件，其中所述富含硅的氧化硅层(500)具有大于1.7的折射率。
8.如权利要求6所述的半导体器件，其中所述栅极结构包括：
在所述衬底(30)上作为所述栅极介电层的隧道氧化物(33)；
在所述隧道氧化物(33)上的浮置栅极电极(34)；
包括在所述浮置栅极电极(34)上的氧化物/氮化物/氧化物ONO堆叠的多晶硅间电介质(35)；以及
在所述多晶硅间电介质(35)上的控制栅极电极(36)。
9.如权利要求8所述的半导体器件，包括在所述栅极结构的侧表面上的氧化硅侧壁间隔物(38)，以及在所述栅极结构的上表面和所述氧化硅侧壁间隔物上的氮化硅层(39)。
10.如权利要求8所述的半导体器件，其中所述层间电介质(300)为掺杂硼和磷的硅酸盐玻璃BPSG。
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