CH620557A5 - - Google Patents
Download PDFInfo
- Publication number
- CH620557A5 CH620557A5 CH1638576A CH1638576A CH620557A5 CH 620557 A5 CH620557 A5 CH 620557A5 CH 1638576 A CH1638576 A CH 1638576A CH 1638576 A CH1638576 A CH 1638576A CH 620557 A5 CH620557 A5 CH 620557A5
- Authority
- CH
- Switzerland
- Prior art keywords
- signal
- level
- gnd
- vdd
- clock pulse
- Prior art date
Links
- 230000005669 field effect Effects 0.000 claims description 2
- 230000015654 memory Effects 0.000 claims description 2
- 239000000872 buffer Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012432 intermediate storage Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018557—Coupling arrangements; Impedance matching circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/01855—Interface arrangements synchronous, i.e. using clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09425—Multistate logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09425—Multistate logic
- H03K19/09429—Multistate logic one of the states being the high impedance or floating state
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Measurement Of Current Or Voltage (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP78476A JPS5284938A (en) | 1976-01-07 | 1976-01-07 | Logic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
CH620557A5 true CH620557A5 (fr) | 1980-11-28 |
Family
ID=11483314
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CH1638576A CH620557A5 (fr) | 1976-01-07 | 1976-12-28 |
Country Status (4)
Country | Link |
---|---|
US (1) | US4100429A (fr) |
JP (1) | JPS5284938A (fr) |
CH (1) | CH620557A5 (fr) |
DE (1) | DE2657948C3 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0523747A1 (fr) * | 1986-03-11 | 1993-01-20 | Fujitsu Limited | Bascule de verrouillage |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4217502A (en) * | 1977-09-10 | 1980-08-12 | Tokyo Shibaura Denki Kabushiki Kaisha | Converter producing three output states |
US4163907A (en) * | 1977-09-16 | 1979-08-07 | Harris Corporation | Three logic state input buffers |
DE2925331C2 (de) * | 1978-06-23 | 1982-12-09 | RCA Corp., 10020 New York, N.Y. | Integrierte Schaltung mit mehrfach benutzbaren Anschlüssen |
US4350906A (en) * | 1978-06-23 | 1982-09-21 | Rca Corporation | Circuit with dual-purpose terminal |
US4207792A (en) * | 1979-05-10 | 1980-06-17 | The Wurlitzer Company | Tri-state encoding circuit for electronic musical instrument |
DE2922595C2 (de) * | 1979-06-02 | 1982-04-01 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Digitales Informationsübertragungssystem |
JPS57119524A (en) * | 1981-01-19 | 1982-07-26 | Oki Electric Ind Co Ltd | Tristate input circuit |
US4449065A (en) * | 1981-10-02 | 1984-05-15 | Fairchild Camera & Instrument Corp. | Tri-level input buffer |
JPS5884522A (ja) * | 1981-11-16 | 1983-05-20 | Toshiba Corp | レベル比較器 |
US4577282A (en) * | 1982-02-22 | 1986-03-18 | Texas Instruments Incorporated | Microcomputer system for digital signal processing |
US4489417A (en) * | 1982-11-24 | 1984-12-18 | International Business Machines Corporation | Multi-level communication circuitry for communicating digital signals between integrated circuits |
DE3328541C2 (de) * | 1983-08-06 | 1987-01-08 | Telefunken electronic GmbH, 7100 Heilbronn | Logische Schaltung |
US4598214A (en) * | 1983-10-31 | 1986-07-01 | Texas Instruments Incorporated | Low power shift register latch |
US4646331A (en) * | 1985-04-01 | 1987-02-24 | Intersil, Inc. | Electronic static switched-latch frequency divider circuit with odd number counting capability |
US4785204A (en) * | 1985-06-21 | 1988-11-15 | Mitsubishi Denki Kabushiki Kaisha | Coincidence element and a data transmission path |
FR2662874B1 (fr) * | 1990-05-30 | 1992-08-07 | Sgs Thomson Microelectronics | Circuit integre avec broche de detection de mode. |
US5631575A (en) * | 1995-09-07 | 1997-05-20 | National Science Council | Intermediate voltage sensor for CMOS circuits |
US5714892A (en) * | 1996-04-04 | 1998-02-03 | Analog Devices, Inc. | Three state logic input |
US5912563A (en) * | 1997-05-22 | 1999-06-15 | Sun Microsystems, Inc. | Trinary signal apparatus and method |
US6133753A (en) * | 1998-11-25 | 2000-10-17 | Analog Devices, Inc. | Tri-state input detection circuit |
TWI269529B (en) * | 2005-06-14 | 2006-12-21 | Richtek Technology Corp | Tri-state output logic with zero quiescent current by one input control |
JP5301262B2 (ja) | 2008-12-19 | 2013-09-25 | ルネサスエレクトロニクス株式会社 | 半導体装置、及び動作モ−ド切換方法 |
US9960588B2 (en) | 2015-03-19 | 2018-05-01 | Infineon Technologies Ag | Power switch device |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3526783A (en) * | 1966-01-28 | 1970-09-01 | North American Rockwell | Multiphase gate usable in multiple phase gating systems |
US3609411A (en) * | 1970-07-06 | 1971-09-28 | Hughes Aircraft Co | Mosfet level detector |
US3832576A (en) * | 1970-08-21 | 1974-08-27 | Texas Instruments Inc | Encoder circuit to reduce pin count for data entry into insulated gate field effect transistor integrated circuits |
US3845328A (en) * | 1972-10-09 | 1974-10-29 | Rca Corp | Tri-state logic circuit |
US3812384A (en) * | 1973-05-17 | 1974-05-21 | Rca Corp | Set-reset flip-flop |
JPS5046374A (fr) * | 1973-08-30 | 1975-04-25 | Toyo Kogyo Co | |
US3936676A (en) * | 1974-05-16 | 1976-02-03 | Hitachi, Ltd. | Multi-level voltage supply circuit for liquid crystal display device |
US3969633A (en) * | 1975-01-08 | 1976-07-13 | Mostek Corporation | Self-biased trinary input circuit for MOSFET integrated circuit |
-
1976
- 1976-01-07 JP JP78476A patent/JPS5284938A/ja active Pending
- 1976-12-20 US US05/752,141 patent/US4100429A/en not_active Expired - Lifetime
- 1976-12-21 DE DE2657948A patent/DE2657948C3/de not_active Expired
- 1976-12-28 CH CH1638576A patent/CH620557A5/de not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0523747A1 (fr) * | 1986-03-11 | 1993-01-20 | Fujitsu Limited | Bascule de verrouillage |
Also Published As
Publication number | Publication date |
---|---|
DE2657948A1 (de) | 1977-07-14 |
JPS5284938A (en) | 1977-07-14 |
DE2657948B2 (de) | 1980-10-02 |
US4100429A (en) | 1978-07-11 |
DE2657948C3 (de) | 1982-09-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CH620557A5 (fr) | ||
DE2414917C2 (de) | Leseverstärker | |
DE69027705T2 (de) | Spannungserhöhungsschaltung für dynamische Speicher | |
DE2225428C3 (de) | Inverterstufe mit einem Paar komplementärer Feldeffekttransistoren und damit aufgebautes Schieberegister | |
DE3200894C2 (fr) | ||
DE19525237A1 (de) | Pegelschieberschaltung | |
DE2222521C3 (de) | N-stufiger Ringzähler | |
DE19882086B4 (de) | Verfahren und Vorrichtung zum Implementieren einer adiabatischen Logikfamilie | |
DE69022644T2 (de) | Steuerschaltung für den Datenausgang für eine Halbleiterspeicheranordnung. | |
DE2343128C3 (de) | R-S-Flip-Flop-Schaltung mit komplementären Isolierschicht-Feldeffekt-Transistoren | |
DE2140305B2 (de) | Statisches Schieberegister | |
EP0499673B1 (fr) | Circuit de commande pour un générateur de tension d'un substrat | |
DE2309080C3 (de) | Binäruntersetzerstufe | |
DE2643020A1 (de) | Schmitt-trigger | |
DE3237778A1 (de) | Dynamisches schieberegister | |
DE2743450A1 (de) | Sperrbare zaehlerstufe | |
DE1956485C3 (de) | Schaltungsanordnung für eine bistabile Kippschaltung mit Feldeffekttransistoren | |
DE3343700C2 (fr) | ||
DE2044418A1 (de) | Schieberegister | |
DE3018509A1 (de) | Schieberegister mit latch-schaltung | |
DE2255210B2 (de) | Datenspeicherschaltung | |
DE19905053C2 (de) | Komparatorschaltung | |
DE68927255T2 (de) | Impulsgeneratorschaltung | |
DE1953478A1 (de) | Integrierter logischer Kreis | |
DE3330559C2 (de) | Ausgangsschaltung für eine integrierte Halbleiterschaltung |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PL | Patent ceased |