CA2050781A1 - Methode de fabrication de dispositifs a semiconducteur - Google Patents
Methode de fabrication de dispositifs a semiconducteurInfo
- Publication number
- CA2050781A1 CA2050781A1 CA2050781A CA2050781A CA2050781A1 CA 2050781 A1 CA2050781 A1 CA 2050781A1 CA 2050781 A CA2050781 A CA 2050781A CA 2050781 A CA2050781 A CA 2050781A CA 2050781 A1 CA2050781 A1 CA 2050781A1
- Authority
- CA
- Canada
- Prior art keywords
- layer
- semiconductor device
- preparing semiconductor
- forming
- preparing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000003795 chemical substances by application Substances 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 239000012535 impurity Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/123—Polycrystalline diffuse anneal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/914—Doping
- Y10S438/923—Diffusion through a layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Bipolar Transistors (AREA)
- Weting (AREA)
Applications Claiming Priority (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23589390A JP2854947B2 (ja) | 1990-09-07 | 1990-09-07 | 半導体装置の製造方法 |
JP2-235894 | 1990-09-07 | ||
JP2-235893 | 1990-09-07 | ||
JP23589490A JPH04116923A (ja) | 1990-09-07 | 1990-09-07 | 半導体装置の製造方法 |
JP25724890A JPH04137619A (ja) | 1990-09-28 | 1990-09-28 | 半導体装置の製造方法 |
JP2-257248 | 1990-09-28 | ||
JP2-326052 | 1990-09-28 | ||
JP32605290A JPH04199634A (ja) | 1990-11-29 | 1990-11-29 | 半導体装置の製造方法 |
JP3-20269 | 1991-01-22 | ||
JP2026991A JPH04237118A (ja) | 1991-01-22 | 1991-01-22 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2050781A1 true CA2050781A1 (fr) | 1992-03-08 |
CA2050781C CA2050781C (fr) | 1997-11-18 |
Family
ID=27520217
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002050781A Expired - Fee Related CA2050781C (fr) | 1990-09-07 | 1991-09-06 | Methode de fabrication de dispositifs a semiconducteur |
Country Status (3)
Country | Link |
---|---|
US (4) | US5242858A (fr) |
EP (1) | EP0480178A3 (fr) |
CA (1) | CA2050781C (fr) |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69424717T2 (de) * | 1993-03-17 | 2001-05-31 | Canon Kk | Verbindungsverfahren einer Verdrahtung mit einem Halbleitergebiet und durch dieses Verfahren hergestellte Halbleitervorrichtung |
KR100355938B1 (ko) * | 1993-05-26 | 2002-12-16 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체장치제작방법 |
US6090646A (en) | 1993-05-26 | 2000-07-18 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
JPH07221174A (ja) * | 1993-12-10 | 1995-08-18 | Canon Inc | 半導体装置及びその製造方法 |
JP3621151B2 (ja) * | 1994-06-02 | 2005-02-16 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6326248B1 (en) | 1994-06-02 | 2001-12-04 | Semiconductor Energy Laboratory Co., Ltd. | Process for fabricating semiconductor device |
JPH0869967A (ja) * | 1994-08-26 | 1996-03-12 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
US6331475B1 (en) | 1995-01-12 | 2001-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Method and manufacturing semiconductor device |
TW463378B (en) | 1995-06-01 | 2001-11-11 | Semiconductor Energy Lab | Method of manufacturing semiconductor device |
US6750091B1 (en) | 1996-03-01 | 2004-06-15 | Micron Technology | Diode formation method |
US5792700A (en) * | 1996-05-31 | 1998-08-11 | Micron Technology, Inc. | Semiconductor processing method for providing large grain polysilicon films |
JP3440698B2 (ja) * | 1996-06-24 | 2003-08-25 | ソニー株式会社 | 半導体装置の製造方法 |
JP3450163B2 (ja) * | 1997-09-12 | 2003-09-22 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
DE19842882A1 (de) * | 1998-09-18 | 2000-03-30 | Siemens Ag | Verfahren zum Herstellen eines Dotierungsgebiets |
US5960322A (en) * | 1997-12-19 | 1999-09-28 | Advanced Micro Devices, Inc. | Suppression of boron segregation for shallow source and drain junctions in semiconductors |
US5904536A (en) * | 1998-05-01 | 1999-05-18 | National Semiconductor Corporation | Self aligned poly emitter bipolar technology using damascene technique |
US6207493B1 (en) * | 1998-08-19 | 2001-03-27 | International Business Machines Corporation | Formation of out-diffused bitline by laser anneal |
KR100379136B1 (ko) * | 1998-10-02 | 2003-04-08 | 인터내셔널 비지네스 머신즈 코포레이션 | 반도체 소자 형성 방법과 반도체 소자 |
TW466758B (en) * | 1998-10-26 | 2001-12-01 | United Microelectronics Corp | Manufacturing method of flash memory |
TW399235B (en) * | 1998-12-04 | 2000-07-21 | United Microelectronics Corp | Selective semi-sphere silicon grain manufacturing method |
US6429101B1 (en) | 1999-01-29 | 2002-08-06 | International Business Machines Corporation | Method of forming thermally stable polycrystal to single crystal electrical contact structure |
US6043130A (en) * | 1999-05-17 | 2000-03-28 | National Semiconductor Corporation | Process for forming bipolar transistor compatible with CMOS utilizing tilted ion implanted base |
US6262472B1 (en) | 1999-05-17 | 2001-07-17 | National Semiconductor Corporation | Bipolar transistor compatible with CMOS utilizing tilted ion implanted base |
US7838794B2 (en) | 1999-12-28 | 2010-11-23 | Gsi Group Corporation | Laser-based method and system for removing one or more target link structures |
US6281471B1 (en) | 1999-12-28 | 2001-08-28 | Gsi Lumonics, Inc. | Energy-efficient, laser-based method and system for processing target material |
US20030222324A1 (en) * | 2000-01-10 | 2003-12-04 | Yunlong Sun | Laser systems for passivation or link processing with a set of laser pulses |
US7671295B2 (en) * | 2000-01-10 | 2010-03-02 | Electro Scientific Industries, Inc. | Processing a memory link with a set of at least two laser pulses |
US20060141681A1 (en) * | 2000-01-10 | 2006-06-29 | Yunlong Sun | Processing a memory link with a set of at least two laser pulses |
US6309982B1 (en) * | 2001-03-12 | 2001-10-30 | Chartered Semiconductor Manufacturing Ltd. | Method for minimizing copper diffusion by doping an inorganic dielectric layer with a reducing agent |
US6777645B2 (en) | 2001-03-29 | 2004-08-17 | Gsi Lumonics Corporation | High-speed, precision, laser-based method and system for processing material of one or more targets within a field |
JP2003077854A (ja) * | 2001-09-05 | 2003-03-14 | Mitsubishi Electric Corp | 半導体装置の製造方法および半導体装置 |
US7563695B2 (en) | 2002-03-27 | 2009-07-21 | Gsi Group Corporation | Method and system for high-speed precise laser trimming and scan lens for use therein |
JP3484177B2 (ja) * | 2002-04-26 | 2004-01-06 | 沖電気工業株式会社 | 半導体装置とその製造方法 |
US7687917B2 (en) * | 2002-05-08 | 2010-03-30 | Nec Electronics Corporation | Single damascene structure semiconductor device having silicon-diffused metal wiring layer |
JP4012040B2 (ja) * | 2002-10-31 | 2007-11-21 | キヤノン株式会社 | センタタップ終端回路及びセンタタップ終端回路を有するプリント配線板 |
US6825102B1 (en) * | 2003-09-18 | 2004-11-30 | International Business Machines Corporation | Method of improving the quality of defective semiconductor material |
EP1622435A1 (fr) * | 2004-07-28 | 2006-02-01 | ATOTECH Deutschland GmbH | Méthode de fabrication d'un dispositif par des techniques d'écriture directe |
US8242354B2 (en) * | 2008-12-04 | 2012-08-14 | Sunpower Corporation | Backside contact solar cell with formed polysilicon doped regions |
TWI453939B (zh) | 2010-12-30 | 2014-09-21 | Au Optronics Corp | 太陽能電池及其製作方法 |
KR102272433B1 (ko) * | 2015-06-30 | 2021-07-05 | 엘지전자 주식회사 | 태양 전지 및 이의 제조 방법 |
JP6702268B2 (ja) * | 2017-06-15 | 2020-05-27 | 信越半導体株式会社 | エピタキシャルウェーハの製造方法 |
CN117711917B (zh) * | 2024-02-05 | 2024-05-28 | 中国科学院长春光学精密机械与物理研究所 | 一种多晶硅薄膜及其制备方法 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4041518A (en) * | 1973-02-24 | 1977-08-09 | Hitachi, Ltd. | MIS semiconductor device and method of manufacturing the same |
US4378627A (en) * | 1980-07-08 | 1983-04-05 | International Business Machines Corporation | Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes |
EP0060676B1 (fr) * | 1981-03-11 | 1990-07-25 | Fujitsu Limited | Procédé pour la réalisation d'un dispositif semiconducteur incluant le recuit d'un corps en silicium |
JPS6084825A (ja) * | 1983-10-14 | 1985-05-14 | Seiko Epson Corp | 半導体装置の製造方法 |
FR2566181B1 (fr) * | 1984-06-14 | 1986-08-22 | Commissariat Energie Atomique | Procede d'autopositionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre |
FR2568723B1 (fr) * | 1984-08-03 | 1987-06-05 | Commissariat Energie Atomique | Circuit integre notamment de type mos et son procede de fabrication |
US4708767A (en) * | 1984-10-05 | 1987-11-24 | Signetics Corporation | Method for providing a semiconductor device with planarized contacts |
JPH0824184B2 (ja) * | 1984-11-15 | 1996-03-06 | ソニー株式会社 | 薄膜トランジスタの製造方法 |
US4617066A (en) * | 1984-11-26 | 1986-10-14 | Hughes Aircraft Company | Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing |
US4604150A (en) * | 1985-01-25 | 1986-08-05 | At&T Bell Laboratories | Controlled boron doping of silicon |
US4676847A (en) * | 1985-01-25 | 1987-06-30 | American Telephone And Telegraph Company At&T Bell Laboratories | Controlled boron doping of silicon |
JPS61208829A (ja) * | 1985-03-14 | 1986-09-17 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
FR2582445B1 (fr) * | 1985-05-21 | 1988-04-08 | Efcis | Procede de fabrication de transistors mos a electrodes de siliciure metallique |
US4707456A (en) * | 1985-09-18 | 1987-11-17 | Advanced Micro Devices, Inc. | Method of making a planar structure containing MOS and bipolar transistors |
IT1209682B (it) * | 1985-12-23 | 1989-08-30 | Sgs Microelettronica Spa | Processo per la fabbricazione mediante ricristallizzazione epitassiale di transistori ad effetto di campo a gate isolato con giunzioni a profondita' minima. |
US4697328A (en) * | 1986-04-28 | 1987-10-06 | Rockwell International Corporation | Method of making hardened NMOS sub-micron field effect transistors |
FR2599182B1 (fr) * | 1986-05-21 | 1991-10-31 | Telemecanique Electrique | Procede et dispositif de commande d'un electro-aimant dont l'excitation, par un courant alternatif, provoque la mise en contact de deux pieces |
JPS6310573A (ja) * | 1986-07-02 | 1988-01-18 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
US4939154A (en) * | 1987-03-25 | 1990-07-03 | Seiko Instruments Inc. | Method of fabricating an insulated gate semiconductor device having a self-aligned gate |
US4871684A (en) * | 1987-10-29 | 1989-10-03 | International Business Machines Corporation | Self-aligned polysilicon emitter and contact structure for high performance bipolar transistors |
JPH07118448B2 (ja) * | 1988-02-05 | 1995-12-18 | 松下電子工業株式会社 | 半導体装置の製造方法 |
GB8810973D0 (en) * | 1988-05-10 | 1988-06-15 | Stc Plc | Improvements in integrated circuits |
-
1991
- 1991-09-05 US US07/755,452 patent/US5242858A/en not_active Expired - Fee Related
- 1991-09-06 CA CA002050781A patent/CA2050781C/fr not_active Expired - Fee Related
- 1991-09-06 EP EP19910115132 patent/EP0480178A3/en not_active Withdrawn
-
1993
- 1993-05-27 US US08/067,788 patent/US5476799A/en not_active Expired - Fee Related
-
1995
- 1995-02-17 US US08/390,548 patent/US5597741A/en not_active Expired - Fee Related
- 1995-06-01 US US08/457,149 patent/US5739590A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0480178A3 (en) | 1992-11-19 |
US5476799A (en) | 1995-12-19 |
CA2050781C (fr) | 1997-11-18 |
US5242858A (en) | 1993-09-07 |
US5739590A (en) | 1998-04-14 |
US5597741A (en) | 1997-01-28 |
EP0480178A2 (fr) | 1992-04-15 |
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