CA1087753A - Computer memory interface apparatus - Google Patents

Computer memory interface apparatus

Info

Publication number
CA1087753A
CA1087753A CA272,638A CA272638A CA1087753A CA 1087753 A CA1087753 A CA 1087753A CA 272638 A CA272638 A CA 272638A CA 1087753 A CA1087753 A CA 1087753A
Authority
CA
Canada
Prior art keywords
memory
data
latched
data bus
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA272,638A
Other languages
English (en)
French (fr)
Inventor
Paul S. Feldman
Robert B. Johnson
Chester M. Nibby, Jr.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Application granted granted Critical
Publication of CA1087753A publication Critical patent/CA1087753A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
CA272,638A 1976-03-31 1977-02-25 Computer memory interface apparatus Expired CA1087753A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/672,103 US4060794A (en) 1976-03-31 1976-03-31 Apparatus and method for generating timing signals for latched type memories
US672,103 1976-03-31

Publications (1)

Publication Number Publication Date
CA1087753A true CA1087753A (en) 1980-10-14

Family

ID=24697157

Family Applications (1)

Application Number Title Priority Date Filing Date
CA272,638A Expired CA1087753A (en) 1976-03-31 1977-02-25 Computer memory interface apparatus

Country Status (7)

Country Link
US (1) US4060794A (enExample)
JP (1) JPS52122439A (enExample)
BE (1) BE852980A (enExample)
CA (1) CA1087753A (enExample)
DE (1) DE2711734A1 (enExample)
FR (1) FR2346774A1 (enExample)
GB (1) GB1523579A (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS533120A (en) * 1976-06-30 1978-01-12 Canon Inc Control circuit
US4153941A (en) * 1976-11-11 1979-05-08 Kearney & Trecker Corporation Timing circuit and method for controlling the operation of cyclical devices
FR2376560A1 (fr) * 1976-12-28 1978-07-28 Cii Honeywell Bull Bascule rapide a temps de basculement minimal controle
US4200928A (en) * 1978-01-23 1980-04-29 Sperry Rand Corporation Method and apparatus for weighting the priority of access to variable length data blocks in a multiple-disk drive data storage system having an auxiliary processing device
US4513372A (en) * 1982-11-15 1985-04-23 Data General Corporation Universal memory
US4596004A (en) * 1983-09-14 1986-06-17 International Business Machines Corporation High speed memory with a multiplexed address bus
US4766572A (en) * 1984-12-27 1988-08-23 Nec Corporation Semiconductor memory having a bypassable data output latch
JPS6238593A (ja) * 1985-08-14 1987-02-19 Fujitsu Ltd ダイナミツク型半導体記憶装置
US4751407A (en) * 1986-12-19 1988-06-14 Hughes Aircraft Company Self-timing circuit
US5230067A (en) * 1988-05-11 1993-07-20 Digital Equipment Corporation Bus control circuit for latching and maintaining data independently of timing event on the bus until new data is driven onto
US5956267A (en) * 1997-12-18 1999-09-21 Honeywell Inc Self-aligned wordline keeper and method of manufacture therefor
US6048739A (en) * 1997-12-18 2000-04-11 Honeywell Inc. Method of manufacturing a high density magnetic memory device
US6872993B1 (en) 1999-05-25 2005-03-29 Micron Technology, Inc. Thin film memory device having local and external magnetic shielding
US6392922B1 (en) * 2000-08-14 2002-05-21 Micron Technology, Inc. Passivated magneto-resistive bit structure and passivation method therefor
US6413788B1 (en) 2001-02-28 2002-07-02 Micron Technology, Inc. Keepers for MRAM electrodes
US6485989B1 (en) 2001-08-30 2002-11-26 Micron Technology, Inc. MRAM sense layer isolation
US6783995B2 (en) * 2002-04-30 2004-08-31 Micron Technology, Inc. Protective layers for MRAM devices
US6914805B2 (en) * 2002-08-21 2005-07-05 Micron Technology, Inc. Method for building a magnetic keeper or flux concentrator used for writing magnetic bits on a MRAM device
KR100515053B1 (ko) * 2002-10-02 2005-09-14 삼성전자주식회사 비트라인 클램핑 전압 레벨에 대해 안정적인 독출 동작이가능한 마그네틱 메모리 장치
US7078239B2 (en) 2003-09-05 2006-07-18 Micron Technology, Inc. Integrated circuit structure formed by damascene process
US7112454B2 (en) * 2003-10-14 2006-09-26 Micron Technology, Inc. System and method for reducing shorting in memory cells

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3678473A (en) * 1970-06-04 1972-07-18 Shell Oil Co Read-write circuit for capacitive memory arrays
US3786437A (en) * 1972-01-03 1974-01-15 Honeywell Inf Systems Random access memory system utilizing an inverting cell concept
US3809884A (en) * 1972-11-15 1974-05-07 Honeywell Inf Systems Apparatus and method for a variable memory cycle in a data processing unit
US3848237A (en) * 1973-02-20 1974-11-12 Advanced Memory Syst High speed mos random access read/write memory device
US3940747A (en) * 1973-08-02 1976-02-24 Texas Instruments Incorporated High density, high speed random access read-write memory
US3906464A (en) * 1974-06-03 1975-09-16 Motorola Inc External data control preset system for inverting cell random access memory
US3912947A (en) * 1974-07-05 1975-10-14 Motorola Inc Mos data bus control circuitry
US3969706A (en) * 1974-10-08 1976-07-13 Mostek Corporation Dynamic random access memory misfet integrated circuit
US3959781A (en) * 1974-11-04 1976-05-25 Intel Corporation Semiconductor random access memory
US4158891A (en) * 1975-08-18 1979-06-19 Honeywell Information Systems Inc. Transparent tri state latch
US4019068A (en) * 1975-09-02 1977-04-19 Motorola, Inc. Low power output disable circuit for random access memory
FR2337917A1 (fr) * 1976-01-08 1977-08-05 Mostek Corp Memoire a acces direct en circuit integre
US4038646A (en) * 1976-03-12 1977-07-26 Intel Corporation Dynamic mos ram

Also Published As

Publication number Publication date
DE2711734A1 (de) 1977-10-06
GB1523579A (en) 1978-09-06
FR2346774A1 (fr) 1977-10-28
FR2346774B1 (enExample) 1984-11-16
US4060794A (en) 1977-11-29
JPS52122439A (en) 1977-10-14
BE852980A (fr) 1977-07-18

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Legal Events

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