BR112022010485A2 - Relógio de meia taxa, super-rápido, de malha aberta e recuperação de dados para interfaces c-phy de próxima geração - Google Patents

Relógio de meia taxa, super-rápido, de malha aberta e recuperação de dados para interfaces c-phy de próxima geração

Info

Publication number
BR112022010485A2
BR112022010485A2 BR112022010485A BR112022010485A BR112022010485A2 BR 112022010485 A2 BR112022010485 A2 BR 112022010485A2 BR 112022010485 A BR112022010485 A BR 112022010485A BR 112022010485 A BR112022010485 A BR 112022010485A BR 112022010485 A2 BR112022010485 A2 BR 112022010485A2
Authority
BR
Brazil
Prior art keywords
pulse
watch
super
fast
symbols
Prior art date
Application number
BR112022010485A
Other languages
English (en)
Inventor
Duan Ying
Dixit Abhay
Chou Shih-Wei
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112022010485A2 publication Critical patent/BR112022010485A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4278—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using an embedded synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

RELÓGIO DE MEIA TAXA, SUPER-RÁPIDO, DE MALHA ABERTA E RECUPERAÇÃO DE DADOS PARA INTERFACES C-PHY DE PRÓXIMA GERAÇÃO. A presente invenção refere-se a métodos, aparelhos e sistemas para comunicação através de uma interface multifio e multifásica. Um aparelho de recuperação de relógio tem uma pluralidade de circuitos geração de pulso, um circuito lógico e um multivibrador biestável de atraso. Cada circuito de geração de pulso gera pulsos de transição em resposta a transições em um de três sinais de diferença representativos de uma diferença no estado de sinalização de um par de fios em um barramento de três fios. As transições nos sinais de diferença podem ocorrer nos limites entre os símbolos sequencialmente transmitidos. O primeiro circuito lógico pode fornecer um pulso único em um sinal de combinação em cada fronteira entre pares de símbolos combinando um ou mais pulsos de transição. O multivibrador biestável de atraso é configurado para responder a cada pulso no sinal de combinação alterando o estado de sinalização de um sinal de relógio que é emitido pelo aparelho de recuperação de relógio. Os símbolos podem ser sequencialmente transmitidos pelo barramento de três fios de acordo com um protocolo C-PHY.
BR112022010485A 2019-12-11 2020-10-28 Relógio de meia taxa, super-rápido, de malha aberta e recuperação de dados para interfaces c-phy de próxima geração BR112022010485A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/711,230 US11038666B1 (en) 2019-12-11 2019-12-11 Open-loop, super fast, half-rate clock and data recovery for next generation C-PHY interfaces
PCT/US2020/057687 WO2021118700A1 (en) 2019-12-11 2020-10-28 Open-loop, super fast, half-rate clock and data recovery for next generation c-phy interfaces

Publications (1)

Publication Number Publication Date
BR112022010485A2 true BR112022010485A2 (pt) 2022-09-06

Family

ID=73402193

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112022010485A BR112022010485A2 (pt) 2019-12-11 2020-10-28 Relógio de meia taxa, super-rápido, de malha aberta e recuperação de dados para interfaces c-phy de próxima geração

Country Status (8)

Country Link
US (1) US11038666B1 (pt)
EP (1) EP4073661A1 (pt)
JP (1) JP7358646B2 (pt)
KR (1) KR102420905B1 (pt)
CN (1) CN114787788B (pt)
BR (1) BR112022010485A2 (pt)
TW (1) TWI762012B (pt)
WO (1) WO2021118700A1 (pt)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116684722B (zh) * 2023-07-27 2023-10-20 武汉精立电子技术有限公司 Mipi c-phy信号接收装置、方法及摄像头模组测试系统
KR102694980B1 (ko) 2024-02-08 2024-08-14 주식회사 램쉽 신호수신회로, 신호수신장치 및 수신신호의 클럭복원방법

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012515376A (ja) 2009-01-12 2012-07-05 ラムバス・インコーポレーテッド クロック転送低電力シグナリングシステム
US20140281085A1 (en) 2013-03-15 2014-09-18 Gregory L. Ebert Method, apparatus, system for hybrid lane stalling or no-lock bus architectures
WO2015176244A1 (en) 2014-05-21 2015-11-26 Qualcomm Incorporated Serializer and deserializer for odd ratio parallel data bus
US9548876B2 (en) * 2015-05-06 2017-01-17 Mediatek Inc. Multiple transmitter system and method for controlling impedances of multiple transmitter system
KR20170008077A (ko) * 2015-07-13 2017-01-23 에스케이하이닉스 주식회사 고속 통신을 위한 인터페이스 회로 및 이를 포함하는 시스템
US9496879B1 (en) 2015-09-01 2016-11-15 Qualcomm Incorporated Multiphase clock data recovery for a 3-phase interface
US9485080B1 (en) * 2015-09-01 2016-11-01 Qualcomm Incorporated Multiphase clock data recovery circuit calibration
US9762228B2 (en) 2015-09-15 2017-09-12 Qualcomm Incorporated High-speed programmable clock divider
US10951389B2 (en) 2015-11-30 2021-03-16 Sony Semiconductor Solutions Corporation Phase detector, phase synchronization circuit, and method of controlling phase synchronization circuit
WO2017119183A1 (ja) 2016-01-08 2017-07-13 ソニー株式会社 同期回路および同期回路の制御方法
US10419246B2 (en) * 2016-08-31 2019-09-17 Qualcomm Incorporated C-PHY training pattern for adaptive equalization, adaptive edge tracking and delay calibration
US9735950B1 (en) * 2016-10-18 2017-08-15 Omnivision Technologies, Inc. Burst mode clock data recovery circuit for MIPI C-PHY receivers
AU2017350752A1 (en) * 2016-10-24 2019-03-28 Qualcomm Incorporated Reducing transmitter encoding jitter in a C-PHY interface using multiple clock phases to launch symbols
US10033519B2 (en) * 2016-11-10 2018-07-24 Qualcomm Incorporated C-PHY half-rate clock and data recovery adaptive edge tracking
KR20180061560A (ko) * 2016-11-29 2018-06-08 삼성전자주식회사 통신 환경에 의존하여 지연을 조절하는 전자 회로
KR102629185B1 (ko) * 2016-12-07 2024-01-24 에스케이하이닉스 주식회사 데이터 통신을 위한 수신기
KR102635791B1 (ko) 2016-12-21 2024-02-08 인텔 코포레이션 무선 통신 기술, 장치 및 방법
US10630295B2 (en) 2018-04-23 2020-04-21 Synaptics Incorporated Device and method for detecting signal state transition
US10298381B1 (en) * 2018-04-30 2019-05-21 Qualcomm Incorporated Multiphase clock data recovery with adaptive tracking for a multi-wire, multi-phase interface
US10333690B1 (en) * 2018-05-04 2019-06-25 Qualcomm Incorporated Calibration pattern and duty-cycle distortion correction for clock data recovery in a multi-wire, multi-phase interface
US10263766B1 (en) 2018-06-11 2019-04-16 Qualcomm Incorporated Independent pair 3-phase eye sampling circuit

Also Published As

Publication number Publication date
US11038666B1 (en) 2021-06-15
EP4073661A1 (en) 2022-10-19
JP2022552022A (ja) 2022-12-14
WO2021118700A1 (en) 2021-06-17
CN114787788A (zh) 2022-07-22
KR20220083842A (ko) 2022-06-20
US20210184829A1 (en) 2021-06-17
JP7358646B2 (ja) 2023-10-10
TWI762012B (zh) 2022-04-21
CN114787788B (zh) 2024-08-20
TW202133559A (zh) 2021-09-01
KR102420905B1 (ko) 2022-07-13

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