BR112018004715A2 - sistemas unificados e métodos para comunicação de nó entre chips e interna de chip - Google Patents

sistemas unificados e métodos para comunicação de nó entre chips e interna de chip

Info

Publication number
BR112018004715A2
BR112018004715A2 BR112018004715A BR112018004715A BR112018004715A2 BR 112018004715 A2 BR112018004715 A2 BR 112018004715A2 BR 112018004715 A BR112018004715 A BR 112018004715A BR 112018004715 A BR112018004715 A BR 112018004715A BR 112018004715 A2 BR112018004715 A2 BR 112018004715A2
Authority
BR
Brazil
Prior art keywords
node
chip
chips
message
methods
Prior art date
Application number
BR112018004715A
Other languages
English (en)
Inventor
Alan Wiley George
Leclercq Maxime
Dominic Wietfeldt Richard
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018004715A2 publication Critical patent/BR112018004715A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
    • H04L43/0817—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Environmental & Geological Engineering (AREA)
  • Mathematical Physics (AREA)
  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Bus Control (AREA)

Abstract

são divulgados sistemas e métodos unificados para comunicação de nós entre chips e interna de chip. em um aspecto, um único barramento unificado de baixa velocidade que conecta cada um dos chips dentro de um dispositivo de computação é fornecido. os chips acoplam ao barramento através de uma interface de camada física e portal de acesso associado. o portal de acesso inclui memória que armazena uma tabela de estado resumindo os estados de cada nó na malha de interface. à medida que os nós experimentam mudanças de estado, os nós fornecem atualizações aos portais de acesso locais associados. os portais de acesso locais, em seguida, enviam mensagem, utilizando uma mensagem de escuta, portais de acesso remotos com informações relacionadas às mudanças de estado. quando um primeiro nó está preparando um sinal para um segundo nó, o primeiro nó verifica a tabela de estado no portal de acesso local associado para determinar um estado atual para o segundo nó. com base no status do segundo nó, o primeiro nó pode enviar a mensagem ou tomar outras ações apropriadas.
BR112018004715A 2015-09-10 2016-08-12 sistemas unificados e métodos para comunicação de nó entre chips e interna de chip BR112018004715A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/850,104 US20170075843A1 (en) 2015-09-10 2015-09-10 Unified systems and methods for interchip and intrachip node communication
PCT/US2016/046728 WO2017044247A1 (en) 2015-09-10 2016-08-12 Unified systems and methods for interchip and intrachip node communication

Publications (1)

Publication Number Publication Date
BR112018004715A2 true BR112018004715A2 (pt) 2018-09-25

Family

ID=56787712

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018004715A BR112018004715A2 (pt) 2015-09-10 2016-08-12 sistemas unificados e métodos para comunicação de nó entre chips e interna de chip

Country Status (7)

Country Link
US (2) US20170075843A1 (pt)
EP (2) EP3347823A1 (pt)
JP (1) JP6845224B2 (pt)
KR (1) KR20180050727A (pt)
CN (1) CN108027792B (pt)
BR (1) BR112018004715A2 (pt)
WO (1) WO2017044247A1 (pt)

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CN115460128B (zh) * 2022-11-09 2023-07-07 之江实验室 一种面向多芯粒组合芯片的片上网络仿真系统

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Also Published As

Publication number Publication date
EP4195058A1 (en) 2023-06-14
CN108027792B (zh) 2021-08-20
WO2017044247A1 (en) 2017-03-16
CN108027792A (zh) 2018-05-11
EP3347823A1 (en) 2018-07-18
US20170075843A1 (en) 2017-03-16
JP6845224B2 (ja) 2021-03-17
US11720512B2 (en) 2023-08-08
KR20180050727A (ko) 2018-05-15
US20210326290A1 (en) 2021-10-21
JP2018528540A (ja) 2018-09-27

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]
B12B Appeal against refusal [chapter 12.2 patent gazette]