BR112017017746A2 - drive shaft protection for integrated circuit packages - Google Patents

drive shaft protection for integrated circuit packages

Info

Publication number
BR112017017746A2
BR112017017746A2 BR112017017746-3A BR112017017746A BR112017017746A2 BR 112017017746 A2 BR112017017746 A2 BR 112017017746A2 BR 112017017746 A BR112017017746 A BR 112017017746A BR 112017017746 A2 BR112017017746 A2 BR 112017017746A2
Authority
BR
Brazil
Prior art keywords
substrate
conductive
dielectric
integrated circuit
posts
Prior art date
Application number
BR112017017746-3A
Other languages
English (en)
Portuguese (pt)
Inventor
Fu Jie
Kim Chin-Kwan
Aldrete Manuel
Pravin Shah Milind
Richard Shirley Dwayne
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of BR112017017746A2 publication Critical patent/BR112017017746A2/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Combinations Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
BR112017017746-3A 2015-02-20 2016-02-18 drive shaft protection for integrated circuit packages BR112017017746A2 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562118886P 2015-02-20 2015-02-20
US62/118,886 2015-02-20
US14/859,318 2015-09-20
US14/859,318 US9768108B2 (en) 2015-02-20 2015-09-20 Conductive post protection for integrated circuit packages
PCT/US2016/018504 WO2016134165A1 (en) 2015-02-20 2016-02-18 Conductive post protection for integrated circuit packages

Publications (1)

Publication Number Publication Date
BR112017017746A2 true BR112017017746A2 (en) 2018-04-03

Family

ID=55442905

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112017017746-3A BR112017017746A2 (en) 2015-02-20 2016-02-18 drive shaft protection for integrated circuit packages

Country Status (8)

Country Link
US (1) US9768108B2 (https=)
EP (1) EP3259776A1 (https=)
JP (1) JP6789228B2 (https=)
KR (1) KR102469282B1 (https=)
CN (1) CN107251217B (https=)
BR (1) BR112017017746A2 (https=)
SG (1) SG11201705672XA (https=)
WO (1) WO2016134165A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102397905B1 (ko) 2017-12-27 2022-05-13 삼성전자주식회사 인터포저 기판 및 반도체 패키지
US11791276B2 (en) * 2021-04-08 2023-10-17 Qualcomm Incorporated Package comprising passive component between substrates for improved power distribution network (PDN) performance
WO2023135720A1 (ja) * 2022-01-14 2023-07-20 キヤノン株式会社 モジュールおよび機器
US20250323136A1 (en) * 2024-04-12 2025-10-16 Qualcomm Incorporated Integrated circuit (ic) package including two substrates and vertical interconnects coupling the two substrates, the vertical interconnects comprising a metal ball and metal pin combination to address an increased distance between substrates

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* Cited by examiner, † Cited by third party
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JP2000208698A (ja) * 1999-01-18 2000-07-28 Toshiba Corp 半導体装置
JP2003347501A (ja) * 2002-05-23 2003-12-05 Hitachi Cable Ltd 半導体モジュール及びそれに用いる配線板、ならびに半導体モジュールの製造方法及び配線板の製造方法
JP3973624B2 (ja) * 2003-12-24 2007-09-12 富士通株式会社 高周波デバイス
JP4396839B2 (ja) * 2004-08-11 2010-01-13 日本電気株式会社 キャビティ構造プリント配線板とその製造方法及び実装構造
JP4551321B2 (ja) * 2005-07-21 2010-09-29 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP2007053235A (ja) * 2005-08-18 2007-03-01 Matsushita Electric Ind Co Ltd 基台及び半導体デバイス
JP2007123524A (ja) * 2005-10-27 2007-05-17 Shinko Electric Ind Co Ltd 電子部品内蔵基板
US7632708B2 (en) 2005-12-27 2009-12-15 Tessera, Inc. Microelectronic component with photo-imageable substrate
JP2007194436A (ja) * 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法
JP2009099750A (ja) * 2007-10-17 2009-05-07 Powertech Technology Inc 半導体パッケージ
JP5185062B2 (ja) * 2008-10-21 2013-04-17 パナソニック株式会社 積層型半導体装置及び電子機器
US8623753B1 (en) * 2009-05-28 2014-01-07 Amkor Technology, Inc. Stackable protruding via package and method
JP2011095705A (ja) * 2009-09-30 2011-05-12 Fujifilm Corp 感光性組成物、感光性ソルダーレジスト組成物及び感光性ソルダーレジストフィルム、並びに、永久パターン、その形成方法及びプリント基板
US8169065B2 (en) * 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
US8531021B2 (en) 2011-01-27 2013-09-10 Unimicron Technology Corporation Package stack device and fabrication method thereof
US8476770B2 (en) 2011-07-07 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for forming through vias
US8637992B2 (en) 2011-11-30 2014-01-28 Invensas Corporation Flip chip package for DRAM with two underfill materials
US9362143B2 (en) 2012-05-14 2016-06-07 Micron Technology, Inc. Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related semiconductor device packages
CN103632988B (zh) * 2012-08-28 2016-10-19 宏启胜精密电子(秦皇岛)有限公司 层叠封装结构及其制作方法
CN103681365B (zh) * 2012-08-31 2016-08-10 宏启胜精密电子(秦皇岛)有限公司 层叠封装结构及其制作方法
CN103681359A (zh) * 2012-09-19 2014-03-26 宏启胜精密电子(秦皇岛)有限公司 层叠封装结构及其制作方法
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US9378982B2 (en) 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
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Also Published As

Publication number Publication date
JP2018507556A (ja) 2018-03-15
CN107251217A (zh) 2017-10-13
KR20170113581A (ko) 2017-10-12
WO2016134165A1 (en) 2016-08-25
EP3259776A1 (en) 2017-12-27
US9768108B2 (en) 2017-09-19
CN107251217B (zh) 2021-03-12
KR102469282B1 (ko) 2022-11-18
US20160247754A1 (en) 2016-08-25
JP6789228B2 (ja) 2020-11-25
SG11201705672XA (en) 2017-09-28

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements