AU2017302566B9 - Circuits and methods providing electronic band gap (EBG) structures at memory module electrical coupling - Google Patents

Circuits and methods providing electronic band gap (EBG) structures at memory module electrical coupling Download PDF

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Publication number
AU2017302566B9
AU2017302566B9 AU2017302566A AU2017302566A AU2017302566B9 AU 2017302566 B9 AU2017302566 B9 AU 2017302566B9 AU 2017302566 A AU2017302566 A AU 2017302566A AU 2017302566 A AU2017302566 A AU 2017302566A AU 2017302566 B9 AU2017302566 B9 AU 2017302566B9
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AU
Australia
Prior art keywords
dimm
memory module
circuit board
printed circuit
bus
Prior art date
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Active
Application number
AU2017302566A
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English (en)
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AU2017302566B2 (en
AU2017302566A1 (en
Inventor
Priyatharshan Pathmanathan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
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Publication date
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Publication of AU2017302566A1 publication Critical patent/AU2017302566A1/en
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Publication of AU2017302566B2 publication Critical patent/AU2017302566B2/en
Publication of AU2017302566B9 publication Critical patent/AU2017302566B9/en
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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0236—Electromagnetic band-gap structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H05K1/0225—Single or multiple openings in a shielding, ground or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0275—Fibers and reinforcement materials
    • H05K2201/029—Woven fibrous reinforcement or textile
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10159—Memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Structure Of Printed Boards (AREA)
AU2017302566A 2016-07-28 2017-07-26 Circuits and methods providing electronic band gap (EBG) structures at memory module electrical coupling Active AU2017302566B9 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662367836P 2016-07-28 2016-07-28
US62/367,836 2016-07-28
US15/659,187 US10349513B2 (en) 2016-07-28 2017-07-25 Circuits and methods providing electronic band gap (EBG) structures at memory module electrical coupling
US15/659,187 2017-07-25
PCT/US2017/043844 WO2018022687A1 (en) 2016-07-28 2017-07-26 Circuits and methods providing electronic band gap (ebg) structures at memory module electrical coupling

Publications (3)

Publication Number Publication Date
AU2017302566A1 AU2017302566A1 (en) 2019-01-17
AU2017302566B2 AU2017302566B2 (en) 2020-08-27
AU2017302566B9 true AU2017302566B9 (en) 2020-12-24

Family

ID=61010581

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2017302566A Active AU2017302566B9 (en) 2016-07-28 2017-07-26 Circuits and methods providing electronic band gap (EBG) structures at memory module electrical coupling

Country Status (9)

Country Link
US (1) US10349513B2 (https=)
EP (1) EP3491898B1 (https=)
JP (1) JP6633243B2 (https=)
KR (1) KR102078065B1 (https=)
CN (1) CN109565925B (https=)
AU (1) AU2017302566B9 (https=)
BR (1) BR112019001333B1 (https=)
TW (1) TWI695658B (https=)
WO (1) WO2018022687A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11169940B2 (en) * 2019-02-20 2021-11-09 Qualcomm Incorporated Trace length on printed circuit board (PCB) based on input/output (I/O) operating speed
TWI795644B (zh) * 2020-06-02 2023-03-11 大陸商上海兆芯集成電路有限公司 電子總成
JP7529628B2 (ja) * 2021-07-26 2024-08-06 株式会社日立製作所 プリント配線板及び情報処理装置

Citations (4)

* Cited by examiner, † Cited by third party
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US6184478B1 (en) * 1998-09-30 2001-02-06 Adtec Corporation Printed wiring device with base layer having a grid pattern
US20090037626A1 (en) * 2007-01-31 2009-02-05 Rambus, Inc. Multi-drop bus system
US20150342030A1 (en) * 2014-05-21 2015-11-26 Fujikura Ltd. Printed wiring board
US20160092351A1 (en) * 2013-06-20 2016-03-31 Hitachi, Ltd. Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein

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JP4023166B2 (ja) 2002-01-25 2007-12-19 ソニー株式会社 高周波モジュール用基板及び高周波モジュール
EP1809101B1 (en) * 2004-11-12 2016-11-02 Organoflush B.V. Composition for cold preservation and perfusion of organs
KR20070062633A (ko) * 2005-12-13 2007-06-18 삼성전자주식회사 컴퓨터 시스템의 시스템 기판에 장착되는 인터페이스 소켓장치
JP2007228222A (ja) * 2006-02-23 2007-09-06 Mitsubishi Electric Corp Ｅｂｇマテリアル
US8159413B2 (en) 2006-11-01 2012-04-17 Agency For Science, Technology And Research Double-stacked EBG structure
ITRA20060064A1 (it) * 2006-11-03 2008-05-04 Fondazione Torino Wireless Dispositivo con costante dielettrica modulata per la propagazione di onde elettromagnetiche.
JP2008171834A (ja) * 2007-01-05 2008-07-24 Hitachi Ltd ガラスクロス配線基板
US7839654B2 (en) 2007-02-28 2010-11-23 International Business Machines Corporation Method for ultimate noise isolation in high-speed digital systems on packages and printed circuit boards (PCBS)
US8164006B2 (en) * 2008-03-19 2012-04-24 Samsung Electro-Mechanics Co., Ltd. Electromagnetic bandgap structure and printed circuit board
KR100956891B1 (ko) * 2008-03-19 2010-05-11 삼성전기주식회사 전자기 밴드갭 구조물 및 인쇄회로기판
KR101086856B1 (ko) * 2008-04-16 2011-11-25 주식회사 하이닉스반도체 반도체 집적 회로 모듈 및 이를 구비하는 ｐｃｂ 장치
KR101038236B1 (ko) * 2009-09-16 2011-06-01 삼성전기주식회사 전자기 밴드갭 구조를 구비하는 인쇄회로기판
JP2011108123A (ja) * 2009-11-20 2011-06-02 Elpida Memory Inc 終端基板、メモリシステム及びその反射波抑制方法
US9112272B2 (en) * 2010-08-12 2015-08-18 Feinics Amatech Teoranta Antenna modules for dual interface smart cards, booster antenna configurations, and methods
JP5041108B2 (ja) * 2010-12-03 2012-10-03 株式会社村田製作所 高周波信号線路
JP2013232613A (ja) * 2012-04-05 2013-11-14 Sony Corp 配線基板及び電子機器
JP5694251B2 (ja) 2012-07-27 2015-04-01 株式会社東芝 Ｅｂｇ構造体および回路基板
JP5670392B2 (ja) * 2012-07-27 2015-02-18 株式会社東芝 回路基板
JP6125274B2 (ja) * 2013-02-27 2017-05-10 株式会社東芝 電子回路および電子機器
JP6168943B2 (ja) * 2013-09-20 2017-07-26 株式会社東芝 Ｅｂｇ構造体、半導体デバイスおよび回路基板
WO2017037957A1 (en) 2015-08-31 2017-03-09 Hitachi, Ltd. Information processing device, apparatus and connection wiring board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184478B1 (en) * 1998-09-30 2001-02-06 Adtec Corporation Printed wiring device with base layer having a grid pattern
US20090037626A1 (en) * 2007-01-31 2009-02-05 Rambus, Inc. Multi-drop bus system
US20160092351A1 (en) * 2013-06-20 2016-03-31 Hitachi, Ltd. Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein
US20150342030A1 (en) * 2014-05-21 2015-11-26 Fujikura Ltd. Printed wiring board

Also Published As

Publication number Publication date
CN109565925B (zh) 2022-01-18
JP2019525472A (ja) 2019-09-05
EP3491898A1 (en) 2019-06-05
JP6633243B2 (ja) 2020-01-22
AU2017302566B2 (en) 2020-08-27
EP3491898C0 (en) 2024-09-25
BR112019001333B1 (pt) 2024-01-02
TWI695658B (zh) 2020-06-01
WO2018022687A1 (en) 2018-02-01
US20180035533A1 (en) 2018-02-01
CN109565925A (zh) 2019-04-02
AU2017302566A1 (en) 2019-01-17
US10349513B2 (en) 2019-07-09
TW201804885A (zh) 2018-02-01
BR112019001333A2 (pt) 2019-05-07
KR102078065B1 (ko) 2020-02-17
KR20190029613A (ko) 2019-03-20
EP3491898B1 (en) 2024-09-25

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