AU2001251415A1 - Method and apparatus for manufacturing an interconnect structure - Google Patents

Method and apparatus for manufacturing an interconnect structure

Info

Publication number
AU2001251415A1
AU2001251415A1 AU2001251415A AU5141501A AU2001251415A1 AU 2001251415 A1 AU2001251415 A1 AU 2001251415A1 AU 2001251415 A AU2001251415 A AU 2001251415A AU 5141501 A AU5141501 A AU 5141501A AU 2001251415 A1 AU2001251415 A1 AU 2001251415A1
Authority
AU
Australia
Prior art keywords
manufacturing
interconnect structure
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001251415A
Other languages
English (en)
Inventor
Kartik Ananthanarayanan
George F. Carney
Rina Chowdhury
Rebecca G. Cole
Deborah A. Hagen
Addi B. Mistry
Scott K. Pozder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AU2001251415A1 publication Critical patent/AU2001251415A1/en
Abandoned legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
AU2001251415A 2000-04-18 2001-04-06 Method and apparatus for manufacturing an interconnect structure Abandoned AU2001251415A1 (en)

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US09551312 2000-04-18
US09/551,312 US6429531B1 (en) 2000-04-18 2000-04-18 Method and apparatus for manufacturing an interconnect structure
PCT/US2001/011319 WO2001080303A2 (en) 2000-04-18 2001-04-06 Method and apparatus for manufacturing an interconnect structure

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JP (1) JP5064632B2 (ja)
KR (1) KR100818902B1 (ja)
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US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US7902679B2 (en) * 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
TWI313507B (en) * 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
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US7470997B2 (en) * 2003-07-23 2008-12-30 Megica Corporation Wirebond pad for semiconductor chip or wafer
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
US8067837B2 (en) * 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
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CN1291468C (zh) 2006-12-20
KR20020091210A (ko) 2002-12-05
WO2001080303A3 (en) 2002-02-21
KR100818902B1 (ko) 2008-04-04
JP2004501504A (ja) 2004-01-15
US6429531B1 (en) 2002-08-06
JP5064632B2 (ja) 2012-10-31
TW490775B (en) 2002-06-11
CN1473359A (zh) 2004-02-04

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