ATE65003T1 - Verfahren zur herstellung einer integrierten schaltung aus tantalsiliziden und nach diesem verfahren hergestellte integrierte schaltung. - Google Patents
Verfahren zur herstellung einer integrierten schaltung aus tantalsiliziden und nach diesem verfahren hergestellte integrierte schaltung.Info
- Publication number
- ATE65003T1 ATE65003T1 AT84402348T AT84402348T ATE65003T1 AT E65003 T1 ATE65003 T1 AT E65003T1 AT 84402348 T AT84402348 T AT 84402348T AT 84402348 T AT84402348 T AT 84402348T AT E65003 T1 ATE65003 T1 AT E65003T1
- Authority
- AT
- Austria
- Prior art keywords
- integrated circuit
- manufacture
- tantalum
- tantalum silicide
- manufactured
- Prior art date
Links
Classifications
-
- H10P14/6314—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
-
- H10D64/0112—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/62—Electrodes ohmically coupled to a semiconductor
-
- H10P14/69393—
-
- H10P14/6334—
-
- H10P14/69215—
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/019—Contacts of silicides
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/02—Contacts, special
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/117—Oxidation, selective
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/147—Silicides
Landscapes
- Electrodes Of Semiconductors (AREA)
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Bipolar Transistors (AREA)
- Details Of Connecting Devices For Male And Female Coupling (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8318565A FR2555365B1 (fr) | 1983-11-22 | 1983-11-22 | Procede de fabrication de circuit integre avec connexions de siliciure de tantale et circuit integre realise selon ce procede |
| EP84402348A EP0143700B1 (de) | 1983-11-22 | 1984-11-16 | Verfahren zur Herstellung einer integrierten Schaltung aus Tantalsiliziden und nach diesem Verfahren hergestellte integrierte Schaltung |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE65003T1 true ATE65003T1 (de) | 1991-07-15 |
Family
ID=9294381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT84402348T ATE65003T1 (de) | 1983-11-22 | 1984-11-16 | Verfahren zur herstellung einer integrierten schaltung aus tantalsiliziden und nach diesem verfahren hergestellte integrierte schaltung. |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US4593454A (de) |
| EP (1) | EP0143700B1 (de) |
| JP (1) | JPS60138942A (de) |
| AT (1) | ATE65003T1 (de) |
| DE (1) | DE3484769D1 (de) |
| FR (1) | FR2555365B1 (de) |
Families Citing this family (71)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4716131A (en) * | 1983-11-28 | 1987-12-29 | Nec Corporation | Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film |
| US4727038A (en) * | 1984-08-22 | 1988-02-23 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating semiconductor device |
| US5227316A (en) * | 1985-01-22 | 1993-07-13 | National Semiconductor Corporation | Method of forming self aligned extended base contact for a bipolar transistor having reduced cell size |
| US5061986A (en) * | 1985-01-22 | 1991-10-29 | National Semiconductor Corporation | Self-aligned extended base contact for a bipolar transistor having reduced cell size and improved electrical characteristics |
| US5045916A (en) * | 1985-01-22 | 1991-09-03 | Fairchild Semiconductor Corporation | Extended silicide and external contact technology |
| US4763177A (en) * | 1985-02-19 | 1988-08-09 | Texas Instruments Incorporated | Read only memory with improved channel length isolation and method of forming |
| US4731318A (en) * | 1985-02-26 | 1988-03-15 | Societe Pour L'etude Et La Fabrication Des Circuits Integres Speciaux - E.F.C.I.S. | Integrated circuit comprising MOS transistors having electrodes of metallic silicide and a method of fabrication of said circuit |
| US5100824A (en) * | 1985-04-01 | 1992-03-31 | National Semiconductor Corporation | Method of making small contactless RAM cell |
| US5340762A (en) * | 1985-04-01 | 1994-08-23 | Fairchild Semiconductor Corporation | Method of making small contactless RAM cell |
| FR2581248B1 (fr) * | 1985-04-26 | 1987-05-29 | Efcis | Procede de fabrication de transistors a effet de champ et transistors bipolaires lateraux sur un meme substrat |
| US4804636A (en) * | 1985-05-01 | 1989-02-14 | Texas Instruments Incorporated | Process for making integrated circuits having titanium nitride triple interconnect |
| US4890141A (en) * | 1985-05-01 | 1989-12-26 | Texas Instruments Incorporated | CMOS device with both p+ and n+ gates |
| US4821085A (en) * | 1985-05-01 | 1989-04-11 | Texas Instruments Incorporated | VLSI local interconnect structure |
| CN1012310B (zh) * | 1985-05-01 | 1991-04-03 | 得克萨斯仪器公司 | 超大规模集成电路的局部互连方法及其结构 |
| US4811076A (en) * | 1985-05-01 | 1989-03-07 | Texas Instruments Incorporated | Device and process with doubled capacitors |
| US4975756A (en) * | 1985-05-01 | 1990-12-04 | Texas Instruments Incorporated | SRAM with local interconnect |
| US4657628A (en) * | 1985-05-01 | 1987-04-14 | Texas Instruments Incorporated | Process for patterning local interconnects |
| US4676866A (en) * | 1985-05-01 | 1987-06-30 | Texas Instruments Incorporated | Process to increase tin thickness |
| DE3676781D1 (de) * | 1985-09-13 | 1991-02-14 | Siemens Ag | Integrierte bipolar- und komplementaere mos-transistoren auf einem gemeinsamen substrat enthaltende schaltung und verfahren zu ihrer herstellung. |
| US4782033A (en) * | 1985-11-27 | 1988-11-01 | Siemens Aktiengesellschaft | Process for producing CMOS having doped polysilicon gate by outdiffusion of boron from implanted silicide gate |
| JPS62160745A (ja) * | 1986-01-09 | 1987-07-16 | Fuji Electric Co Ltd | 半導体装置 |
| US4703551A (en) * | 1986-01-24 | 1987-11-03 | Ncr Corporation | Process for forming LDD MOS/CMOS structures |
| JPH07120672B2 (ja) * | 1986-01-28 | 1995-12-20 | 日本電気株式会社 | 半導体装置 |
| US4755479A (en) * | 1986-02-17 | 1988-07-05 | Fujitsu Limited | Manufacturing method of insulated gate field effect transistor using reflowable sidewall spacers |
| US4690730A (en) * | 1986-03-07 | 1987-09-01 | Texas Instruments Incorporated | Oxide-capped titanium silicide formation |
| JPS6312168A (ja) * | 1986-07-03 | 1988-01-19 | Oki Electric Ind Co Ltd | Lddmis型電界効果トランジスタ |
| ATE94688T1 (de) * | 1986-07-04 | 1993-10-15 | Siemens Ag | Integrierte bipolar- und komplementaere mostransistoren auf einem gemeinsamen substrat enthaltende schaltung und verfahren zu ihrer herstellung. |
| US5436496A (en) * | 1986-08-29 | 1995-07-25 | National Semiconductor Corporation | Vertical fuse device |
| WO1988002209A1 (fr) * | 1986-09-19 | 1988-03-24 | Kabushiki Kaisha Komatsu Seisakusho | Dispositif el a film mince |
| US4849344A (en) * | 1986-12-11 | 1989-07-18 | Fairchild Semiconductor Corporation | Enhanced density modified isoplanar process |
| JP2552159B2 (ja) * | 1987-02-02 | 1996-11-06 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
| US4816423A (en) * | 1987-05-01 | 1989-03-28 | Texas Instruments Incorporated | Bicmos process for forming shallow npn emitters and mosfet source/drains |
| US5059546A (en) * | 1987-05-01 | 1991-10-22 | Texas Instruments Incorporated | BICMOS process for forming shallow NPN emitters and mosfet source/drains |
| US4874715A (en) * | 1987-05-20 | 1989-10-17 | Texas Instruments Incorporated | Read only memory with improved channel length control and method of forming |
| JP2659714B2 (ja) * | 1987-07-21 | 1997-09-30 | 株式会社日立製作所 | 半導体集積回路装置 |
| US4755478A (en) * | 1987-08-13 | 1988-07-05 | International Business Machines Corporation | Method of forming metal-strapped polysilicon gate electrode for FET device |
| US4990995A (en) * | 1987-09-08 | 1991-02-05 | General Electric Company | Low reflectance conductor in an integrated circuit |
| US4922311A (en) * | 1987-12-04 | 1990-05-01 | American Telephone And Telegraph Company | Folded extended window field effect transistor |
| US4855247A (en) * | 1988-01-19 | 1989-08-08 | Standard Microsystems Corporation | Process for fabricating self-aligned silicide lightly doped drain MOS devices |
| JPH0687483B2 (ja) * | 1988-02-13 | 1994-11-02 | 株式会社東芝 | 半導体装置 |
| US4951103A (en) * | 1988-06-03 | 1990-08-21 | Texas Instruments, Incorporated | Fast, trench isolated, planar flash EEPROMS with silicided bitlines |
| JPH0294477A (ja) * | 1988-09-30 | 1990-04-05 | Toshiba Corp | 半導体装置及びその製造方法 |
| US4998151A (en) * | 1989-04-13 | 1991-03-05 | General Electric Company | Power field effect devices having small cell size and low contact resistance |
| JPH02273934A (ja) * | 1989-04-17 | 1990-11-08 | Oki Electric Ind Co Ltd | 半導体素子およびその製造方法 |
| US4985740A (en) * | 1989-06-01 | 1991-01-15 | General Electric Company | Power field effect devices having low gate sheet resistance and low ohmic contact resistance |
| JPH03141645A (ja) * | 1989-07-10 | 1991-06-17 | Texas Instr Inc <Ti> | ポリサイドによる局所的相互接続方法とその方法により製造された半導体素子 |
| US5234851A (en) * | 1989-09-05 | 1993-08-10 | General Electric Company | Small cell, low contact assistance rugged power field effect devices and method of fabrication |
| US5119153A (en) * | 1989-09-05 | 1992-06-02 | General Electric Company | Small cell low contact resistance rugged power field effect devices and method of fabrication |
| US5019534A (en) * | 1989-10-31 | 1991-05-28 | Mos Electronics | Process of making self-aligned contact using differential oxidation |
| US5288666A (en) * | 1990-03-21 | 1994-02-22 | Ncr Corporation | Process for forming self-aligned titanium silicide by heating in an oxygen rich environment |
| JP2757927B2 (ja) * | 1990-06-28 | 1998-05-25 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 半導体基板上の隔置されたシリコン領域の相互接続方法 |
| US5034348A (en) * | 1990-08-16 | 1991-07-23 | International Business Machines Corp. | Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit |
| US5387811A (en) * | 1991-01-25 | 1995-02-07 | Nec Corporation | Composite semiconductor device with a particular bipolar structure |
| TW520072U (en) * | 1991-07-08 | 2003-02-01 | Samsung Electronics Co Ltd | A semiconductor device having a multi-layer metal contact |
| US5154514A (en) * | 1991-08-29 | 1992-10-13 | International Business Machines Corporation | On-chip temperature sensor utilizing a Schottky barrier diode structure |
| US5206187A (en) * | 1991-08-30 | 1993-04-27 | Micron Technology, Inc. | Method of processing semiconductor wafers using a contact etch stop |
| US5495121A (en) * | 1991-09-30 | 1996-02-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP2606143B2 (ja) * | 1994-07-22 | 1997-04-30 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| JPH10163311A (ja) * | 1996-11-27 | 1998-06-19 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| US6124189A (en) * | 1997-03-14 | 2000-09-26 | Kabushiki Kaisha Toshiba | Metallization structure and method for a semiconductor device |
| US6255180B1 (en) * | 1998-05-14 | 2001-07-03 | Cypress Semiconductor Corporation | Semiconductor device with outwardly tapered sidewall spacers and method for forming same |
| US6127276A (en) * | 1998-06-02 | 2000-10-03 | United Microelectronics Corp | Method of formation for a via opening |
| US6235630B1 (en) | 1998-08-19 | 2001-05-22 | Micron Technology, Inc. | Silicide pattern structures and methods of fabricating the same |
| US6174762B1 (en) * | 1999-03-02 | 2001-01-16 | International Business Machines Corporation | Salicide device with borderless contact |
| US6461951B1 (en) * | 1999-03-29 | 2002-10-08 | Advanced Micro Devices, Inc. | Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers |
| US6265252B1 (en) | 1999-05-03 | 2001-07-24 | Vlsi Technology, Inc. | Reducing the formation of electrical leakage pathways during manufacture of an electronic device |
| EP1301941A2 (de) * | 2000-07-20 | 2003-04-16 | North Carolina State University | Metallsilikate mit hoher dielektrizitätskonstante, hergestellt durch metall-oberflächenreaktionen |
| US6642131B2 (en) | 2001-06-21 | 2003-11-04 | Matsushita Electric Industrial Co., Ltd. | Method of forming a silicon-containing metal-oxide gate dielectric by depositing a high dielectric constant film on a silicon substrate and diffusing silicon from the substrate into the high dielectric constant film |
| US6894353B2 (en) * | 2002-07-31 | 2005-05-17 | Freescale Semiconductor, Inc. | Capped dual metal gate transistors for CMOS process and method for making the same |
| US20070262363A1 (en) * | 2003-02-28 | 2007-11-15 | Board Of Regents, University Of Texas System | Low temperature fabrication of discrete silicon-containing substrates and devices |
| US20160276156A1 (en) * | 2015-03-16 | 2016-09-22 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing process thereof |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1923265B2 (de) * | 1969-05-07 | 1972-06-22 | Licentia Patent Verwaltungs GmbH, 6000 Frankfurt | Verfahren zum herstellen eines feldeffekttransistors mit isolierter steuerelektrode |
| US3967371A (en) * | 1970-01-06 | 1976-07-06 | Sescosem- Societe Europeenne Des Semi-Conducteurs Et De Microelectronique | Methods of manufacturing multilayer interconnections for integrated circuits and to integrated circuits utilizing said method |
| GB1503017A (en) * | 1974-02-28 | 1978-03-08 | Tokyo Shibaura Electric Co | Method of manufacturing semiconductor devices |
| US3986897A (en) * | 1974-09-30 | 1976-10-19 | Motorola, Inc. | Aluminum treatment to prevent hillocking |
| NL7510903A (nl) * | 1975-09-17 | 1977-03-21 | Philips Nv | Werkwijze voor het vervaardigen van een halfgelei- derinrichting, en inrichting vervaardigd volgens de werkwijze. |
| JPS5317393A (en) * | 1976-07-31 | 1978-02-17 | Mitsubishi Heavy Ind Ltd | Commodities delivery detector |
| US4332839A (en) * | 1978-12-29 | 1982-06-01 | Bell Telephone Laboratories, Incorporated | Method for making integrated semiconductor circuit structure with formation of Ti or Ta silicide |
| US4329706A (en) * | 1979-03-01 | 1982-05-11 | International Business Machines Corporation | Doped polysilicon silicide semiconductor integrated circuit interconnections |
| US4305200A (en) * | 1979-11-06 | 1981-12-15 | Hewlett-Packard Company | Method of forming self-registering source, drain, and gate contacts for FET transistor structures |
| US4384301A (en) * | 1979-11-07 | 1983-05-17 | Texas Instruments Incorporated | High performance submicron metal-oxide-semiconductor field effect transistor device structure |
| NL188432C (nl) * | 1980-12-26 | 1992-06-16 | Nippon Telegraph & Telephone | Werkwijze voor het vervaardigen van een mosfet. |
| JPS57176746A (en) * | 1981-04-21 | 1982-10-30 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor integrated circuit and manufacture thereof |
| US4374700A (en) * | 1981-05-29 | 1983-02-22 | Texas Instruments Incorporated | Method of manufacturing silicide contacts for CMOS devices |
| JPH0722183B2 (ja) * | 1981-10-09 | 1995-03-08 | 富士通株式会社 | 半導体装置用誘電体層の製造方法 |
| DE3211761A1 (de) * | 1982-03-30 | 1983-10-06 | Siemens Ag | Verfahren zum herstellen von integrierten mos-feldeffekttransistorschaltungen in siliziumgate-technologie mit silizid beschichteten diffusionsgebieten als niederohmige leiterbahnen |
| US4471524A (en) * | 1982-06-01 | 1984-09-18 | At&T Bell Laboratories | Method for manufacturing an insulated gate field effect transistor device |
| US4432035A (en) * | 1982-06-11 | 1984-02-14 | International Business Machines Corp. | Method of making high dielectric constant insulators and capacitors using same |
| US4574467A (en) * | 1983-08-31 | 1986-03-11 | Solid State Scientific, Inc. | N- well CMOS process on a P substrate with double field guard rings and a PMOS buried channel |
-
1983
- 1983-11-22 FR FR8318565A patent/FR2555365B1/fr not_active Expired
-
1984
- 1984-11-16 EP EP84402348A patent/EP0143700B1/de not_active Expired - Lifetime
- 1984-11-16 DE DE8484402348T patent/DE3484769D1/de not_active Expired - Lifetime
- 1984-11-16 AT AT84402348T patent/ATE65003T1/de not_active IP Right Cessation
- 1984-11-20 US US06/673,425 patent/US4593454A/en not_active Expired - Lifetime
- 1984-11-22 JP JP59246368A patent/JPS60138942A/ja active Granted
-
1986
- 1986-02-26 US US06/833,845 patent/US4714951A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| FR2555365A1 (fr) | 1985-05-24 |
| US4714951A (en) | 1987-12-22 |
| US4593454A (en) | 1986-06-10 |
| FR2555365B1 (fr) | 1986-08-29 |
| JPS60138942A (ja) | 1985-07-23 |
| EP0143700B1 (de) | 1991-07-03 |
| JPH0418702B2 (de) | 1992-03-27 |
| EP0143700A3 (en) | 1985-09-18 |
| DE3484769D1 (de) | 1991-08-08 |
| EP0143700A2 (de) | 1985-06-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |