ATE552611T1 - Verfahren zur erzeugung von dünnen sgoi-wafern mit hoher relaxations- und niedriger stapelfehlerdefektdichte - Google Patents

Verfahren zur erzeugung von dünnen sgoi-wafern mit hoher relaxations- und niedriger stapelfehlerdefektdichte

Info

Publication number
ATE552611T1
ATE552611T1 AT04703076T AT04703076T ATE552611T1 AT E552611 T1 ATE552611 T1 AT E552611T1 AT 04703076 T AT04703076 T AT 04703076T AT 04703076 T AT04703076 T AT 04703076T AT E552611 T1 ATE552611 T1 AT E552611T1
Authority
AT
Austria
Prior art keywords
defect density
sige
sgoi
stacking fault
high relaxation
Prior art date
Application number
AT04703076T
Other languages
English (en)
Inventor
Huajie Chen
Stephen Bedell
Devendra Sadana
Dan Mocuta
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE552611T1 publication Critical patent/ATE552611T1/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/0245Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
AT04703076T 2004-01-16 2004-01-16 Verfahren zur erzeugung von dünnen sgoi-wafern mit hoher relaxations- und niedriger stapelfehlerdefektdichte ATE552611T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2004/001555 WO2005078786A1 (en) 2004-01-16 2004-01-16 Method of forming thin sgoi wafers with high relaxation and low stacking fault defect density

Publications (1)

Publication Number Publication Date
ATE552611T1 true ATE552611T1 (de) 2012-04-15

Family

ID=34862309

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04703076T ATE552611T1 (de) 2004-01-16 2004-01-16 Verfahren zur erzeugung von dünnen sgoi-wafern mit hoher relaxations- und niedriger stapelfehlerdefektdichte

Country Status (7)

Country Link
US (1) US7550370B2 (de)
EP (1) EP1709671B1 (de)
JP (1) JP4686480B2 (de)
KR (1) KR100925310B1 (de)
CN (1) CN100459072C (de)
AT (1) ATE552611T1 (de)
WO (1) WO2005078786A1 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
US7550370B2 (en) * 2004-01-16 2009-06-23 International Business Machines Corporation Method of forming thin SGOI wafers with high relaxation and low stacking fault defect density
JP2006080278A (ja) * 2004-09-09 2006-03-23 Toshiba Ceramics Co Ltd 歪みシリコンウエハおよびその製造方法
EP1763069B1 (de) 2005-09-07 2016-04-13 Soitec Herstellungsverfahren einer Heterostruktur
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
US20070154637A1 (en) * 2005-12-19 2007-07-05 Rohm And Haas Electronic Materials Llc Organometallic composition
DE102006020825A1 (de) * 2006-05-04 2007-11-08 Siltronic Ag Verfahren zur Herstellung einer Schichtenstruktur
JP5018066B2 (ja) * 2006-12-19 2012-09-05 信越半導体株式会社 歪Si基板の製造方法
WO2010013325A1 (ja) * 2008-07-30 2010-02-04 株式会社ニレコ 分光測光装置
CN101388331B (zh) * 2008-10-31 2010-08-25 上海新傲科技股份有限公司 制备绝缘体上硅材料的内热氧化方法
DE102009010883B4 (de) * 2009-02-27 2011-05-26 Amd Fab 36 Limited Liability Company & Co. Kg Einstellen eines nicht-Siliziumanteils in einer Halbleiterlegierung während der FET-Transistorherstellung mittels eines Zwischenoxidationsprozesses
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
US20110086444A1 (en) * 2009-10-14 2011-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Process for producing substrates free of patterns using an alpha stepper to ensure results
US8703551B2 (en) * 2011-05-06 2014-04-22 Globalfoundries Inc. Process flow to reduce hole defects in P-active regions and to reduce across-wafer threshold voltage scatter
JP2013055231A (ja) * 2011-09-05 2013-03-21 Shin Etsu Handotai Co Ltd エピタキシャルウェーハの製造方法
CN102290369B (zh) * 2011-09-22 2013-12-04 中国科学院上海微系统与信息技术研究所 一种薄goi晶片及其制备方法
US8883598B2 (en) * 2012-03-05 2014-11-11 Taiwan Semiconductor Manufacturing Co., Ltd. Thin capped channel layers of semiconductor devices and methods of forming the same
CN104078407B (zh) * 2013-03-29 2018-12-04 济南晶正电子科技有限公司 薄膜和制造薄膜的方法
US9324843B2 (en) 2014-09-05 2016-04-26 International Business Machines Corporation High germanium content silicon germanium fins
KR102259328B1 (ko) 2014-10-10 2021-06-02 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9608067B2 (en) * 2015-03-30 2017-03-28 International Business Machines Corporation Hybrid aspect ratio trapping
KR102326316B1 (ko) 2015-04-10 2021-11-16 삼성전자주식회사 반도체 소자의 제조 방법
CN106257631A (zh) * 2015-06-18 2016-12-28 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法、电子装置
US9818761B2 (en) 2015-06-25 2017-11-14 International Business Machines Corporation Selective oxidation for making relaxed silicon germanium on insulator structures
US9362311B1 (en) 2015-07-24 2016-06-07 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
US9530669B1 (en) * 2015-11-30 2016-12-27 International Business Machines Corporation Method of making a semiconductor device having a semiconductor material on a relaxed semiconductor including replacing a strained, selective etchable material, with a low density dielectric in a cavity
US9570298B1 (en) 2015-12-09 2017-02-14 International Business Machines Corporation Localized elastic strain relaxed buffer
FR3061803B1 (fr) * 2017-01-11 2019-08-16 Soitec Substrat pour capteur d'image de type face avant et procede de fabrication d'un tel substrat
FR3061988B1 (fr) 2017-01-13 2019-11-01 Soitec Procede de lissage de surface d'un substrat semiconducteur sur isolant
CN111551762A (zh) * 2020-05-14 2020-08-18 中国电子科技集团公司第二十四研究所 一种基于原位腐蚀的锗外延层缺陷密度检测方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4409260A (en) * 1979-08-15 1983-10-11 Hughes Aircraft Company Process for low-temperature surface layer oxidation of a semiconductor substrate
US5298457A (en) * 1993-07-01 1994-03-29 G. I. Corporation Method of making semiconductor devices using epitaxial techniques to form Si/Si-Ge interfaces and inverting the material
JP3361922B2 (ja) * 1994-09-13 2003-01-07 株式会社東芝 半導体装置
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US6066576A (en) * 1997-06-04 2000-05-23 Micron Technology, Inc. Method for forming oxide using high pressure
FR2773177B1 (fr) 1997-12-29 2000-03-17 France Telecom Procede d'obtention d'une couche de germanium ou silicium monocristallin sur un substrat de silicium ou germanium monocristallin, respectivement, et produits multicouches obtenus
JP3884203B2 (ja) * 1998-12-24 2007-02-21 株式会社東芝 半導体装置の製造方法
US6346453B1 (en) 2000-01-27 2002-02-12 Sige Microsystems Inc. Method of producing a SI-GE base heterojunction bipolar device
JP2001351869A (ja) * 2000-06-09 2001-12-21 Mitsubishi Materials Silicon Corp シリコンウェーハおよびその製造方法
US6524935B1 (en) 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
US6890835B1 (en) * 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
TWI313059B (de) * 2000-12-08 2009-08-01 Sony Corporatio
US6448152B1 (en) * 2001-02-20 2002-09-10 Silicon Genesis Corporation Method and system for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer
US6646322B2 (en) 2001-03-02 2003-11-11 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
JP2002289533A (ja) * 2001-03-26 2002-10-04 Kentaro Sawano 半導体表面の研磨方法、半導体デバイスの製造方法および半導体デバイス
US6660607B2 (en) * 2001-03-30 2003-12-09 International Business Machines Corporation Method for fabricating heterojunction bipolar transistors
US20020168802A1 (en) * 2001-05-14 2002-11-14 Hsu Sheng Teng SiGe/SOI CMOS and method of making the same
US6855436B2 (en) * 2003-05-30 2005-02-15 International Business Machines Corporation Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal
US6593625B2 (en) 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
JP4378904B2 (ja) * 2001-09-28 2009-12-09 株式会社Sumco 半導体基板の製造方法及び電界効果型トランジスタの製造方法
JP2003158250A (ja) * 2001-10-30 2003-05-30 Sharp Corp SiGe/SOIのCMOSおよびその製造方法
US6805962B2 (en) 2002-01-23 2004-10-19 International Business Machines Corporation Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications
US7026249B2 (en) * 2003-05-30 2006-04-11 International Business Machines Corporation SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth
JP2004363199A (ja) * 2003-06-02 2004-12-24 Sumitomo Mitsubishi Silicon Corp 半導体基板の製造方法
JP4037803B2 (ja) * 2003-07-24 2008-01-23 株式会社東芝 Sgoi基板の製造方法
US7550370B2 (en) * 2004-01-16 2009-06-23 International Business Machines Corporation Method of forming thin SGOI wafers with high relaxation and low stacking fault defect density
US7235812B2 (en) * 2004-09-13 2007-06-26 International Business Machines Corporation Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques

Also Published As

Publication number Publication date
US20070128840A1 (en) 2007-06-07
CN100459072C (zh) 2009-02-04
JP2007518264A (ja) 2007-07-05
EP1709671A1 (de) 2006-10-11
KR20060123471A (ko) 2006-12-01
CN1906742A (zh) 2007-01-31
JP4686480B2 (ja) 2011-05-25
US7550370B2 (en) 2009-06-23
EP1709671B1 (de) 2012-04-04
KR100925310B1 (ko) 2009-11-04
WO2005078786A1 (en) 2005-08-25
EP1709671A4 (de) 2010-06-16

Similar Documents

Publication Publication Date Title
ATE552611T1 (de) Verfahren zur erzeugung von dünnen sgoi-wafern mit hoher relaxations- und niedriger stapelfehlerdefektdichte
US10985049B2 (en) Manufacturing method of smoothing a semiconductor surface
JP5068635B2 (ja) 半導体ヘテロ構造を作製する方法
JP2005203756A (ja) 水素注入による膜移動および緩和による絶縁体上の歪みシリコン
JP2010016390A (ja) グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス
JP2008141206A6 (ja) 半導体ヘテロ構造を作製する方法
US7022593B2 (en) SiGe rectification process
TWI699832B (zh) 製造絕緣體覆矽鍺之方法
CN109155278B (zh) 制造应变绝缘体上半导体衬底的方法
JP2008153671A (ja) 半導体ヘテロ構造
JP2006524426A5 (de)
JP2005109448A (ja) 層転位によりガラス上に緩和したシリコンゲルマニウムを作製する方法
JP2006191112A (ja) シリコン−ゲルマニウム層を備えた半導体ウェハ及びその製造方法
US20090087961A1 (en) Process for fabricating semiconductor structures useful for the production of semiconductor-on-insulator substrates, and its applications
JP2010525598A (ja) 複合材料ウェハの製造方法および対応する複合材料ウェハ
KR20070108063A (ko) 층 구조물의 제조 방법
KR100797210B1 (ko) 다층구조의 제조방법
US20180005872A1 (en) Preparation of silicon-germanium-on-insulator structures
CN111739788A (zh) 制备锗硅半导体材料层的方法、锗硅半导体材料层
US8309437B2 (en) (110) oriented silicon substrate and a bonded pair of substrates comprising said (110) oriented silicon substrate
JP5031190B2 (ja) 歪みSi層を有する半導体ウェーハの製造方法
JP5643488B2 (ja) 低応力膜を備えたsoiウェーハの製造方法
JP2009059939A (ja) 歪み緩和シリコンゲルマニウム薄膜及びその製造方法