ATE552611T1 - Verfahren zur erzeugung von dünnen sgoi-wafern mit hoher relaxations- und niedriger stapelfehlerdefektdichte - Google Patents
Verfahren zur erzeugung von dünnen sgoi-wafern mit hoher relaxations- und niedriger stapelfehlerdefektdichteInfo
- Publication number
- ATE552611T1 ATE552611T1 AT04703076T AT04703076T ATE552611T1 AT E552611 T1 ATE552611 T1 AT E552611T1 AT 04703076 T AT04703076 T AT 04703076T AT 04703076 T AT04703076 T AT 04703076T AT E552611 T1 ATE552611 T1 AT E552611T1
- Authority
- AT
- Austria
- Prior art keywords
- defect density
- sige
- sgoi
- stacking fault
- high relaxation
- Prior art date
Links
- 229910000577 Silicon-germanium Inorganic materials 0.000 title abstract 11
- 230000007547 defect Effects 0.000 title abstract 4
- 238000004519 manufacturing process Methods 0.000 title 1
- 235000012431 wafers Nutrition 0.000 title 1
- 238000000034 method Methods 0.000 abstract 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 abstract 2
- 239000001257 hydrogen Substances 0.000 abstract 2
- 229910052739 hydrogen Inorganic materials 0.000 abstract 2
- 238000011065 in-situ storage Methods 0.000 abstract 2
- 230000003647 oxidation Effects 0.000 abstract 2
- 238000007254 oxidation reaction Methods 0.000 abstract 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 238000000407 epitaxy Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 abstract 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 abstract 1
- 229910052986 germanium hydride Inorganic materials 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 239000012212 insulator Substances 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2004/001555 WO2005078786A1 (en) | 2004-01-16 | 2004-01-16 | Method of forming thin sgoi wafers with high relaxation and low stacking fault defect density |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE552611T1 true ATE552611T1 (de) | 2012-04-15 |
Family
ID=34862309
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT04703076T ATE552611T1 (de) | 2004-01-16 | 2004-01-16 | Verfahren zur erzeugung von dünnen sgoi-wafern mit hoher relaxations- und niedriger stapelfehlerdefektdichte |
Country Status (7)
Country | Link |
---|---|
US (1) | US7550370B2 (de) |
EP (1) | EP1709671B1 (de) |
JP (1) | JP4686480B2 (de) |
KR (1) | KR100925310B1 (de) |
CN (1) | CN100459072C (de) |
AT (1) | ATE552611T1 (de) |
WO (1) | WO2005078786A1 (de) |
Families Citing this family (30)
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FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
US7550370B2 (en) * | 2004-01-16 | 2009-06-23 | International Business Machines Corporation | Method of forming thin SGOI wafers with high relaxation and low stacking fault defect density |
JP2006080278A (ja) * | 2004-09-09 | 2006-03-23 | Toshiba Ceramics Co Ltd | 歪みシリコンウエハおよびその製造方法 |
EP1763069B1 (de) | 2005-09-07 | 2016-04-13 | Soitec | Herstellungsverfahren einer Heterostruktur |
FR2891281B1 (fr) * | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
US20070154637A1 (en) * | 2005-12-19 | 2007-07-05 | Rohm And Haas Electronic Materials Llc | Organometallic composition |
DE102006020825A1 (de) * | 2006-05-04 | 2007-11-08 | Siltronic Ag | Verfahren zur Herstellung einer Schichtenstruktur |
JP5018066B2 (ja) * | 2006-12-19 | 2012-09-05 | 信越半導体株式会社 | 歪Si基板の製造方法 |
WO2010013325A1 (ja) * | 2008-07-30 | 2010-02-04 | 株式会社ニレコ | 分光測光装置 |
CN101388331B (zh) * | 2008-10-31 | 2010-08-25 | 上海新傲科技股份有限公司 | 制备绝缘体上硅材料的内热氧化方法 |
DE102009010883B4 (de) * | 2009-02-27 | 2011-05-26 | Amd Fab 36 Limited Liability Company & Co. Kg | Einstellen eines nicht-Siliziumanteils in einer Halbleiterlegierung während der FET-Transistorherstellung mittels eines Zwischenoxidationsprozesses |
FR2947098A1 (fr) | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
US20110086444A1 (en) * | 2009-10-14 | 2011-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for producing substrates free of patterns using an alpha stepper to ensure results |
US8703551B2 (en) * | 2011-05-06 | 2014-04-22 | Globalfoundries Inc. | Process flow to reduce hole defects in P-active regions and to reduce across-wafer threshold voltage scatter |
JP2013055231A (ja) * | 2011-09-05 | 2013-03-21 | Shin Etsu Handotai Co Ltd | エピタキシャルウェーハの製造方法 |
CN102290369B (zh) * | 2011-09-22 | 2013-12-04 | 中国科学院上海微系统与信息技术研究所 | 一种薄goi晶片及其制备方法 |
US8883598B2 (en) * | 2012-03-05 | 2014-11-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thin capped channel layers of semiconductor devices and methods of forming the same |
CN104078407B (zh) * | 2013-03-29 | 2018-12-04 | 济南晶正电子科技有限公司 | 薄膜和制造薄膜的方法 |
US9324843B2 (en) | 2014-09-05 | 2016-04-26 | International Business Machines Corporation | High germanium content silicon germanium fins |
KR102259328B1 (ko) | 2014-10-10 | 2021-06-02 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US9608067B2 (en) * | 2015-03-30 | 2017-03-28 | International Business Machines Corporation | Hybrid aspect ratio trapping |
KR102326316B1 (ko) | 2015-04-10 | 2021-11-16 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
CN106257631A (zh) * | 2015-06-18 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法、电子装置 |
US9818761B2 (en) | 2015-06-25 | 2017-11-14 | International Business Machines Corporation | Selective oxidation for making relaxed silicon germanium on insulator structures |
US9362311B1 (en) | 2015-07-24 | 2016-06-07 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
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FR3061803B1 (fr) * | 2017-01-11 | 2019-08-16 | Soitec | Substrat pour capteur d'image de type face avant et procede de fabrication d'un tel substrat |
FR3061988B1 (fr) | 2017-01-13 | 2019-11-01 | Soitec | Procede de lissage de surface d'un substrat semiconducteur sur isolant |
CN111551762A (zh) * | 2020-05-14 | 2020-08-18 | 中国电子科技集团公司第二十四研究所 | 一种基于原位腐蚀的锗外延层缺陷密度检测方法 |
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US7026249B2 (en) * | 2003-05-30 | 2006-04-11 | International Business Machines Corporation | SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth |
JP2004363199A (ja) * | 2003-06-02 | 2004-12-24 | Sumitomo Mitsubishi Silicon Corp | 半導体基板の製造方法 |
JP4037803B2 (ja) * | 2003-07-24 | 2008-01-23 | 株式会社東芝 | Sgoi基板の製造方法 |
US7550370B2 (en) * | 2004-01-16 | 2009-06-23 | International Business Machines Corporation | Method of forming thin SGOI wafers with high relaxation and low stacking fault defect density |
US7235812B2 (en) * | 2004-09-13 | 2007-06-26 | International Business Machines Corporation | Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques |
-
2004
- 2004-01-16 US US10/597,066 patent/US7550370B2/en not_active Expired - Fee Related
- 2004-01-16 AT AT04703076T patent/ATE552611T1/de active
- 2004-01-16 WO PCT/US2004/001555 patent/WO2005078786A1/en active Application Filing
- 2004-01-16 CN CNB2004800405182A patent/CN100459072C/zh not_active Expired - Fee Related
- 2004-01-16 JP JP2006549218A patent/JP4686480B2/ja not_active Expired - Fee Related
- 2004-01-16 EP EP04703076A patent/EP1709671B1/de not_active Expired - Lifetime
- 2004-01-16 KR KR1020067013849A patent/KR100925310B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
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US20070128840A1 (en) | 2007-06-07 |
CN100459072C (zh) | 2009-02-04 |
JP2007518264A (ja) | 2007-07-05 |
EP1709671A1 (de) | 2006-10-11 |
KR20060123471A (ko) | 2006-12-01 |
CN1906742A (zh) | 2007-01-31 |
JP4686480B2 (ja) | 2011-05-25 |
US7550370B2 (en) | 2009-06-23 |
EP1709671B1 (de) | 2012-04-04 |
KR100925310B1 (ko) | 2009-11-04 |
WO2005078786A1 (en) | 2005-08-25 |
EP1709671A4 (de) | 2010-06-16 |
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